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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (C) STMicroelectronics 2017
0004  * Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics.
0005  */
0006 
0007 #include <linux/clk.h>
0008 #include <linux/clk-provider.h>
0009 #include <linux/err.h>
0010 #include <linux/io.h>
0011 #include <linux/mfd/syscon.h>
0012 #include <linux/of.h>
0013 #include <linux/of_address.h>
0014 #include <linux/slab.h>
0015 #include <linux/spinlock.h>
0016 #include <linux/regmap.h>
0017 
0018 #include <dt-bindings/clock/stm32h7-clks.h>
0019 
0020 /* Reset Clock Control Registers */
0021 #define RCC_CR      0x00
0022 #define RCC_CFGR    0x10
0023 #define RCC_D1CFGR  0x18
0024 #define RCC_D2CFGR  0x1C
0025 #define RCC_D3CFGR  0x20
0026 #define RCC_PLLCKSELR   0x28
0027 #define RCC_PLLCFGR 0x2C
0028 #define RCC_PLL1DIVR    0x30
0029 #define RCC_PLL1FRACR   0x34
0030 #define RCC_PLL2DIVR    0x38
0031 #define RCC_PLL2FRACR   0x3C
0032 #define RCC_PLL3DIVR    0x40
0033 #define RCC_PLL3FRACR   0x44
0034 #define RCC_D1CCIPR 0x4C
0035 #define RCC_D2CCIP1R    0x50
0036 #define RCC_D2CCIP2R    0x54
0037 #define RCC_D3CCIPR 0x58
0038 #define RCC_BDCR    0x70
0039 #define RCC_CSR     0x74
0040 #define RCC_AHB3ENR 0xD4
0041 #define RCC_AHB1ENR 0xD8
0042 #define RCC_AHB2ENR 0xDC
0043 #define RCC_AHB4ENR 0xE0
0044 #define RCC_APB3ENR 0xE4
0045 #define RCC_APB1LENR    0xE8
0046 #define RCC_APB1HENR    0xEC
0047 #define RCC_APB2ENR 0xF0
0048 #define RCC_APB4ENR 0xF4
0049 
0050 static DEFINE_SPINLOCK(stm32rcc_lock);
0051 
0052 static void __iomem *base;
0053 static struct clk_hw **hws;
0054 
0055 /* System clock parent */
0056 static const char * const sys_src[] = {
0057     "hsi_ck", "csi_ck", "hse_ck", "pll1_p" };
0058 
0059 static const char * const tracein_src[] = {
0060     "hsi_ck", "csi_ck", "hse_ck", "pll1_r" };
0061 
0062 static const char * const per_src[] = {
0063     "hsi_ker", "csi_ker", "hse_ck", "disabled" };
0064 
0065 static const char * const pll_src[] = {
0066     "hsi_ck", "csi_ck", "hse_ck", "no clock" };
0067 
0068 static const char * const sdmmc_src[] = { "pll1_q", "pll2_r" };
0069 
0070 static const char * const dsi_src[] = { "ck_dsi_phy", "pll2_q" };
0071 
0072 static const char * const qspi_src[] = {
0073     "hclk", "pll1_q", "pll2_r", "per_ck" };
0074 
0075 static const char * const fmc_src[] = {
0076     "hclk", "pll1_q", "pll2_r", "per_ck" };
0077 
0078 /* Kernel clock parent */
0079 static const char * const swp_src[] = { "pclk1", "hsi_ker" };
0080 
0081 static const char * const fdcan_src[] = { "hse_ck", "pll1_q", "pll2_q" };
0082 
0083 static const char * const dfsdm1_src[] = { "pclk2", "sys_ck" };
0084 
0085 static const char * const spdifrx_src[] = {
0086     "pll1_q", "pll2_r", "pll3_r", "hsi_ker" };
0087 
0088 static const char *spi_src1[5] = {
0089     "pll1_q", "pll2_p", "pll3_p", NULL, "per_ck" };
0090 
0091 static const char * const spi_src2[] = {
0092     "pclk2", "pll2_q", "pll3_q", "hsi_ker", "csi_ker", "hse_ck" };
0093 
0094 static const char * const spi_src3[] = {
0095     "pclk4", "pll2_q", "pll3_q", "hsi_ker", "csi_ker", "hse_ck" };
0096 
0097 static const char * const lptim_src1[] = {
0098     "pclk1", "pll2_p", "pll3_r", "lse_ck", "lsi_ck", "per_ck" };
0099 
0100 static const char * const lptim_src2[] = {
0101     "pclk4", "pll2_p", "pll3_r", "lse_ck", "lsi_ck", "per_ck" };
0102 
0103 static const char * const cec_src[] = {"lse_ck", "lsi_ck", "csi_ker_div122" };
0104 
0105 static const char * const usbotg_src[] = {"pll1_q", "pll3_q", "rc48_ck" };
0106 
0107 /* i2c 1,2,3 src */
0108 static const char * const i2c_src1[] = {
0109     "pclk1", "pll3_r", "hsi_ker", "csi_ker" };
0110 
0111 static const char * const i2c_src2[] = {
0112     "pclk4", "pll3_r", "hsi_ker", "csi_ker" };
0113 
0114 static const char * const rng_src[] = {
0115     "rc48_ck", "pll1_q", "lse_ck", "lsi_ck" };
0116 
0117 /* usart 1,6 src */
0118 static const char * const usart_src1[] = {
0119     "pclk2", "pll2_q", "pll3_q", "hsi_ker", "csi_ker", "lse_ck" };
0120 
0121 /* usart 2,3,4,5,7,8 src */
0122 static const char * const usart_src2[] = {
0123     "pclk1", "pll2_q", "pll3_q", "hsi_ker", "csi_ker", "lse_ck" };
0124 
0125 static const char *sai_src[5] = {
0126     "pll1_q", "pll2_p", "pll3_p", NULL, "per_ck" };
0127 
0128 static const char * const adc_src[] = { "pll2_p", "pll3_r", "per_ck" };
0129 
0130 /* lptim 2,3,4,5 src */
0131 static const char * const lpuart1_src[] = {
0132     "pclk3", "pll2_q", "pll3_q", "csi_ker", "lse_ck" };
0133 
0134 static const char * const hrtim_src[] = { "tim2_ker", "d1cpre" };
0135 
0136 /* RTC clock parent */
0137 static const char * const rtc_src[] = { "off", "lse_ck", "lsi_ck", "hse_1M" };
0138 
0139 /* Micro-controller output clock parent */
0140 static const char * const mco_src1[] = {
0141     "hsi_ck", "lse_ck", "hse_ck", "pll1_q", "rc48_ck" };
0142 
0143 static const char * const mco_src2[] = {
0144     "sys_ck", "pll2_p", "hse_ck", "pll1_p", "csi_ck", "lsi_ck" };
0145 
0146 /* LCD clock */
0147 static const char * const ltdc_src[] = {"pll3_r"};
0148 
0149 /* Gate clock with ready bit and backup domain management */
0150 struct stm32_ready_gate {
0151     struct  clk_gate gate;
0152     u8  bit_rdy;
0153 };
0154 
0155 #define to_ready_gate_clk(_rgate) container_of(_rgate, struct stm32_ready_gate,\
0156         gate)
0157 
0158 #define RGATE_TIMEOUT 10000
0159 
0160 static int ready_gate_clk_enable(struct clk_hw *hw)
0161 {
0162     struct clk_gate *gate = to_clk_gate(hw);
0163     struct stm32_ready_gate *rgate = to_ready_gate_clk(gate);
0164     int bit_status;
0165     unsigned int timeout = RGATE_TIMEOUT;
0166 
0167     if (clk_gate_ops.is_enabled(hw))
0168         return 0;
0169 
0170     clk_gate_ops.enable(hw);
0171 
0172     /* We can't use readl_poll_timeout() because we can blocked if
0173      * someone enables this clock before clocksource changes.
0174      * Only jiffies counter is available. Jiffies are incremented by
0175      * interruptions and enable op does not allow to be interrupted.
0176      */
0177     do {
0178         bit_status = !(readl(gate->reg) & BIT(rgate->bit_rdy));
0179 
0180         if (bit_status)
0181             udelay(100);
0182 
0183     } while (bit_status && --timeout);
0184 
0185     return bit_status;
0186 }
0187 
0188 static void ready_gate_clk_disable(struct clk_hw *hw)
0189 {
0190     struct clk_gate *gate = to_clk_gate(hw);
0191     struct stm32_ready_gate *rgate = to_ready_gate_clk(gate);
0192     int bit_status;
0193     unsigned int timeout = RGATE_TIMEOUT;
0194 
0195     if (!clk_gate_ops.is_enabled(hw))
0196         return;
0197 
0198     clk_gate_ops.disable(hw);
0199 
0200     do {
0201         bit_status = !!(readl(gate->reg) & BIT(rgate->bit_rdy));
0202 
0203         if (bit_status)
0204             udelay(100);
0205 
0206     } while (bit_status && --timeout);
0207 }
0208 
0209 static const struct clk_ops ready_gate_clk_ops = {
0210     .enable     = ready_gate_clk_enable,
0211     .disable    = ready_gate_clk_disable,
0212     .is_enabled = clk_gate_is_enabled,
0213 };
0214 
0215 static struct clk_hw *clk_register_ready_gate(struct device *dev,
0216         const char *name, const char *parent_name,
0217         void __iomem *reg, u8 bit_idx, u8 bit_rdy,
0218         unsigned long flags, spinlock_t *lock)
0219 {
0220     struct stm32_ready_gate *rgate;
0221     struct clk_init_data init = { NULL };
0222     struct clk_hw *hw;
0223     int ret;
0224 
0225     rgate = kzalloc(sizeof(*rgate), GFP_KERNEL);
0226     if (!rgate)
0227         return ERR_PTR(-ENOMEM);
0228 
0229     init.name = name;
0230     init.ops = &ready_gate_clk_ops;
0231     init.flags = flags;
0232     init.parent_names = &parent_name;
0233     init.num_parents = 1;
0234 
0235     rgate->bit_rdy = bit_rdy;
0236     rgate->gate.lock = lock;
0237     rgate->gate.reg = reg;
0238     rgate->gate.bit_idx = bit_idx;
0239     rgate->gate.hw.init = &init;
0240 
0241     hw = &rgate->gate.hw;
0242     ret = clk_hw_register(dev, hw);
0243     if (ret) {
0244         kfree(rgate);
0245         hw = ERR_PTR(ret);
0246     }
0247 
0248     return hw;
0249 }
0250 
0251 struct gate_cfg {
0252     u32 offset;
0253     u8  bit_idx;
0254 };
0255 
0256 struct muxdiv_cfg {
0257     u32 offset;
0258     u8 shift;
0259     u8 width;
0260 };
0261 
0262 struct composite_clk_cfg {
0263     struct gate_cfg *gate;
0264     struct muxdiv_cfg *mux;
0265     struct muxdiv_cfg *div;
0266     const char *name;
0267     const char * const *parent_name;
0268     int num_parents;
0269     u32 flags;
0270 };
0271 
0272 struct composite_clk_gcfg_t {
0273     u8 flags;
0274     const struct clk_ops *ops;
0275 };
0276 
0277 /*
0278  * General config definition of a composite clock (only clock diviser for rate)
0279  */
0280 struct composite_clk_gcfg {
0281     struct composite_clk_gcfg_t *mux;
0282     struct composite_clk_gcfg_t *div;
0283     struct composite_clk_gcfg_t *gate;
0284 };
0285 
0286 #define M_CFG_MUX(_mux_ops, _mux_flags)\
0287     .mux = &(struct composite_clk_gcfg_t) { _mux_flags, _mux_ops}
0288 
0289 #define M_CFG_DIV(_rate_ops, _rate_flags)\
0290     .div = &(struct composite_clk_gcfg_t) {_rate_flags, _rate_ops}
0291 
0292 #define M_CFG_GATE(_gate_ops, _gate_flags)\
0293     .gate = &(struct composite_clk_gcfg_t) { _gate_flags, _gate_ops}
0294 
0295 static struct clk_mux *_get_cmux(void __iomem *reg, u8 shift, u8 width,
0296         u32 flags, spinlock_t *lock)
0297 {
0298     struct clk_mux *mux;
0299 
0300     mux = kzalloc(sizeof(*mux), GFP_KERNEL);
0301     if (!mux)
0302         return ERR_PTR(-ENOMEM);
0303 
0304     mux->reg    = reg;
0305     mux->shift  = shift;
0306     mux->mask   = (1 << width) - 1;
0307     mux->flags  = flags;
0308     mux->lock   = lock;
0309 
0310     return mux;
0311 }
0312 
0313 static struct clk_divider *_get_cdiv(void __iomem *reg, u8 shift, u8 width,
0314         u32 flags, spinlock_t *lock)
0315 {
0316     struct clk_divider *div;
0317 
0318     div = kzalloc(sizeof(*div), GFP_KERNEL);
0319 
0320     if (!div)
0321         return ERR_PTR(-ENOMEM);
0322 
0323     div->reg   = reg;
0324     div->shift = shift;
0325     div->width = width;
0326     div->flags = flags;
0327     div->lock  = lock;
0328 
0329     return div;
0330 }
0331 
0332 static struct clk_gate *_get_cgate(void __iomem *reg, u8 bit_idx, u32 flags,
0333         spinlock_t *lock)
0334 {
0335     struct clk_gate *gate;
0336 
0337     gate = kzalloc(sizeof(*gate), GFP_KERNEL);
0338     if (!gate)
0339         return ERR_PTR(-ENOMEM);
0340 
0341     gate->reg   = reg;
0342     gate->bit_idx   = bit_idx;
0343     gate->flags = flags;
0344     gate->lock  = lock;
0345 
0346     return gate;
0347 }
0348 
0349 struct composite_cfg {
0350     struct clk_hw *mux_hw;
0351     struct clk_hw *div_hw;
0352     struct clk_hw *gate_hw;
0353 
0354     const struct clk_ops *mux_ops;
0355     const struct clk_ops *div_ops;
0356     const struct clk_ops *gate_ops;
0357 };
0358 
0359 static void get_cfg_composite_div(const struct composite_clk_gcfg *gcfg,
0360         const struct composite_clk_cfg *cfg,
0361         struct composite_cfg *composite, spinlock_t *lock)
0362 {
0363     struct clk_mux     *mux = NULL;
0364     struct clk_divider *div = NULL;
0365     struct clk_gate    *gate = NULL;
0366     const struct clk_ops *mux_ops, *div_ops, *gate_ops;
0367     struct clk_hw *mux_hw;
0368     struct clk_hw *div_hw;
0369     struct clk_hw *gate_hw;
0370 
0371     mux_ops = div_ops = gate_ops = NULL;
0372     mux_hw = div_hw = gate_hw = NULL;
0373 
0374     if (gcfg->mux && cfg->mux) {
0375         mux = _get_cmux(base + cfg->mux->offset,
0376                 cfg->mux->shift,
0377                 cfg->mux->width,
0378                 gcfg->mux->flags, lock);
0379 
0380         if (!IS_ERR(mux)) {
0381             mux_hw = &mux->hw;
0382             mux_ops = gcfg->mux->ops ?
0383                   gcfg->mux->ops : &clk_mux_ops;
0384         }
0385     }
0386 
0387     if (gcfg->div && cfg->div) {
0388         div = _get_cdiv(base + cfg->div->offset,
0389                 cfg->div->shift,
0390                 cfg->div->width,
0391                 gcfg->div->flags, lock);
0392 
0393         if (!IS_ERR(div)) {
0394             div_hw = &div->hw;
0395             div_ops = gcfg->div->ops ?
0396                   gcfg->div->ops : &clk_divider_ops;
0397         }
0398     }
0399 
0400     if (gcfg->gate && cfg->gate) {
0401         gate = _get_cgate(base + cfg->gate->offset,
0402                 cfg->gate->bit_idx,
0403                 gcfg->gate->flags, lock);
0404 
0405         if (!IS_ERR(gate)) {
0406             gate_hw = &gate->hw;
0407             gate_ops = gcfg->gate->ops ?
0408                    gcfg->gate->ops : &clk_gate_ops;
0409         }
0410     }
0411 
0412     composite->mux_hw = mux_hw;
0413     composite->mux_ops = mux_ops;
0414 
0415     composite->div_hw = div_hw;
0416     composite->div_ops = div_ops;
0417 
0418     composite->gate_hw = gate_hw;
0419     composite->gate_ops = gate_ops;
0420 }
0421 
0422 /* Kernel Timer */
0423 struct timer_ker {
0424     u8 dppre_shift;
0425     struct clk_hw hw;
0426     spinlock_t *lock;
0427 };
0428 
0429 #define to_timer_ker(_hw) container_of(_hw, struct timer_ker, hw)
0430 
0431 static unsigned long timer_ker_recalc_rate(struct clk_hw *hw,
0432         unsigned long parent_rate)
0433 {
0434     struct timer_ker *clk_elem = to_timer_ker(hw);
0435     u32 timpre;
0436     u32 dppre_shift = clk_elem->dppre_shift;
0437     u32 prescaler;
0438     u32 mul;
0439 
0440     timpre = (readl(base + RCC_CFGR) >> 15) & 0x01;
0441 
0442     prescaler = (readl(base + RCC_D2CFGR) >> dppre_shift) & 0x03;
0443 
0444     mul = 2;
0445 
0446     if (prescaler < 4)
0447         mul = 1;
0448 
0449     else if (timpre && prescaler > 4)
0450         mul = 4;
0451 
0452     return parent_rate * mul;
0453 }
0454 
0455 static const struct clk_ops timer_ker_ops = {
0456     .recalc_rate = timer_ker_recalc_rate,
0457 };
0458 
0459 static struct clk_hw *clk_register_stm32_timer_ker(struct device *dev,
0460         const char *name, const char *parent_name,
0461         unsigned long flags,
0462         u8 dppre_shift,
0463         spinlock_t *lock)
0464 {
0465     struct timer_ker *element;
0466     struct clk_init_data init;
0467     struct clk_hw *hw;
0468     int err;
0469 
0470     element = kzalloc(sizeof(*element), GFP_KERNEL);
0471     if (!element)
0472         return ERR_PTR(-ENOMEM);
0473 
0474     init.name = name;
0475     init.ops = &timer_ker_ops;
0476     init.flags = flags;
0477     init.parent_names = &parent_name;
0478     init.num_parents = 1;
0479 
0480     element->hw.init = &init;
0481     element->lock = lock;
0482     element->dppre_shift = dppre_shift;
0483 
0484     hw = &element->hw;
0485     err = clk_hw_register(dev, hw);
0486 
0487     if (err) {
0488         kfree(element);
0489         return ERR_PTR(err);
0490     }
0491 
0492     return hw;
0493 }
0494 
0495 static const struct clk_div_table d1cpre_div_table[] = {
0496     { 0, 1 }, { 1, 1 }, { 2, 1 }, { 3, 1},
0497     { 4, 1 }, { 5, 1 }, { 6, 1 }, { 7, 1},
0498     { 8, 2 }, { 9, 4 }, { 10, 8 }, { 11, 16 },
0499     { 12, 64 }, { 13, 128 }, { 14, 256 },
0500     { 15, 512 },
0501     { 0 },
0502 };
0503 
0504 static const struct clk_div_table ppre_div_table[] = {
0505     { 0, 1 }, { 1, 1 }, { 2, 1 }, { 3, 1},
0506     { 4, 2 }, { 5, 4 }, { 6, 8 }, { 7, 16 },
0507     { 0 },
0508 };
0509 
0510 static void register_core_and_bus_clocks(void)
0511 {
0512     /* CORE AND BUS */
0513     hws[SYS_D1CPRE] = clk_hw_register_divider_table(NULL, "d1cpre",
0514             "sys_ck", CLK_IGNORE_UNUSED, base + RCC_D1CFGR, 8, 4, 0,
0515             d1cpre_div_table, &stm32rcc_lock);
0516 
0517     hws[HCLK] = clk_hw_register_divider_table(NULL, "hclk", "d1cpre",
0518             CLK_IGNORE_UNUSED, base + RCC_D1CFGR, 0, 4, 0,
0519             d1cpre_div_table, &stm32rcc_lock);
0520 
0521     /* D1 DOMAIN */
0522     /* * CPU Systick */
0523     hws[CPU_SYSTICK] = clk_hw_register_fixed_factor(NULL, "systick",
0524             "d1cpre", 0, 1, 8);
0525 
0526     /* * APB3 peripheral */
0527     hws[PCLK3] = clk_hw_register_divider_table(NULL, "pclk3", "hclk", 0,
0528             base + RCC_D1CFGR, 4, 3, 0,
0529             ppre_div_table, &stm32rcc_lock);
0530 
0531     /* D2 DOMAIN */
0532     /* * APB1 peripheral */
0533     hws[PCLK1] = clk_hw_register_divider_table(NULL, "pclk1", "hclk", 0,
0534             base + RCC_D2CFGR, 4, 3, 0,
0535             ppre_div_table, &stm32rcc_lock);
0536 
0537     /* Timers prescaler clocks */
0538     clk_register_stm32_timer_ker(NULL, "tim1_ker", "pclk1", 0,
0539             4, &stm32rcc_lock);
0540 
0541     /* * APB2 peripheral */
0542     hws[PCLK2] = clk_hw_register_divider_table(NULL, "pclk2", "hclk", 0,
0543             base + RCC_D2CFGR, 8, 3, 0, ppre_div_table,
0544             &stm32rcc_lock);
0545 
0546     clk_register_stm32_timer_ker(NULL, "tim2_ker", "pclk2", 0, 8,
0547             &stm32rcc_lock);
0548 
0549     /* D3 DOMAIN */
0550     /* * APB4 peripheral */
0551     hws[PCLK4] = clk_hw_register_divider_table(NULL, "pclk4", "hclk", 0,
0552             base + RCC_D3CFGR, 4, 3, 0,
0553             ppre_div_table, &stm32rcc_lock);
0554 }
0555 
0556 /* MUX clock configuration */
0557 struct stm32_mux_clk {
0558     const char *name;
0559     const char * const *parents;
0560     u8 num_parents;
0561     u32 offset;
0562     u8 shift;
0563     u8 width;
0564     u32 flags;
0565 };
0566 
0567 #define M_MCLOCF(_name, _parents, _mux_offset, _mux_shift, _mux_width, _flags)\
0568 {\
0569     .name       = _name,\
0570     .parents    = _parents,\
0571     .num_parents    = ARRAY_SIZE(_parents),\
0572     .offset     = _mux_offset,\
0573     .shift      = _mux_shift,\
0574     .width      = _mux_width,\
0575     .flags      = _flags,\
0576 }
0577 
0578 #define M_MCLOC(_name, _parents, _mux_offset, _mux_shift, _mux_width)\
0579     M_MCLOCF(_name, _parents, _mux_offset, _mux_shift, _mux_width, 0)\
0580 
0581 static const struct stm32_mux_clk stm32_mclk[] __initconst = {
0582     M_MCLOC("per_ck",   per_src,    RCC_D1CCIPR,    28, 3),
0583     M_MCLOC("pllsrc",   pll_src,    RCC_PLLCKSELR,   0, 3),
0584     M_MCLOC("sys_ck",   sys_src,    RCC_CFGR,    0, 3),
0585     M_MCLOC("tracein_ck",   tracein_src,    RCC_CFGR,    0, 3),
0586 };
0587 
0588 /* Oscillary clock configuration */
0589 struct stm32_osc_clk {
0590     const char *name;
0591     const char *parent;
0592     u32 gate_offset;
0593     u8 bit_idx;
0594     u8 bit_rdy;
0595     u32 flags;
0596 };
0597 
0598 #define OSC_CLKF(_name, _parent, _gate_offset, _bit_idx, _bit_rdy, _flags)\
0599 {\
0600     .name       = _name,\
0601     .parent     = _parent,\
0602     .gate_offset    = _gate_offset,\
0603     .bit_idx    = _bit_idx,\
0604     .bit_rdy    = _bit_rdy,\
0605     .flags      = _flags,\
0606 }
0607 
0608 #define OSC_CLK(_name, _parent, _gate_offset, _bit_idx, _bit_rdy)\
0609     OSC_CLKF(_name, _parent, _gate_offset, _bit_idx, _bit_rdy, 0)
0610 
0611 static const struct stm32_osc_clk stm32_oclk[] __initconst = {
0612     OSC_CLKF("hsi_ck",  "hsidiv",   RCC_CR,   0,  2, CLK_IGNORE_UNUSED),
0613     OSC_CLKF("hsi_ker", "hsidiv",   RCC_CR,   1,  2, CLK_IGNORE_UNUSED),
0614     OSC_CLKF("csi_ck",  "clk-csi",  RCC_CR,   7,  8, CLK_IGNORE_UNUSED),
0615     OSC_CLKF("csi_ker", "clk-csi",  RCC_CR,   9,  8, CLK_IGNORE_UNUSED),
0616     OSC_CLKF("rc48_ck", "clk-rc48", RCC_CR,  12, 13, CLK_IGNORE_UNUSED),
0617     OSC_CLKF("lsi_ck",  "clk-lsi",  RCC_CSR,  0,  1, CLK_IGNORE_UNUSED),
0618 };
0619 
0620 /* PLL configuration */
0621 struct st32h7_pll_cfg {
0622     u8 bit_idx;
0623     u32 offset_divr;
0624     u8 bit_frac_en;
0625     u32 offset_frac;
0626     u8 divm;
0627 };
0628 
0629 struct stm32_pll_data {
0630     const char *name;
0631     const char *parent_name;
0632     unsigned long flags;
0633     const struct st32h7_pll_cfg *cfg;
0634 };
0635 
0636 static const struct st32h7_pll_cfg stm32h7_pll1 = {
0637     .bit_idx = 24,
0638     .offset_divr = RCC_PLL1DIVR,
0639     .bit_frac_en = 0,
0640     .offset_frac = RCC_PLL1FRACR,
0641     .divm = 4,
0642 };
0643 
0644 static const struct st32h7_pll_cfg stm32h7_pll2 = {
0645     .bit_idx = 26,
0646     .offset_divr = RCC_PLL2DIVR,
0647     .bit_frac_en = 4,
0648     .offset_frac = RCC_PLL2FRACR,
0649     .divm = 12,
0650 };
0651 
0652 static const struct st32h7_pll_cfg stm32h7_pll3 = {
0653     .bit_idx = 28,
0654     .offset_divr = RCC_PLL3DIVR,
0655     .bit_frac_en = 8,
0656     .offset_frac = RCC_PLL3FRACR,
0657     .divm = 20,
0658 };
0659 
0660 static const struct stm32_pll_data stm32_pll[] = {
0661     { "vco1", "pllsrc", CLK_IGNORE_UNUSED, &stm32h7_pll1 },
0662     { "vco2", "pllsrc", 0, &stm32h7_pll2 },
0663     { "vco3", "pllsrc", 0, &stm32h7_pll3 },
0664 };
0665 
0666 struct stm32_fractional_divider {
0667     void __iomem    *mreg;
0668     u8      mshift;
0669     u8      mwidth;
0670     u32     mmask;
0671 
0672     void __iomem    *nreg;
0673     u8      nshift;
0674     u8      nwidth;
0675 
0676     void __iomem    *freg_status;
0677     u8      freg_bit;
0678     void __iomem    *freg_value;
0679     u8      fshift;
0680     u8      fwidth;
0681 
0682     u8      flags;
0683     struct clk_hw   hw;
0684     spinlock_t  *lock;
0685 };
0686 
0687 struct stm32_pll_obj {
0688     spinlock_t *lock;
0689     struct stm32_fractional_divider div;
0690     struct stm32_ready_gate rgate;
0691     struct clk_hw hw;
0692 };
0693 
0694 #define to_pll(_hw) container_of(_hw, struct stm32_pll_obj, hw)
0695 
0696 static int pll_is_enabled(struct clk_hw *hw)
0697 {
0698     struct stm32_pll_obj *clk_elem = to_pll(hw);
0699     struct clk_hw *_hw = &clk_elem->rgate.gate.hw;
0700 
0701     __clk_hw_set_clk(_hw, hw);
0702 
0703     return ready_gate_clk_ops.is_enabled(_hw);
0704 }
0705 
0706 static int pll_enable(struct clk_hw *hw)
0707 {
0708     struct stm32_pll_obj *clk_elem = to_pll(hw);
0709     struct clk_hw *_hw = &clk_elem->rgate.gate.hw;
0710 
0711     __clk_hw_set_clk(_hw, hw);
0712 
0713     return ready_gate_clk_ops.enable(_hw);
0714 }
0715 
0716 static void pll_disable(struct clk_hw *hw)
0717 {
0718     struct stm32_pll_obj *clk_elem = to_pll(hw);
0719     struct clk_hw *_hw = &clk_elem->rgate.gate.hw;
0720 
0721     __clk_hw_set_clk(_hw, hw);
0722 
0723     ready_gate_clk_ops.disable(_hw);
0724 }
0725 
0726 static int pll_frac_is_enabled(struct clk_hw *hw)
0727 {
0728     struct stm32_pll_obj *clk_elem = to_pll(hw);
0729     struct stm32_fractional_divider *fd = &clk_elem->div;
0730 
0731     return (readl(fd->freg_status) >> fd->freg_bit) & 0x01;
0732 }
0733 
0734 static unsigned long pll_read_frac(struct clk_hw *hw)
0735 {
0736     struct stm32_pll_obj *clk_elem = to_pll(hw);
0737     struct stm32_fractional_divider *fd = &clk_elem->div;
0738 
0739     return (readl(fd->freg_value) >> fd->fshift) &
0740         GENMASK(fd->fwidth - 1, 0);
0741 }
0742 
0743 static unsigned long pll_fd_recalc_rate(struct clk_hw *hw,
0744         unsigned long parent_rate)
0745 {
0746     struct stm32_pll_obj *clk_elem = to_pll(hw);
0747     struct stm32_fractional_divider *fd = &clk_elem->div;
0748     unsigned long m, n;
0749     u32 val, mask;
0750     u64 rate, rate1 = 0;
0751 
0752     val = readl(fd->mreg);
0753     mask = GENMASK(fd->mwidth - 1, 0) << fd->mshift;
0754     m = (val & mask) >> fd->mshift;
0755 
0756     val = readl(fd->nreg);
0757     mask = GENMASK(fd->nwidth - 1, 0) << fd->nshift;
0758     n = ((val & mask) >> fd->nshift) + 1;
0759 
0760     if (!n || !m)
0761         return parent_rate;
0762 
0763     rate = (u64)parent_rate * n;
0764     do_div(rate, m);
0765 
0766     if (pll_frac_is_enabled(hw)) {
0767         val = pll_read_frac(hw);
0768         rate1 = (u64)parent_rate * (u64)val;
0769         do_div(rate1, (m * 8191));
0770     }
0771 
0772     return rate + rate1;
0773 }
0774 
0775 static const struct clk_ops pll_ops = {
0776     .enable     = pll_enable,
0777     .disable    = pll_disable,
0778     .is_enabled = pll_is_enabled,
0779     .recalc_rate    = pll_fd_recalc_rate,
0780 };
0781 
0782 static struct clk_hw *clk_register_stm32_pll(struct device *dev,
0783         const char *name,
0784         const char *parent,
0785         unsigned long flags,
0786         const struct st32h7_pll_cfg *cfg,
0787         spinlock_t *lock)
0788 {
0789     struct stm32_pll_obj *pll;
0790     struct clk_init_data init = { NULL };
0791     struct clk_hw *hw;
0792     int ret;
0793     struct stm32_fractional_divider *div = NULL;
0794     struct stm32_ready_gate *rgate;
0795 
0796     pll = kzalloc(sizeof(*pll), GFP_KERNEL);
0797     if (!pll)
0798         return ERR_PTR(-ENOMEM);
0799 
0800     init.name = name;
0801     init.ops = &pll_ops;
0802     init.flags = flags;
0803     init.parent_names = &parent;
0804     init.num_parents = 1;
0805     pll->hw.init = &init;
0806 
0807     hw = &pll->hw;
0808     rgate = &pll->rgate;
0809 
0810     rgate->bit_rdy = cfg->bit_idx + 1;
0811     rgate->gate.lock = lock;
0812     rgate->gate.reg = base + RCC_CR;
0813     rgate->gate.bit_idx = cfg->bit_idx;
0814 
0815     div = &pll->div;
0816     div->flags = 0;
0817     div->mreg = base + RCC_PLLCKSELR;
0818     div->mshift = cfg->divm;
0819     div->mwidth = 6;
0820     div->nreg = base +  cfg->offset_divr;
0821     div->nshift = 0;
0822     div->nwidth = 9;
0823 
0824     div->freg_status = base + RCC_PLLCFGR;
0825     div->freg_bit = cfg->bit_frac_en;
0826     div->freg_value = base +  cfg->offset_frac;
0827     div->fshift = 3;
0828     div->fwidth = 13;
0829 
0830     div->lock = lock;
0831 
0832     ret = clk_hw_register(dev, hw);
0833     if (ret) {
0834         kfree(pll);
0835         hw = ERR_PTR(ret);
0836     }
0837 
0838     return hw;
0839 }
0840 
0841 /* ODF CLOCKS */
0842 static unsigned long odf_divider_recalc_rate(struct clk_hw *hw,
0843         unsigned long parent_rate)
0844 {
0845     return clk_divider_ops.recalc_rate(hw, parent_rate);
0846 }
0847 
0848 static int odf_divider_determine_rate(struct clk_hw *hw,
0849                       struct clk_rate_request *req)
0850 {
0851     return clk_divider_ops.determine_rate(hw, req);
0852 }
0853 
0854 static int odf_divider_set_rate(struct clk_hw *hw, unsigned long rate,
0855         unsigned long parent_rate)
0856 {
0857     struct clk_hw *hwp;
0858     int pll_status;
0859     int ret;
0860 
0861     hwp = clk_hw_get_parent(hw);
0862 
0863     pll_status = pll_is_enabled(hwp);
0864 
0865     if (pll_status)
0866         pll_disable(hwp);
0867 
0868     ret = clk_divider_ops.set_rate(hw, rate, parent_rate);
0869 
0870     if (pll_status)
0871         pll_enable(hwp);
0872 
0873     return ret;
0874 }
0875 
0876 static const struct clk_ops odf_divider_ops = {
0877     .recalc_rate    = odf_divider_recalc_rate,
0878     .determine_rate = odf_divider_determine_rate,
0879     .set_rate   = odf_divider_set_rate,
0880 };
0881 
0882 static int odf_gate_enable(struct clk_hw *hw)
0883 {
0884     struct clk_hw *hwp;
0885     int pll_status;
0886     int ret;
0887 
0888     if (clk_gate_ops.is_enabled(hw))
0889         return 0;
0890 
0891     hwp = clk_hw_get_parent(hw);
0892 
0893     pll_status = pll_is_enabled(hwp);
0894 
0895     if (pll_status)
0896         pll_disable(hwp);
0897 
0898     ret = clk_gate_ops.enable(hw);
0899 
0900     if (pll_status)
0901         pll_enable(hwp);
0902 
0903     return ret;
0904 }
0905 
0906 static void odf_gate_disable(struct clk_hw *hw)
0907 {
0908     struct clk_hw *hwp;
0909     int pll_status;
0910 
0911     if (!clk_gate_ops.is_enabled(hw))
0912         return;
0913 
0914     hwp = clk_hw_get_parent(hw);
0915 
0916     pll_status = pll_is_enabled(hwp);
0917 
0918     if (pll_status)
0919         pll_disable(hwp);
0920 
0921     clk_gate_ops.disable(hw);
0922 
0923     if (pll_status)
0924         pll_enable(hwp);
0925 }
0926 
0927 static const struct clk_ops odf_gate_ops = {
0928     .enable     = odf_gate_enable,
0929     .disable    = odf_gate_disable,
0930     .is_enabled = clk_gate_is_enabled,
0931 };
0932 
0933 static struct composite_clk_gcfg odf_clk_gcfg = {
0934     M_CFG_DIV(&odf_divider_ops, 0),
0935     M_CFG_GATE(&odf_gate_ops, 0),
0936 };
0937 
0938 #define M_ODF_F(_name, _parent, _gate_offset,  _bit_idx, _rate_offset,\
0939         _rate_shift, _rate_width, _flags)\
0940 {\
0941     .mux = NULL,\
0942     .div = &(struct muxdiv_cfg) {_rate_offset, _rate_shift, _rate_width},\
0943     .gate = &(struct gate_cfg) {_gate_offset, _bit_idx },\
0944     .name = _name,\
0945     .parent_name = &(const char *) {_parent},\
0946     .num_parents = 1,\
0947     .flags = _flags,\
0948 }
0949 
0950 #define M_ODF(_name, _parent, _gate_offset,  _bit_idx, _rate_offset,\
0951         _rate_shift, _rate_width)\
0952 M_ODF_F(_name, _parent, _gate_offset,  _bit_idx, _rate_offset,\
0953         _rate_shift, _rate_width, 0)\
0954 
0955 static const struct composite_clk_cfg stm32_odf[3][3] = {
0956     {
0957         M_ODF_F("pll1_p", "vco1", RCC_PLLCFGR, 16, RCC_PLL1DIVR,  9, 7,
0958                 CLK_IGNORE_UNUSED),
0959         M_ODF_F("pll1_q", "vco1", RCC_PLLCFGR, 17, RCC_PLL1DIVR, 16, 7,
0960                 CLK_IGNORE_UNUSED),
0961         M_ODF_F("pll1_r", "vco1", RCC_PLLCFGR, 18, RCC_PLL1DIVR, 24, 7,
0962                 CLK_IGNORE_UNUSED),
0963     },
0964 
0965     {
0966         M_ODF("pll2_p", "vco2", RCC_PLLCFGR, 19, RCC_PLL2DIVR,  9, 7),
0967         M_ODF("pll2_q", "vco2", RCC_PLLCFGR, 20, RCC_PLL2DIVR, 16, 7),
0968         M_ODF("pll2_r", "vco2", RCC_PLLCFGR, 21, RCC_PLL2DIVR, 24, 7),
0969     },
0970     {
0971         M_ODF("pll3_p", "vco3", RCC_PLLCFGR, 22, RCC_PLL3DIVR,  9, 7),
0972         M_ODF("pll3_q", "vco3", RCC_PLLCFGR, 23, RCC_PLL3DIVR, 16, 7),
0973         M_ODF("pll3_r", "vco3", RCC_PLLCFGR, 24, RCC_PLL3DIVR, 24, 7),
0974     }
0975 };
0976 
0977 /* PERIF CLOCKS */
0978 struct pclk_t {
0979     u32 gate_offset;
0980     u8 bit_idx;
0981     const char *name;
0982     const char *parent;
0983     u32 flags;
0984 };
0985 
0986 #define PER_CLKF(_gate_offset, _bit_idx, _name, _parent, _flags)\
0987 {\
0988     .gate_offset    = _gate_offset,\
0989     .bit_idx    = _bit_idx,\
0990     .name       = _name,\
0991     .parent     = _parent,\
0992     .flags      = _flags,\
0993 }
0994 
0995 #define PER_CLK(_gate_offset, _bit_idx, _name, _parent)\
0996     PER_CLKF(_gate_offset, _bit_idx, _name, _parent, 0)
0997 
0998 static const struct pclk_t pclk[] = {
0999     PER_CLK(RCC_AHB3ENR, 31, "d1sram1", "hclk"),
1000     PER_CLK(RCC_AHB3ENR, 30, "itcm", "hclk"),
1001     PER_CLK(RCC_AHB3ENR, 29, "dtcm2", "hclk"),
1002     PER_CLK(RCC_AHB3ENR, 28, "dtcm1", "hclk"),
1003     PER_CLK(RCC_AHB3ENR, 8, "flitf", "hclk"),
1004     PER_CLK(RCC_AHB3ENR, 5, "jpgdec", "hclk"),
1005     PER_CLK(RCC_AHB3ENR, 4, "dma2d", "hclk"),
1006     PER_CLK(RCC_AHB3ENR, 0, "mdma", "hclk"),
1007     PER_CLK(RCC_AHB1ENR, 28, "usb2ulpi", "hclk"),
1008     PER_CLK(RCC_AHB1ENR, 26, "usb1ulpi", "hclk"),
1009     PER_CLK(RCC_AHB1ENR, 17, "eth1rx", "hclk"),
1010     PER_CLK(RCC_AHB1ENR, 16, "eth1tx", "hclk"),
1011     PER_CLK(RCC_AHB1ENR, 15, "eth1mac", "hclk"),
1012     PER_CLK(RCC_AHB1ENR, 14, "art", "hclk"),
1013     PER_CLK(RCC_AHB1ENR, 1, "dma2", "hclk"),
1014     PER_CLK(RCC_AHB1ENR, 0, "dma1", "hclk"),
1015     PER_CLK(RCC_AHB2ENR, 31, "d2sram3", "hclk"),
1016     PER_CLK(RCC_AHB2ENR, 30, "d2sram2", "hclk"),
1017     PER_CLK(RCC_AHB2ENR, 29, "d2sram1", "hclk"),
1018     PER_CLK(RCC_AHB2ENR, 5, "hash", "hclk"),
1019     PER_CLK(RCC_AHB2ENR, 4, "crypt", "hclk"),
1020     PER_CLK(RCC_AHB2ENR, 0, "camitf", "hclk"),
1021     PER_CLK(RCC_AHB4ENR, 28, "bkpram", "hclk"),
1022     PER_CLK(RCC_AHB4ENR, 25, "hsem", "hclk"),
1023     PER_CLK(RCC_AHB4ENR, 21, "bdma", "hclk"),
1024     PER_CLK(RCC_AHB4ENR, 19, "crc", "hclk"),
1025     PER_CLK(RCC_AHB4ENR, 10, "gpiok", "hclk"),
1026     PER_CLK(RCC_AHB4ENR, 9, "gpioj", "hclk"),
1027     PER_CLK(RCC_AHB4ENR, 8, "gpioi", "hclk"),
1028     PER_CLK(RCC_AHB4ENR, 7, "gpioh", "hclk"),
1029     PER_CLK(RCC_AHB4ENR, 6, "gpiog", "hclk"),
1030     PER_CLK(RCC_AHB4ENR, 5, "gpiof", "hclk"),
1031     PER_CLK(RCC_AHB4ENR, 4, "gpioe", "hclk"),
1032     PER_CLK(RCC_AHB4ENR, 3, "gpiod", "hclk"),
1033     PER_CLK(RCC_AHB4ENR, 2, "gpioc", "hclk"),
1034     PER_CLK(RCC_AHB4ENR, 1, "gpiob", "hclk"),
1035     PER_CLK(RCC_AHB4ENR, 0, "gpioa", "hclk"),
1036     PER_CLK(RCC_APB3ENR, 6, "wwdg1", "pclk3"),
1037     PER_CLK(RCC_APB1LENR, 29, "dac12", "pclk1"),
1038     PER_CLK(RCC_APB1LENR, 11, "wwdg2", "pclk1"),
1039     PER_CLK(RCC_APB1LENR, 8, "tim14", "tim1_ker"),
1040     PER_CLK(RCC_APB1LENR, 7, "tim13", "tim1_ker"),
1041     PER_CLK(RCC_APB1LENR, 6, "tim12", "tim1_ker"),
1042     PER_CLK(RCC_APB1LENR, 5, "tim7", "tim1_ker"),
1043     PER_CLK(RCC_APB1LENR, 4, "tim6", "tim1_ker"),
1044     PER_CLK(RCC_APB1LENR, 3, "tim5", "tim1_ker"),
1045     PER_CLK(RCC_APB1LENR, 2, "tim4", "tim1_ker"),
1046     PER_CLK(RCC_APB1LENR, 1, "tim3", "tim1_ker"),
1047     PER_CLK(RCC_APB1LENR, 0, "tim2", "tim1_ker"),
1048     PER_CLK(RCC_APB1HENR, 5, "mdios", "pclk1"),
1049     PER_CLK(RCC_APB1HENR, 4, "opamp", "pclk1"),
1050     PER_CLK(RCC_APB1HENR, 1, "crs", "pclk1"),
1051     PER_CLK(RCC_APB2ENR, 18, "tim17", "tim2_ker"),
1052     PER_CLK(RCC_APB2ENR, 17, "tim16", "tim2_ker"),
1053     PER_CLK(RCC_APB2ENR, 16, "tim15", "tim2_ker"),
1054     PER_CLK(RCC_APB2ENR, 1, "tim8", "tim2_ker"),
1055     PER_CLK(RCC_APB2ENR, 0, "tim1", "tim2_ker"),
1056     PER_CLK(RCC_APB4ENR, 26, "tmpsens", "pclk4"),
1057     PER_CLK(RCC_APB4ENR, 16, "rtcapb", "pclk4"),
1058     PER_CLK(RCC_APB4ENR, 15, "vref", "pclk4"),
1059     PER_CLK(RCC_APB4ENR, 14, "comp12", "pclk4"),
1060     PER_CLK(RCC_APB4ENR, 1, "syscfg", "pclk4"),
1061 };
1062 
1063 /* KERNEL CLOCKS */
1064 #define KER_CLKF(_gate_offset, _bit_idx,\
1065         _mux_offset, _mux_shift, _mux_width,\
1066         _name, _parent_name,\
1067         _flags) \
1068 { \
1069     .gate = &(struct gate_cfg) {_gate_offset, _bit_idx},\
1070     .mux = &(struct muxdiv_cfg) {_mux_offset, _mux_shift, _mux_width },\
1071     .name = _name, \
1072     .parent_name = _parent_name, \
1073     .num_parents = ARRAY_SIZE(_parent_name),\
1074     .flags = _flags,\
1075 }
1076 
1077 #define KER_CLK(_gate_offset, _bit_idx, _mux_offset, _mux_shift, _mux_width,\
1078         _name, _parent_name) \
1079 KER_CLKF(_gate_offset, _bit_idx, _mux_offset, _mux_shift, _mux_width,\
1080         _name, _parent_name, 0)\
1081 
1082 #define KER_CLKF_NOMUX(_gate_offset, _bit_idx,\
1083         _name, _parent_name,\
1084         _flags) \
1085 { \
1086     .gate = &(struct gate_cfg) {_gate_offset, _bit_idx},\
1087     .mux = NULL,\
1088     .name = _name, \
1089     .parent_name = _parent_name, \
1090     .num_parents = 1,\
1091     .flags = _flags,\
1092 }
1093 
1094 static const struct composite_clk_cfg kclk[] = {
1095     KER_CLK(RCC_AHB3ENR,  16, RCC_D1CCIPR,  16, 1, "sdmmc1", sdmmc_src),
1096     KER_CLKF(RCC_AHB3ENR, 14, RCC_D1CCIPR,   4, 2, "quadspi", qspi_src,
1097             CLK_IGNORE_UNUSED),
1098     KER_CLKF(RCC_AHB3ENR, 12, RCC_D1CCIPR,   0, 2, "fmc", fmc_src,
1099             CLK_IGNORE_UNUSED),
1100     KER_CLK(RCC_AHB1ENR,  27, RCC_D2CCIP2R, 20, 2, "usb2otg", usbotg_src),
1101     KER_CLK(RCC_AHB1ENR,  25, RCC_D2CCIP2R, 20, 2, "usb1otg", usbotg_src),
1102     KER_CLK(RCC_AHB1ENR,   5, RCC_D3CCIPR,  16, 2, "adc12", adc_src),
1103     KER_CLK(RCC_AHB2ENR,   9, RCC_D1CCIPR,  16, 1, "sdmmc2", sdmmc_src),
1104     KER_CLK(RCC_AHB2ENR,   6, RCC_D2CCIP2R,  8, 2, "rng", rng_src),
1105     KER_CLK(RCC_AHB4ENR,  24, RCC_D3CCIPR,  16, 2, "adc3", adc_src),
1106     KER_CLKF(RCC_APB3ENR,   4, RCC_D1CCIPR,  8, 1, "dsi", dsi_src,
1107             CLK_SET_RATE_PARENT),
1108     KER_CLKF_NOMUX(RCC_APB3ENR, 3, "ltdc", ltdc_src, CLK_SET_RATE_PARENT),
1109     KER_CLK(RCC_APB1LENR, 31, RCC_D2CCIP2R,  0, 3, "usart8", usart_src2),
1110     KER_CLK(RCC_APB1LENR, 30, RCC_D2CCIP2R,  0, 3, "usart7", usart_src2),
1111     KER_CLK(RCC_APB1LENR, 27, RCC_D2CCIP2R, 22, 2, "hdmicec", cec_src),
1112     KER_CLK(RCC_APB1LENR, 23, RCC_D2CCIP2R, 12, 2, "i2c3", i2c_src1),
1113     KER_CLK(RCC_APB1LENR, 22, RCC_D2CCIP2R, 12, 2, "i2c2", i2c_src1),
1114     KER_CLK(RCC_APB1LENR, 21, RCC_D2CCIP2R, 12, 2, "i2c1", i2c_src1),
1115     KER_CLK(RCC_APB1LENR, 20, RCC_D2CCIP2R,  0, 3, "uart5", usart_src2),
1116     KER_CLK(RCC_APB1LENR, 19, RCC_D2CCIP2R,  0, 3, "uart4", usart_src2),
1117     KER_CLK(RCC_APB1LENR, 18, RCC_D2CCIP2R,  0, 3, "usart3", usart_src2),
1118     KER_CLK(RCC_APB1LENR, 17, RCC_D2CCIP2R,  0, 3, "usart2", usart_src2),
1119     KER_CLK(RCC_APB1LENR, 16, RCC_D2CCIP1R, 20, 2, "spdifrx", spdifrx_src),
1120     KER_CLK(RCC_APB1LENR, 15, RCC_D2CCIP1R, 16, 3, "spi3", spi_src1),
1121     KER_CLK(RCC_APB1LENR, 14, RCC_D2CCIP1R, 16, 3, "spi2", spi_src1),
1122     KER_CLK(RCC_APB1LENR,  9, RCC_D2CCIP2R, 28, 3, "lptim1", lptim_src1),
1123     KER_CLK(RCC_APB1HENR,  8, RCC_D2CCIP1R, 28, 2, "fdcan", fdcan_src),
1124     KER_CLK(RCC_APB1HENR,  2, RCC_D2CCIP1R, 31, 1, "swp", swp_src),
1125     KER_CLK(RCC_APB2ENR,  29, RCC_CFGR, 14, 1, "hrtim", hrtim_src),
1126     KER_CLK(RCC_APB2ENR,  28, RCC_D2CCIP1R, 24, 1, "dfsdm1", dfsdm1_src),
1127     KER_CLKF(RCC_APB2ENR,  24, RCC_D2CCIP1R,  6, 3, "sai3", sai_src,
1128          CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT),
1129     KER_CLKF(RCC_APB2ENR,  23, RCC_D2CCIP1R,  6, 3, "sai2", sai_src,
1130          CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT),
1131     KER_CLKF(RCC_APB2ENR,  22, RCC_D2CCIP1R,  0, 3, "sai1", sai_src,
1132          CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT),
1133     KER_CLK(RCC_APB2ENR,  20, RCC_D2CCIP1R, 16, 3, "spi5", spi_src2),
1134     KER_CLK(RCC_APB2ENR,  13, RCC_D2CCIP1R, 16, 3, "spi4", spi_src2),
1135     KER_CLK(RCC_APB2ENR,  12, RCC_D2CCIP1R, 16, 3, "spi1", spi_src1),
1136     KER_CLK(RCC_APB2ENR,   5, RCC_D2CCIP2R,  3, 3, "usart6", usart_src1),
1137     KER_CLK(RCC_APB2ENR,   4, RCC_D2CCIP2R,  3, 3, "usart1", usart_src1),
1138     KER_CLK(RCC_APB4ENR,  21, RCC_D3CCIPR,  24, 3, "sai4b", sai_src),
1139     KER_CLK(RCC_APB4ENR,  21, RCC_D3CCIPR,  21, 3, "sai4a", sai_src),
1140     KER_CLK(RCC_APB4ENR,  12, RCC_D3CCIPR,  13, 3, "lptim5", lptim_src2),
1141     KER_CLK(RCC_APB4ENR,  11, RCC_D3CCIPR,  13, 3, "lptim4", lptim_src2),
1142     KER_CLK(RCC_APB4ENR,  10, RCC_D3CCIPR,  13, 3, "lptim3", lptim_src2),
1143     KER_CLK(RCC_APB4ENR,   9, RCC_D3CCIPR,  10, 3, "lptim2", lptim_src2),
1144     KER_CLK(RCC_APB4ENR,   7, RCC_D3CCIPR,   8, 2, "i2c4", i2c_src2),
1145     KER_CLK(RCC_APB4ENR,   5, RCC_D3CCIPR,  28, 3, "spi6", spi_src3),
1146     KER_CLK(RCC_APB4ENR,   3, RCC_D3CCIPR,   0, 3, "lpuart1", lpuart1_src),
1147 };
1148 
1149 static struct composite_clk_gcfg kernel_clk_cfg = {
1150     M_CFG_MUX(NULL, 0),
1151     M_CFG_GATE(NULL, 0),
1152 };
1153 
1154 /* RTC clock */
1155 /*
1156  * RTC & LSE registers are protected against parasitic write access.
1157  * PWR_CR_DBP bit must be set to enable write access to RTC registers.
1158  */
1159 /* STM32_PWR_CR */
1160 #define PWR_CR              0x00
1161 /* STM32_PWR_CR bit field */
1162 #define PWR_CR_DBP          BIT(8)
1163 
1164 static struct composite_clk_gcfg rtc_clk_cfg = {
1165     M_CFG_MUX(NULL, 0),
1166     M_CFG_GATE(NULL, 0),
1167 };
1168 
1169 static const struct composite_clk_cfg rtc_clk =
1170     KER_CLK(RCC_BDCR, 15, RCC_BDCR, 8, 2, "rtc_ck", rtc_src);
1171 
1172 /* Micro-controller output clock */
1173 static struct composite_clk_gcfg mco_clk_cfg = {
1174     M_CFG_MUX(NULL, 0),
1175     M_CFG_DIV(NULL, CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO),
1176 };
1177 
1178 #define M_MCO_F(_name, _parents, _mux_offset,  _mux_shift, _mux_width,\
1179         _rate_offset, _rate_shift, _rate_width,\
1180         _flags)\
1181 {\
1182     .mux = &(struct muxdiv_cfg) {_mux_offset, _mux_shift, _mux_width },\
1183     .div = &(struct muxdiv_cfg) {_rate_offset, _rate_shift, _rate_width},\
1184     .gate = NULL,\
1185     .name = _name,\
1186     .parent_name = _parents,\
1187     .num_parents = ARRAY_SIZE(_parents),\
1188     .flags = _flags,\
1189 }
1190 
1191 static const struct composite_clk_cfg mco_clk[] = {
1192     M_MCO_F("mco1", mco_src1, RCC_CFGR, 22, 4, RCC_CFGR, 18, 4, 0),
1193     M_MCO_F("mco2", mco_src2, RCC_CFGR, 29, 3, RCC_CFGR, 25, 4, 0),
1194 };
1195 
1196 static void __init stm32h7_rcc_init(struct device_node *np)
1197 {
1198     struct clk_hw_onecell_data *clk_data;
1199     struct composite_cfg c_cfg;
1200     int n;
1201     const char *hse_clk, *lse_clk, *i2s_clk;
1202     struct regmap *pdrm;
1203 
1204     clk_data = kzalloc(struct_size(clk_data, hws, STM32H7_MAX_CLKS),
1205                GFP_KERNEL);
1206     if (!clk_data)
1207         return;
1208 
1209     clk_data->num = STM32H7_MAX_CLKS;
1210 
1211     hws = clk_data->hws;
1212 
1213     for (n = 0; n < STM32H7_MAX_CLKS; n++)
1214         hws[n] = ERR_PTR(-ENOENT);
1215 
1216     /* get RCC base @ from DT */
1217     base = of_iomap(np, 0);
1218     if (!base) {
1219         pr_err("%pOFn: unable to map resource", np);
1220         goto err_free_clks;
1221     }
1222 
1223     pdrm = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
1224     if (IS_ERR(pdrm))
1225         pr_warn("%s: Unable to get syscfg\n", __func__);
1226     else
1227         /* In any case disable backup domain write protection
1228          * and will never be enabled.
1229          * Needed by LSE & RTC clocks.
1230          */
1231         regmap_update_bits(pdrm, PWR_CR, PWR_CR_DBP, PWR_CR_DBP);
1232 
1233     /* Put parent names from DT */
1234     hse_clk = of_clk_get_parent_name(np, 0);
1235     lse_clk = of_clk_get_parent_name(np, 1);
1236     i2s_clk = of_clk_get_parent_name(np, 2);
1237 
1238     sai_src[3] = i2s_clk;
1239     spi_src1[3] = i2s_clk;
1240 
1241     /* Register Internal oscillators */
1242     clk_hw_register_fixed_rate(NULL, "clk-hsi", NULL, 0, 64000000);
1243     clk_hw_register_fixed_rate(NULL, "clk-csi", NULL, 0, 4000000);
1244     clk_hw_register_fixed_rate(NULL, "clk-lsi", NULL, 0, 32000);
1245     clk_hw_register_fixed_rate(NULL, "clk-rc48", NULL, 0, 48000);
1246 
1247     /* This clock is coming from outside. Frequencies unknown */
1248     hws[CK_DSI_PHY] = clk_hw_register_fixed_rate(NULL, "ck_dsi_phy", NULL,
1249             0, 0);
1250 
1251     hws[HSI_DIV] = clk_hw_register_divider(NULL, "hsidiv", "clk-hsi", 0,
1252             base + RCC_CR, 3, 2, CLK_DIVIDER_POWER_OF_TWO,
1253             &stm32rcc_lock);
1254 
1255     hws[HSE_1M] = clk_hw_register_divider(NULL, "hse_1M", "hse_ck", 0,
1256             base + RCC_CFGR, 8, 6, CLK_DIVIDER_ONE_BASED |
1257             CLK_DIVIDER_ALLOW_ZERO,
1258             &stm32rcc_lock);
1259 
1260     /* Mux system clocks */
1261     for (n = 0; n < ARRAY_SIZE(stm32_mclk); n++)
1262         hws[MCLK_BANK + n] = clk_hw_register_mux(NULL,
1263                 stm32_mclk[n].name,
1264                 stm32_mclk[n].parents,
1265                 stm32_mclk[n].num_parents,
1266                 stm32_mclk[n].flags,
1267                 stm32_mclk[n].offset + base,
1268                 stm32_mclk[n].shift,
1269                 stm32_mclk[n].width,
1270                 0,
1271                 &stm32rcc_lock);
1272 
1273     register_core_and_bus_clocks();
1274 
1275     /* Oscillary clocks */
1276     for (n = 0; n < ARRAY_SIZE(stm32_oclk); n++)
1277         hws[OSC_BANK + n] = clk_register_ready_gate(NULL,
1278                 stm32_oclk[n].name,
1279                 stm32_oclk[n].parent,
1280                 stm32_oclk[n].gate_offset + base,
1281                 stm32_oclk[n].bit_idx,
1282                 stm32_oclk[n].bit_rdy,
1283                 stm32_oclk[n].flags,
1284                 &stm32rcc_lock);
1285 
1286     hws[HSE_CK] = clk_register_ready_gate(NULL,
1287                 "hse_ck",
1288                 hse_clk,
1289                 RCC_CR + base,
1290                 16, 17,
1291                 0,
1292                 &stm32rcc_lock);
1293 
1294     hws[LSE_CK] = clk_register_ready_gate(NULL,
1295                 "lse_ck",
1296                 lse_clk,
1297                 RCC_BDCR + base,
1298                 0, 1,
1299                 0,
1300                 &stm32rcc_lock);
1301 
1302     hws[CSI_KER_DIV122 + n] = clk_hw_register_fixed_factor(NULL,
1303             "csi_ker_div122", "csi_ker", 0, 1, 122);
1304 
1305     /* PLLs */
1306     for (n = 0; n < ARRAY_SIZE(stm32_pll); n++) {
1307         int odf;
1308 
1309         /* Register the VCO */
1310         clk_register_stm32_pll(NULL, stm32_pll[n].name,
1311                 stm32_pll[n].parent_name, stm32_pll[n].flags,
1312                 stm32_pll[n].cfg,
1313                 &stm32rcc_lock);
1314 
1315         /* Register the 3 output dividers */
1316         for (odf = 0; odf < 3; odf++) {
1317             int idx = n * 3 + odf;
1318 
1319             get_cfg_composite_div(&odf_clk_gcfg, &stm32_odf[n][odf],
1320                     &c_cfg, &stm32rcc_lock);
1321 
1322             hws[ODF_BANK + idx] = clk_hw_register_composite(NULL,
1323                     stm32_odf[n][odf].name,
1324                     stm32_odf[n][odf].parent_name,
1325                     stm32_odf[n][odf].num_parents,
1326                     c_cfg.mux_hw, c_cfg.mux_ops,
1327                     c_cfg.div_hw, c_cfg.div_ops,
1328                     c_cfg.gate_hw, c_cfg.gate_ops,
1329                     stm32_odf[n][odf].flags);
1330         }
1331     }
1332 
1333     /* Peripheral clocks */
1334     for (n = 0; n < ARRAY_SIZE(pclk); n++)
1335         hws[PERIF_BANK + n] = clk_hw_register_gate(NULL, pclk[n].name,
1336                 pclk[n].parent,
1337                 pclk[n].flags, base + pclk[n].gate_offset,
1338                 pclk[n].bit_idx, pclk[n].flags, &stm32rcc_lock);
1339 
1340     /* Kernel clocks */
1341     for (n = 0; n < ARRAY_SIZE(kclk); n++) {
1342         get_cfg_composite_div(&kernel_clk_cfg, &kclk[n], &c_cfg,
1343                 &stm32rcc_lock);
1344 
1345         hws[KERN_BANK + n] = clk_hw_register_composite(NULL,
1346                 kclk[n].name,
1347                 kclk[n].parent_name,
1348                 kclk[n].num_parents,
1349                 c_cfg.mux_hw, c_cfg.mux_ops,
1350                 c_cfg.div_hw, c_cfg.div_ops,
1351                 c_cfg.gate_hw, c_cfg.gate_ops,
1352                 kclk[n].flags);
1353     }
1354 
1355     /* RTC clock (default state is off) */
1356     clk_hw_register_fixed_rate(NULL, "off", NULL, 0, 0);
1357 
1358     get_cfg_composite_div(&rtc_clk_cfg, &rtc_clk, &c_cfg, &stm32rcc_lock);
1359 
1360     hws[RTC_CK] = clk_hw_register_composite(NULL,
1361             rtc_clk.name,
1362             rtc_clk.parent_name,
1363             rtc_clk.num_parents,
1364             c_cfg.mux_hw, c_cfg.mux_ops,
1365             c_cfg.div_hw, c_cfg.div_ops,
1366             c_cfg.gate_hw, c_cfg.gate_ops,
1367             rtc_clk.flags);
1368 
1369     /* Micro-controller clocks */
1370     for (n = 0; n < ARRAY_SIZE(mco_clk); n++) {
1371         get_cfg_composite_div(&mco_clk_cfg, &mco_clk[n], &c_cfg,
1372                 &stm32rcc_lock);
1373 
1374         hws[MCO_BANK + n] = clk_hw_register_composite(NULL,
1375                 mco_clk[n].name,
1376                 mco_clk[n].parent_name,
1377                 mco_clk[n].num_parents,
1378                 c_cfg.mux_hw, c_cfg.mux_ops,
1379                 c_cfg.div_hw, c_cfg.div_ops,
1380                 c_cfg.gate_hw, c_cfg.gate_ops,
1381                 mco_clk[n].flags);
1382     }
1383 
1384     of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
1385 
1386     return;
1387 
1388 err_free_clks:
1389     kfree(clk_data);
1390 }
1391 
1392 /* The RCC node is a clock and reset controller, and these
1393  * functionalities are supported by different drivers that
1394  * matches the same compatible strings.
1395  */
1396 CLK_OF_DECLARE_DRIVER(stm32h7_rcc, "st,stm32h743-rcc", stm32h7_rcc_init);
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