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0008 #include <linux/clk-provider.h>
0009 #include <linux/err.h>
0010 #include <linux/io.h>
0011 #include <linux/iopoll.h>
0012 #include <linux/ioport.h>
0013 #include <linux/slab.h>
0014 #include <linux/spinlock.h>
0015 #include <linux/of.h>
0016 #include <linux/of_address.h>
0017 #include <linux/regmap.h>
0018 #include <linux/mfd/syscon.h>
0019
0020
0021
0022
0023
0024
0025 #include <dt-bindings/clock/stm32fx-clock.h>
0026
0027 #define STM32F4_RCC_CR 0x00
0028 #define STM32F4_RCC_PLLCFGR 0x04
0029 #define STM32F4_RCC_CFGR 0x08
0030 #define STM32F4_RCC_AHB1ENR 0x30
0031 #define STM32F4_RCC_AHB2ENR 0x34
0032 #define STM32F4_RCC_AHB3ENR 0x38
0033 #define STM32F4_RCC_APB1ENR 0x40
0034 #define STM32F4_RCC_APB2ENR 0x44
0035 #define STM32F4_RCC_BDCR 0x70
0036 #define STM32F4_RCC_CSR 0x74
0037 #define STM32F4_RCC_PLLI2SCFGR 0x84
0038 #define STM32F4_RCC_PLLSAICFGR 0x88
0039 #define STM32F4_RCC_DCKCFGR 0x8c
0040 #define STM32F7_RCC_DCKCFGR2 0x90
0041
0042 #define NONE -1
0043 #define NO_IDX NONE
0044 #define NO_MUX NONE
0045 #define NO_GATE NONE
0046
0047 struct stm32f4_gate_data {
0048 u8 offset;
0049 u8 bit_idx;
0050 const char *name;
0051 const char *parent_name;
0052 unsigned long flags;
0053 };
0054
0055 static const struct stm32f4_gate_data stm32f429_gates[] __initconst = {
0056 { STM32F4_RCC_AHB1ENR, 0, "gpioa", "ahb_div" },
0057 { STM32F4_RCC_AHB1ENR, 1, "gpiob", "ahb_div" },
0058 { STM32F4_RCC_AHB1ENR, 2, "gpioc", "ahb_div" },
0059 { STM32F4_RCC_AHB1ENR, 3, "gpiod", "ahb_div" },
0060 { STM32F4_RCC_AHB1ENR, 4, "gpioe", "ahb_div" },
0061 { STM32F4_RCC_AHB1ENR, 5, "gpiof", "ahb_div" },
0062 { STM32F4_RCC_AHB1ENR, 6, "gpiog", "ahb_div" },
0063 { STM32F4_RCC_AHB1ENR, 7, "gpioh", "ahb_div" },
0064 { STM32F4_RCC_AHB1ENR, 8, "gpioi", "ahb_div" },
0065 { STM32F4_RCC_AHB1ENR, 9, "gpioj", "ahb_div" },
0066 { STM32F4_RCC_AHB1ENR, 10, "gpiok", "ahb_div" },
0067 { STM32F4_RCC_AHB1ENR, 12, "crc", "ahb_div" },
0068 { STM32F4_RCC_AHB1ENR, 18, "bkpsra", "ahb_div" },
0069 { STM32F4_RCC_AHB1ENR, 20, "ccmdatam", "ahb_div" },
0070 { STM32F4_RCC_AHB1ENR, 21, "dma1", "ahb_div" },
0071 { STM32F4_RCC_AHB1ENR, 22, "dma2", "ahb_div" },
0072 { STM32F4_RCC_AHB1ENR, 23, "dma2d", "ahb_div" },
0073 { STM32F4_RCC_AHB1ENR, 25, "ethmac", "ahb_div" },
0074 { STM32F4_RCC_AHB1ENR, 26, "ethmactx", "ahb_div" },
0075 { STM32F4_RCC_AHB1ENR, 27, "ethmacrx", "ahb_div" },
0076 { STM32F4_RCC_AHB1ENR, 28, "ethmacptp", "ahb_div" },
0077 { STM32F4_RCC_AHB1ENR, 29, "otghs", "ahb_div" },
0078 { STM32F4_RCC_AHB1ENR, 30, "otghsulpi", "ahb_div" },
0079
0080 { STM32F4_RCC_AHB2ENR, 0, "dcmi", "ahb_div" },
0081 { STM32F4_RCC_AHB2ENR, 4, "cryp", "ahb_div" },
0082 { STM32F4_RCC_AHB2ENR, 5, "hash", "ahb_div" },
0083 { STM32F4_RCC_AHB2ENR, 6, "rng", "pll48" },
0084 { STM32F4_RCC_AHB2ENR, 7, "otgfs", "pll48" },
0085
0086 { STM32F4_RCC_AHB3ENR, 0, "fmc", "ahb_div",
0087 CLK_IGNORE_UNUSED },
0088
0089 { STM32F4_RCC_APB1ENR, 0, "tim2", "apb1_mul" },
0090 { STM32F4_RCC_APB1ENR, 1, "tim3", "apb1_mul" },
0091 { STM32F4_RCC_APB1ENR, 2, "tim4", "apb1_mul" },
0092 { STM32F4_RCC_APB1ENR, 3, "tim5", "apb1_mul" },
0093 { STM32F4_RCC_APB1ENR, 4, "tim6", "apb1_mul" },
0094 { STM32F4_RCC_APB1ENR, 5, "tim7", "apb1_mul" },
0095 { STM32F4_RCC_APB1ENR, 6, "tim12", "apb1_mul" },
0096 { STM32F4_RCC_APB1ENR, 7, "tim13", "apb1_mul" },
0097 { STM32F4_RCC_APB1ENR, 8, "tim14", "apb1_mul" },
0098 { STM32F4_RCC_APB1ENR, 11, "wwdg", "apb1_div" },
0099 { STM32F4_RCC_APB1ENR, 14, "spi2", "apb1_div" },
0100 { STM32F4_RCC_APB1ENR, 15, "spi3", "apb1_div" },
0101 { STM32F4_RCC_APB1ENR, 17, "uart2", "apb1_div" },
0102 { STM32F4_RCC_APB1ENR, 18, "uart3", "apb1_div" },
0103 { STM32F4_RCC_APB1ENR, 19, "uart4", "apb1_div" },
0104 { STM32F4_RCC_APB1ENR, 20, "uart5", "apb1_div" },
0105 { STM32F4_RCC_APB1ENR, 21, "i2c1", "apb1_div" },
0106 { STM32F4_RCC_APB1ENR, 22, "i2c2", "apb1_div" },
0107 { STM32F4_RCC_APB1ENR, 23, "i2c3", "apb1_div" },
0108 { STM32F4_RCC_APB1ENR, 25, "can1", "apb1_div" },
0109 { STM32F4_RCC_APB1ENR, 26, "can2", "apb1_div" },
0110 { STM32F4_RCC_APB1ENR, 28, "pwr", "apb1_div" },
0111 { STM32F4_RCC_APB1ENR, 29, "dac", "apb1_div" },
0112 { STM32F4_RCC_APB1ENR, 30, "uart7", "apb1_div" },
0113 { STM32F4_RCC_APB1ENR, 31, "uart8", "apb1_div" },
0114
0115 { STM32F4_RCC_APB2ENR, 0, "tim1", "apb2_mul" },
0116 { STM32F4_RCC_APB2ENR, 1, "tim8", "apb2_mul" },
0117 { STM32F4_RCC_APB2ENR, 4, "usart1", "apb2_div" },
0118 { STM32F4_RCC_APB2ENR, 5, "usart6", "apb2_div" },
0119 { STM32F4_RCC_APB2ENR, 8, "adc1", "apb2_div" },
0120 { STM32F4_RCC_APB2ENR, 9, "adc2", "apb2_div" },
0121 { STM32F4_RCC_APB2ENR, 10, "adc3", "apb2_div" },
0122 { STM32F4_RCC_APB2ENR, 11, "sdio", "pll48" },
0123 { STM32F4_RCC_APB2ENR, 12, "spi1", "apb2_div" },
0124 { STM32F4_RCC_APB2ENR, 13, "spi4", "apb2_div" },
0125 { STM32F4_RCC_APB2ENR, 14, "syscfg", "apb2_div" },
0126 { STM32F4_RCC_APB2ENR, 16, "tim9", "apb2_mul" },
0127 { STM32F4_RCC_APB2ENR, 17, "tim10", "apb2_mul" },
0128 { STM32F4_RCC_APB2ENR, 18, "tim11", "apb2_mul" },
0129 { STM32F4_RCC_APB2ENR, 20, "spi5", "apb2_div" },
0130 { STM32F4_RCC_APB2ENR, 21, "spi6", "apb2_div" },
0131 { STM32F4_RCC_APB2ENR, 22, "sai1", "apb2_div" },
0132 };
0133
0134 static const struct stm32f4_gate_data stm32f469_gates[] __initconst = {
0135 { STM32F4_RCC_AHB1ENR, 0, "gpioa", "ahb_div" },
0136 { STM32F4_RCC_AHB1ENR, 1, "gpiob", "ahb_div" },
0137 { STM32F4_RCC_AHB1ENR, 2, "gpioc", "ahb_div" },
0138 { STM32F4_RCC_AHB1ENR, 3, "gpiod", "ahb_div" },
0139 { STM32F4_RCC_AHB1ENR, 4, "gpioe", "ahb_div" },
0140 { STM32F4_RCC_AHB1ENR, 5, "gpiof", "ahb_div" },
0141 { STM32F4_RCC_AHB1ENR, 6, "gpiog", "ahb_div" },
0142 { STM32F4_RCC_AHB1ENR, 7, "gpioh", "ahb_div" },
0143 { STM32F4_RCC_AHB1ENR, 8, "gpioi", "ahb_div" },
0144 { STM32F4_RCC_AHB1ENR, 9, "gpioj", "ahb_div" },
0145 { STM32F4_RCC_AHB1ENR, 10, "gpiok", "ahb_div" },
0146 { STM32F4_RCC_AHB1ENR, 12, "crc", "ahb_div" },
0147 { STM32F4_RCC_AHB1ENR, 18, "bkpsra", "ahb_div" },
0148 { STM32F4_RCC_AHB1ENR, 20, "ccmdatam", "ahb_div" },
0149 { STM32F4_RCC_AHB1ENR, 21, "dma1", "ahb_div" },
0150 { STM32F4_RCC_AHB1ENR, 22, "dma2", "ahb_div" },
0151 { STM32F4_RCC_AHB1ENR, 23, "dma2d", "ahb_div" },
0152 { STM32F4_RCC_AHB1ENR, 25, "ethmac", "ahb_div" },
0153 { STM32F4_RCC_AHB1ENR, 26, "ethmactx", "ahb_div" },
0154 { STM32F4_RCC_AHB1ENR, 27, "ethmacrx", "ahb_div" },
0155 { STM32F4_RCC_AHB1ENR, 28, "ethmacptp", "ahb_div" },
0156 { STM32F4_RCC_AHB1ENR, 29, "otghs", "ahb_div" },
0157 { STM32F4_RCC_AHB1ENR, 30, "otghsulpi", "ahb_div" },
0158
0159 { STM32F4_RCC_AHB2ENR, 0, "dcmi", "ahb_div" },
0160 { STM32F4_RCC_AHB2ENR, 4, "cryp", "ahb_div" },
0161 { STM32F4_RCC_AHB2ENR, 5, "hash", "ahb_div" },
0162 { STM32F4_RCC_AHB2ENR, 6, "rng", "pll48" },
0163 { STM32F4_RCC_AHB2ENR, 7, "otgfs", "pll48" },
0164
0165 { STM32F4_RCC_AHB3ENR, 0, "fmc", "ahb_div",
0166 CLK_IGNORE_UNUSED },
0167 { STM32F4_RCC_AHB3ENR, 1, "qspi", "ahb_div",
0168 CLK_IGNORE_UNUSED },
0169
0170 { STM32F4_RCC_APB1ENR, 0, "tim2", "apb1_mul" },
0171 { STM32F4_RCC_APB1ENR, 1, "tim3", "apb1_mul" },
0172 { STM32F4_RCC_APB1ENR, 2, "tim4", "apb1_mul" },
0173 { STM32F4_RCC_APB1ENR, 3, "tim5", "apb1_mul" },
0174 { STM32F4_RCC_APB1ENR, 4, "tim6", "apb1_mul" },
0175 { STM32F4_RCC_APB1ENR, 5, "tim7", "apb1_mul" },
0176 { STM32F4_RCC_APB1ENR, 6, "tim12", "apb1_mul" },
0177 { STM32F4_RCC_APB1ENR, 7, "tim13", "apb1_mul" },
0178 { STM32F4_RCC_APB1ENR, 8, "tim14", "apb1_mul" },
0179 { STM32F4_RCC_APB1ENR, 11, "wwdg", "apb1_div" },
0180 { STM32F4_RCC_APB1ENR, 14, "spi2", "apb1_div" },
0181 { STM32F4_RCC_APB1ENR, 15, "spi3", "apb1_div" },
0182 { STM32F4_RCC_APB1ENR, 17, "uart2", "apb1_div" },
0183 { STM32F4_RCC_APB1ENR, 18, "uart3", "apb1_div" },
0184 { STM32F4_RCC_APB1ENR, 19, "uart4", "apb1_div" },
0185 { STM32F4_RCC_APB1ENR, 20, "uart5", "apb1_div" },
0186 { STM32F4_RCC_APB1ENR, 21, "i2c1", "apb1_div" },
0187 { STM32F4_RCC_APB1ENR, 22, "i2c2", "apb1_div" },
0188 { STM32F4_RCC_APB1ENR, 23, "i2c3", "apb1_div" },
0189 { STM32F4_RCC_APB1ENR, 25, "can1", "apb1_div" },
0190 { STM32F4_RCC_APB1ENR, 26, "can2", "apb1_div" },
0191 { STM32F4_RCC_APB1ENR, 28, "pwr", "apb1_div" },
0192 { STM32F4_RCC_APB1ENR, 29, "dac", "apb1_div" },
0193 { STM32F4_RCC_APB1ENR, 30, "uart7", "apb1_div" },
0194 { STM32F4_RCC_APB1ENR, 31, "uart8", "apb1_div" },
0195
0196 { STM32F4_RCC_APB2ENR, 0, "tim1", "apb2_mul" },
0197 { STM32F4_RCC_APB2ENR, 1, "tim8", "apb2_mul" },
0198 { STM32F4_RCC_APB2ENR, 4, "usart1", "apb2_div" },
0199 { STM32F4_RCC_APB2ENR, 5, "usart6", "apb2_div" },
0200 { STM32F4_RCC_APB2ENR, 8, "adc1", "apb2_div" },
0201 { STM32F4_RCC_APB2ENR, 9, "adc2", "apb2_div" },
0202 { STM32F4_RCC_APB2ENR, 10, "adc3", "apb2_div" },
0203 { STM32F4_RCC_APB2ENR, 11, "sdio", "sdmux" },
0204 { STM32F4_RCC_APB2ENR, 12, "spi1", "apb2_div" },
0205 { STM32F4_RCC_APB2ENR, 13, "spi4", "apb2_div" },
0206 { STM32F4_RCC_APB2ENR, 14, "syscfg", "apb2_div" },
0207 { STM32F4_RCC_APB2ENR, 16, "tim9", "apb2_mul" },
0208 { STM32F4_RCC_APB2ENR, 17, "tim10", "apb2_mul" },
0209 { STM32F4_RCC_APB2ENR, 18, "tim11", "apb2_mul" },
0210 { STM32F4_RCC_APB2ENR, 20, "spi5", "apb2_div" },
0211 { STM32F4_RCC_APB2ENR, 21, "spi6", "apb2_div" },
0212 { STM32F4_RCC_APB2ENR, 22, "sai1", "apb2_div" },
0213 };
0214
0215 static const struct stm32f4_gate_data stm32f746_gates[] __initconst = {
0216 { STM32F4_RCC_AHB1ENR, 0, "gpioa", "ahb_div" },
0217 { STM32F4_RCC_AHB1ENR, 1, "gpiob", "ahb_div" },
0218 { STM32F4_RCC_AHB1ENR, 2, "gpioc", "ahb_div" },
0219 { STM32F4_RCC_AHB1ENR, 3, "gpiod", "ahb_div" },
0220 { STM32F4_RCC_AHB1ENR, 4, "gpioe", "ahb_div" },
0221 { STM32F4_RCC_AHB1ENR, 5, "gpiof", "ahb_div" },
0222 { STM32F4_RCC_AHB1ENR, 6, "gpiog", "ahb_div" },
0223 { STM32F4_RCC_AHB1ENR, 7, "gpioh", "ahb_div" },
0224 { STM32F4_RCC_AHB1ENR, 8, "gpioi", "ahb_div" },
0225 { STM32F4_RCC_AHB1ENR, 9, "gpioj", "ahb_div" },
0226 { STM32F4_RCC_AHB1ENR, 10, "gpiok", "ahb_div" },
0227 { STM32F4_RCC_AHB1ENR, 12, "crc", "ahb_div" },
0228 { STM32F4_RCC_AHB1ENR, 18, "bkpsra", "ahb_div" },
0229 { STM32F4_RCC_AHB1ENR, 20, "dtcmram", "ahb_div" },
0230 { STM32F4_RCC_AHB1ENR, 21, "dma1", "ahb_div" },
0231 { STM32F4_RCC_AHB1ENR, 22, "dma2", "ahb_div" },
0232 { STM32F4_RCC_AHB1ENR, 23, "dma2d", "ahb_div" },
0233 { STM32F4_RCC_AHB1ENR, 25, "ethmac", "ahb_div" },
0234 { STM32F4_RCC_AHB1ENR, 26, "ethmactx", "ahb_div" },
0235 { STM32F4_RCC_AHB1ENR, 27, "ethmacrx", "ahb_div" },
0236 { STM32F4_RCC_AHB1ENR, 28, "ethmacptp", "ahb_div" },
0237 { STM32F4_RCC_AHB1ENR, 29, "otghs", "ahb_div" },
0238 { STM32F4_RCC_AHB1ENR, 30, "otghsulpi", "ahb_div" },
0239
0240 { STM32F4_RCC_AHB2ENR, 0, "dcmi", "ahb_div" },
0241 { STM32F4_RCC_AHB2ENR, 4, "cryp", "ahb_div" },
0242 { STM32F4_RCC_AHB2ENR, 5, "hash", "ahb_div" },
0243 { STM32F4_RCC_AHB2ENR, 6, "rng", "pll48" },
0244 { STM32F4_RCC_AHB2ENR, 7, "otgfs", "pll48" },
0245
0246 { STM32F4_RCC_AHB3ENR, 0, "fmc", "ahb_div",
0247 CLK_IGNORE_UNUSED },
0248 { STM32F4_RCC_AHB3ENR, 1, "qspi", "ahb_div",
0249 CLK_IGNORE_UNUSED },
0250
0251 { STM32F4_RCC_APB1ENR, 0, "tim2", "apb1_mul" },
0252 { STM32F4_RCC_APB1ENR, 1, "tim3", "apb1_mul" },
0253 { STM32F4_RCC_APB1ENR, 2, "tim4", "apb1_mul" },
0254 { STM32F4_RCC_APB1ENR, 3, "tim5", "apb1_mul" },
0255 { STM32F4_RCC_APB1ENR, 4, "tim6", "apb1_mul" },
0256 { STM32F4_RCC_APB1ENR, 5, "tim7", "apb1_mul" },
0257 { STM32F4_RCC_APB1ENR, 6, "tim12", "apb1_mul" },
0258 { STM32F4_RCC_APB1ENR, 7, "tim13", "apb1_mul" },
0259 { STM32F4_RCC_APB1ENR, 8, "tim14", "apb1_mul" },
0260 { STM32F4_RCC_APB1ENR, 11, "wwdg", "apb1_div" },
0261 { STM32F4_RCC_APB1ENR, 14, "spi2", "apb1_div" },
0262 { STM32F4_RCC_APB1ENR, 15, "spi3", "apb1_div" },
0263 { STM32F4_RCC_APB1ENR, 16, "spdifrx", "apb1_div" },
0264 { STM32F4_RCC_APB1ENR, 25, "can1", "apb1_div" },
0265 { STM32F4_RCC_APB1ENR, 26, "can2", "apb1_div" },
0266 { STM32F4_RCC_APB1ENR, 27, "cec", "apb1_div" },
0267 { STM32F4_RCC_APB1ENR, 28, "pwr", "apb1_div" },
0268 { STM32F4_RCC_APB1ENR, 29, "dac", "apb1_div" },
0269
0270 { STM32F4_RCC_APB2ENR, 0, "tim1", "apb2_mul" },
0271 { STM32F4_RCC_APB2ENR, 1, "tim8", "apb2_mul" },
0272 { STM32F4_RCC_APB2ENR, 7, "sdmmc2", "sdmux" },
0273 { STM32F4_RCC_APB2ENR, 8, "adc1", "apb2_div" },
0274 { STM32F4_RCC_APB2ENR, 9, "adc2", "apb2_div" },
0275 { STM32F4_RCC_APB2ENR, 10, "adc3", "apb2_div" },
0276 { STM32F4_RCC_APB2ENR, 11, "sdmmc", "sdmux" },
0277 { STM32F4_RCC_APB2ENR, 12, "spi1", "apb2_div" },
0278 { STM32F4_RCC_APB2ENR, 13, "spi4", "apb2_div" },
0279 { STM32F4_RCC_APB2ENR, 14, "syscfg", "apb2_div" },
0280 { STM32F4_RCC_APB2ENR, 16, "tim9", "apb2_mul" },
0281 { STM32F4_RCC_APB2ENR, 17, "tim10", "apb2_mul" },
0282 { STM32F4_RCC_APB2ENR, 18, "tim11", "apb2_mul" },
0283 { STM32F4_RCC_APB2ENR, 20, "spi5", "apb2_div" },
0284 { STM32F4_RCC_APB2ENR, 21, "spi6", "apb2_div" },
0285 { STM32F4_RCC_APB2ENR, 22, "sai1", "apb2_div" },
0286 { STM32F4_RCC_APB2ENR, 23, "sai2", "apb2_div" },
0287 };
0288
0289 static const struct stm32f4_gate_data stm32f769_gates[] __initconst = {
0290 { STM32F4_RCC_AHB1ENR, 0, "gpioa", "ahb_div" },
0291 { STM32F4_RCC_AHB1ENR, 1, "gpiob", "ahb_div" },
0292 { STM32F4_RCC_AHB1ENR, 2, "gpioc", "ahb_div" },
0293 { STM32F4_RCC_AHB1ENR, 3, "gpiod", "ahb_div" },
0294 { STM32F4_RCC_AHB1ENR, 4, "gpioe", "ahb_div" },
0295 { STM32F4_RCC_AHB1ENR, 5, "gpiof", "ahb_div" },
0296 { STM32F4_RCC_AHB1ENR, 6, "gpiog", "ahb_div" },
0297 { STM32F4_RCC_AHB1ENR, 7, "gpioh", "ahb_div" },
0298 { STM32F4_RCC_AHB1ENR, 8, "gpioi", "ahb_div" },
0299 { STM32F4_RCC_AHB1ENR, 9, "gpioj", "ahb_div" },
0300 { STM32F4_RCC_AHB1ENR, 10, "gpiok", "ahb_div" },
0301 { STM32F4_RCC_AHB1ENR, 12, "crc", "ahb_div" },
0302 { STM32F4_RCC_AHB1ENR, 18, "bkpsra", "ahb_div" },
0303 { STM32F4_RCC_AHB1ENR, 20, "dtcmram", "ahb_div" },
0304 { STM32F4_RCC_AHB1ENR, 21, "dma1", "ahb_div" },
0305 { STM32F4_RCC_AHB1ENR, 22, "dma2", "ahb_div" },
0306 { STM32F4_RCC_AHB1ENR, 23, "dma2d", "ahb_div" },
0307 { STM32F4_RCC_AHB1ENR, 25, "ethmac", "ahb_div" },
0308 { STM32F4_RCC_AHB1ENR, 26, "ethmactx", "ahb_div" },
0309 { STM32F4_RCC_AHB1ENR, 27, "ethmacrx", "ahb_div" },
0310 { STM32F4_RCC_AHB1ENR, 28, "ethmacptp", "ahb_div" },
0311 { STM32F4_RCC_AHB1ENR, 29, "otghs", "ahb_div" },
0312 { STM32F4_RCC_AHB1ENR, 30, "otghsulpi", "ahb_div" },
0313
0314 { STM32F4_RCC_AHB2ENR, 0, "dcmi", "ahb_div" },
0315 { STM32F4_RCC_AHB2ENR, 1, "jpeg", "ahb_div" },
0316 { STM32F4_RCC_AHB2ENR, 4, "cryp", "ahb_div" },
0317 { STM32F4_RCC_AHB2ENR, 5, "hash", "ahb_div" },
0318 { STM32F4_RCC_AHB2ENR, 6, "rng", "pll48" },
0319 { STM32F4_RCC_AHB2ENR, 7, "otgfs", "pll48" },
0320
0321 { STM32F4_RCC_AHB3ENR, 0, "fmc", "ahb_div",
0322 CLK_IGNORE_UNUSED },
0323 { STM32F4_RCC_AHB3ENR, 1, "qspi", "ahb_div",
0324 CLK_IGNORE_UNUSED },
0325
0326 { STM32F4_RCC_APB1ENR, 0, "tim2", "apb1_mul" },
0327 { STM32F4_RCC_APB1ENR, 1, "tim3", "apb1_mul" },
0328 { STM32F4_RCC_APB1ENR, 2, "tim4", "apb1_mul" },
0329 { STM32F4_RCC_APB1ENR, 3, "tim5", "apb1_mul" },
0330 { STM32F4_RCC_APB1ENR, 4, "tim6", "apb1_mul" },
0331 { STM32F4_RCC_APB1ENR, 5, "tim7", "apb1_mul" },
0332 { STM32F4_RCC_APB1ENR, 6, "tim12", "apb1_mul" },
0333 { STM32F4_RCC_APB1ENR, 7, "tim13", "apb1_mul" },
0334 { STM32F4_RCC_APB1ENR, 8, "tim14", "apb1_mul" },
0335 { STM32F4_RCC_APB1ENR, 10, "rtcapb", "apb1_mul" },
0336 { STM32F4_RCC_APB1ENR, 11, "wwdg", "apb1_div" },
0337 { STM32F4_RCC_APB1ENR, 13, "can3", "apb1_div" },
0338 { STM32F4_RCC_APB1ENR, 14, "spi2", "apb1_div" },
0339 { STM32F4_RCC_APB1ENR, 15, "spi3", "apb1_div" },
0340 { STM32F4_RCC_APB1ENR, 16, "spdifrx", "apb1_div" },
0341 { STM32F4_RCC_APB1ENR, 25, "can1", "apb1_div" },
0342 { STM32F4_RCC_APB1ENR, 26, "can2", "apb1_div" },
0343 { STM32F4_RCC_APB1ENR, 27, "cec", "apb1_div" },
0344 { STM32F4_RCC_APB1ENR, 28, "pwr", "apb1_div" },
0345 { STM32F4_RCC_APB1ENR, 29, "dac", "apb1_div" },
0346
0347 { STM32F4_RCC_APB2ENR, 0, "tim1", "apb2_mul" },
0348 { STM32F4_RCC_APB2ENR, 1, "tim8", "apb2_mul" },
0349 { STM32F4_RCC_APB2ENR, 7, "sdmmc2", "sdmux2" },
0350 { STM32F4_RCC_APB2ENR, 8, "adc1", "apb2_div" },
0351 { STM32F4_RCC_APB2ENR, 9, "adc2", "apb2_div" },
0352 { STM32F4_RCC_APB2ENR, 10, "adc3", "apb2_div" },
0353 { STM32F4_RCC_APB2ENR, 11, "sdmmc1", "sdmux1" },
0354 { STM32F4_RCC_APB2ENR, 12, "spi1", "apb2_div" },
0355 { STM32F4_RCC_APB2ENR, 13, "spi4", "apb2_div" },
0356 { STM32F4_RCC_APB2ENR, 14, "syscfg", "apb2_div" },
0357 { STM32F4_RCC_APB2ENR, 16, "tim9", "apb2_mul" },
0358 { STM32F4_RCC_APB2ENR, 17, "tim10", "apb2_mul" },
0359 { STM32F4_RCC_APB2ENR, 18, "tim11", "apb2_mul" },
0360 { STM32F4_RCC_APB2ENR, 20, "spi5", "apb2_div" },
0361 { STM32F4_RCC_APB2ENR, 21, "spi6", "apb2_div" },
0362 { STM32F4_RCC_APB2ENR, 22, "sai1", "apb2_div" },
0363 { STM32F4_RCC_APB2ENR, 23, "sai2", "apb2_div" },
0364 { STM32F4_RCC_APB2ENR, 30, "mdio", "apb2_div" },
0365 };
0366
0367
0368
0369
0370
0371 #define MAX_GATE_MAP 3
0372
0373 static const u64 stm32f42xx_gate_map[MAX_GATE_MAP] = { 0x000000f17ef417ffull,
0374 0x0000000000000001ull,
0375 0x04777f33f6fec9ffull };
0376
0377 static const u64 stm32f46xx_gate_map[MAX_GATE_MAP] = { 0x000000f17ef417ffull,
0378 0x0000000000000003ull,
0379 0x0c777f33f6fec9ffull };
0380
0381 static const u64 stm32f746_gate_map[MAX_GATE_MAP] = { 0x000000f17ef417ffull,
0382 0x0000000000000003ull,
0383 0x04f77f833e01c9ffull };
0384
0385 static const u64 stm32f769_gate_map[MAX_GATE_MAP] = { 0x000000f37ef417ffull,
0386 0x0000000000000003ull,
0387 0x44F77F833E01EDFFull };
0388
0389 static const u64 *stm32f4_gate_map;
0390
0391 static struct clk_hw **clks;
0392
0393 static DEFINE_SPINLOCK(stm32f4_clk_lock);
0394 static void __iomem *base;
0395
0396 static struct regmap *pdrm;
0397
0398 static int stm32fx_end_primary_clk;
0399
0400
0401
0402
0403
0404
0405
0406
0407
0408 struct clk_apb_mul {
0409 struct clk_hw hw;
0410 u8 bit_idx;
0411 };
0412
0413 #define to_clk_apb_mul(_hw) container_of(_hw, struct clk_apb_mul, hw)
0414
0415 static unsigned long clk_apb_mul_recalc_rate(struct clk_hw *hw,
0416 unsigned long parent_rate)
0417 {
0418 struct clk_apb_mul *am = to_clk_apb_mul(hw);
0419
0420 if (readl(base + STM32F4_RCC_CFGR) & BIT(am->bit_idx))
0421 return parent_rate * 2;
0422
0423 return parent_rate;
0424 }
0425
0426 static long clk_apb_mul_round_rate(struct clk_hw *hw, unsigned long rate,
0427 unsigned long *prate)
0428 {
0429 struct clk_apb_mul *am = to_clk_apb_mul(hw);
0430 unsigned long mult = 1;
0431
0432 if (readl(base + STM32F4_RCC_CFGR) & BIT(am->bit_idx))
0433 mult = 2;
0434
0435 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
0436 unsigned long best_parent = rate / mult;
0437
0438 *prate = clk_hw_round_rate(clk_hw_get_parent(hw), best_parent);
0439 }
0440
0441 return *prate * mult;
0442 }
0443
0444 static int clk_apb_mul_set_rate(struct clk_hw *hw, unsigned long rate,
0445 unsigned long parent_rate)
0446 {
0447
0448
0449
0450
0451
0452
0453 return 0;
0454 }
0455
0456 static const struct clk_ops clk_apb_mul_factor_ops = {
0457 .round_rate = clk_apb_mul_round_rate,
0458 .set_rate = clk_apb_mul_set_rate,
0459 .recalc_rate = clk_apb_mul_recalc_rate,
0460 };
0461
0462 static struct clk *clk_register_apb_mul(struct device *dev, const char *name,
0463 const char *parent_name,
0464 unsigned long flags, u8 bit_idx)
0465 {
0466 struct clk_apb_mul *am;
0467 struct clk_init_data init;
0468 struct clk *clk;
0469
0470 am = kzalloc(sizeof(*am), GFP_KERNEL);
0471 if (!am)
0472 return ERR_PTR(-ENOMEM);
0473
0474 am->bit_idx = bit_idx;
0475 am->hw.init = &init;
0476
0477 init.name = name;
0478 init.ops = &clk_apb_mul_factor_ops;
0479 init.flags = flags;
0480 init.parent_names = &parent_name;
0481 init.num_parents = 1;
0482
0483 clk = clk_register(dev, &am->hw);
0484
0485 if (IS_ERR(clk))
0486 kfree(am);
0487
0488 return clk;
0489 }
0490
0491 enum {
0492 PLL,
0493 PLL_I2S,
0494 PLL_SAI,
0495 };
0496
0497 static const struct clk_div_table pll_divp_table[] = {
0498 { 0, 2 }, { 1, 4 }, { 2, 6 }, { 3, 8 }, { 0 }
0499 };
0500
0501 static const struct clk_div_table pll_divq_table[] = {
0502 { 2, 2 }, { 3, 3 }, { 4, 4 }, { 5, 5 }, { 6, 6 }, { 7, 7 },
0503 { 8, 8 }, { 9, 9 }, { 10, 10 }, { 11, 11 }, { 12, 12 }, { 13, 13 },
0504 { 14, 14 }, { 15, 15 },
0505 { 0 }
0506 };
0507
0508 static const struct clk_div_table pll_divr_table[] = {
0509 { 2, 2 }, { 3, 3 }, { 4, 4 }, { 5, 5 }, { 6, 6 }, { 7, 7 }, { 0 }
0510 };
0511
0512 struct stm32f4_pll {
0513 spinlock_t *lock;
0514 struct clk_gate gate;
0515 u8 offset;
0516 u8 bit_rdy_idx;
0517 u8 status;
0518 u8 n_start;
0519 };
0520
0521 #define to_stm32f4_pll(_gate) container_of(_gate, struct stm32f4_pll, gate)
0522
0523 struct stm32f4_pll_post_div_data {
0524 int idx;
0525 int pll_idx;
0526 const char *name;
0527 const char *parent;
0528 u8 flag;
0529 u8 offset;
0530 u8 shift;
0531 u8 width;
0532 u8 flag_div;
0533 const struct clk_div_table *div_table;
0534 };
0535
0536 struct stm32f4_vco_data {
0537 const char *vco_name;
0538 u8 offset;
0539 u8 bit_idx;
0540 u8 bit_rdy_idx;
0541 };
0542
0543 static const struct stm32f4_vco_data vco_data[] = {
0544 { "vco", STM32F4_RCC_PLLCFGR, 24, 25 },
0545 { "vco-i2s", STM32F4_RCC_PLLI2SCFGR, 26, 27 },
0546 { "vco-sai", STM32F4_RCC_PLLSAICFGR, 28, 29 },
0547 };
0548
0549
0550 static const struct clk_div_table post_divr_table[] = {
0551 { 0, 2 }, { 1, 4 }, { 2, 8 }, { 3, 16 }, { 0 }
0552 };
0553
0554 #define MAX_POST_DIV 3
0555 static const struct stm32f4_pll_post_div_data post_div_data[MAX_POST_DIV] = {
0556 { CLK_I2SQ_PDIV, PLL_VCO_I2S, "plli2s-q-div", "plli2s-q",
0557 CLK_SET_RATE_PARENT, STM32F4_RCC_DCKCFGR, 0, 5, 0, NULL},
0558
0559 { CLK_SAIQ_PDIV, PLL_VCO_SAI, "pllsai-q-div", "pllsai-q",
0560 CLK_SET_RATE_PARENT, STM32F4_RCC_DCKCFGR, 8, 5, 0, NULL },
0561
0562 { NO_IDX, PLL_VCO_SAI, "pllsai-r-div", "pllsai-r", CLK_SET_RATE_PARENT,
0563 STM32F4_RCC_DCKCFGR, 16, 2, 0, post_divr_table },
0564 };
0565
0566 struct stm32f4_div_data {
0567 u8 shift;
0568 u8 width;
0569 u8 flag_div;
0570 const struct clk_div_table *div_table;
0571 };
0572
0573 #define MAX_PLL_DIV 3
0574 static const struct stm32f4_div_data div_data[MAX_PLL_DIV] = {
0575 { 16, 2, 0, pll_divp_table },
0576 { 24, 4, 0, pll_divq_table },
0577 { 28, 3, 0, pll_divr_table },
0578 };
0579
0580 struct stm32f4_pll_data {
0581 u8 pll_num;
0582 u8 n_start;
0583 const char *div_name[MAX_PLL_DIV];
0584 };
0585
0586 static const struct stm32f4_pll_data stm32f429_pll[MAX_PLL_DIV] = {
0587 { PLL, 192, { "pll", "pll48", NULL } },
0588 { PLL_I2S, 192, { NULL, "plli2s-q", "plli2s-r" } },
0589 { PLL_SAI, 49, { NULL, "pllsai-q", "pllsai-r" } },
0590 };
0591
0592 static const struct stm32f4_pll_data stm32f469_pll[MAX_PLL_DIV] = {
0593 { PLL, 50, { "pll", "pll-q", "pll-r" } },
0594 { PLL_I2S, 50, { "plli2s-p", "plli2s-q", "plli2s-r" } },
0595 { PLL_SAI, 50, { "pllsai-p", "pllsai-q", "pllsai-r" } },
0596 };
0597
0598 static int stm32f4_pll_is_enabled(struct clk_hw *hw)
0599 {
0600 return clk_gate_ops.is_enabled(hw);
0601 }
0602
0603 #define PLL_TIMEOUT 10000
0604
0605 static int stm32f4_pll_enable(struct clk_hw *hw)
0606 {
0607 struct clk_gate *gate = to_clk_gate(hw);
0608 struct stm32f4_pll *pll = to_stm32f4_pll(gate);
0609 int bit_status;
0610 unsigned int timeout = PLL_TIMEOUT;
0611
0612 if (clk_gate_ops.is_enabled(hw))
0613 return 0;
0614
0615 clk_gate_ops.enable(hw);
0616
0617 do {
0618 bit_status = !(readl(gate->reg) & BIT(pll->bit_rdy_idx));
0619
0620 } while (bit_status && --timeout);
0621
0622 return bit_status;
0623 }
0624
0625 static void stm32f4_pll_disable(struct clk_hw *hw)
0626 {
0627 clk_gate_ops.disable(hw);
0628 }
0629
0630 static unsigned long stm32f4_pll_recalc(struct clk_hw *hw,
0631 unsigned long parent_rate)
0632 {
0633 struct clk_gate *gate = to_clk_gate(hw);
0634 struct stm32f4_pll *pll = to_stm32f4_pll(gate);
0635 unsigned long n;
0636
0637 n = (readl(base + pll->offset) >> 6) & 0x1ff;
0638
0639 return parent_rate * n;
0640 }
0641
0642 static long stm32f4_pll_round_rate(struct clk_hw *hw, unsigned long rate,
0643 unsigned long *prate)
0644 {
0645 struct clk_gate *gate = to_clk_gate(hw);
0646 struct stm32f4_pll *pll = to_stm32f4_pll(gate);
0647 unsigned long n;
0648
0649 n = rate / *prate;
0650
0651 if (n < pll->n_start)
0652 n = pll->n_start;
0653 else if (n > 432)
0654 n = 432;
0655
0656 return *prate * n;
0657 }
0658
0659 static int stm32f4_pll_set_rate(struct clk_hw *hw, unsigned long rate,
0660 unsigned long parent_rate)
0661 {
0662 struct clk_gate *gate = to_clk_gate(hw);
0663 struct stm32f4_pll *pll = to_stm32f4_pll(gate);
0664
0665 unsigned long n;
0666 unsigned long val;
0667 int pll_state;
0668
0669 pll_state = stm32f4_pll_is_enabled(hw);
0670
0671 if (pll_state)
0672 stm32f4_pll_disable(hw);
0673
0674 n = rate / parent_rate;
0675
0676 val = readl(base + pll->offset) & ~(0x1ff << 6);
0677
0678 writel(val | ((n & 0x1ff) << 6), base + pll->offset);
0679
0680 if (pll_state)
0681 stm32f4_pll_enable(hw);
0682
0683 return 0;
0684 }
0685
0686 static const struct clk_ops stm32f4_pll_gate_ops = {
0687 .enable = stm32f4_pll_enable,
0688 .disable = stm32f4_pll_disable,
0689 .is_enabled = stm32f4_pll_is_enabled,
0690 .recalc_rate = stm32f4_pll_recalc,
0691 .round_rate = stm32f4_pll_round_rate,
0692 .set_rate = stm32f4_pll_set_rate,
0693 };
0694
0695 struct stm32f4_pll_div {
0696 struct clk_divider div;
0697 struct clk_hw *hw_pll;
0698 };
0699
0700 #define to_pll_div_clk(_div) container_of(_div, struct stm32f4_pll_div, div)
0701
0702 static unsigned long stm32f4_pll_div_recalc_rate(struct clk_hw *hw,
0703 unsigned long parent_rate)
0704 {
0705 return clk_divider_ops.recalc_rate(hw, parent_rate);
0706 }
0707
0708 static int stm32f4_pll_div_determine_rate(struct clk_hw *hw,
0709 struct clk_rate_request *req)
0710 {
0711 return clk_divider_ops.determine_rate(hw, req);
0712 }
0713
0714 static int stm32f4_pll_div_set_rate(struct clk_hw *hw, unsigned long rate,
0715 unsigned long parent_rate)
0716 {
0717 int pll_state, ret;
0718
0719 struct clk_divider *div = to_clk_divider(hw);
0720 struct stm32f4_pll_div *pll_div = to_pll_div_clk(div);
0721
0722 pll_state = stm32f4_pll_is_enabled(pll_div->hw_pll);
0723
0724 if (pll_state)
0725 stm32f4_pll_disable(pll_div->hw_pll);
0726
0727 ret = clk_divider_ops.set_rate(hw, rate, parent_rate);
0728
0729 if (pll_state)
0730 stm32f4_pll_enable(pll_div->hw_pll);
0731
0732 return ret;
0733 }
0734
0735 static const struct clk_ops stm32f4_pll_div_ops = {
0736 .recalc_rate = stm32f4_pll_div_recalc_rate,
0737 .determine_rate = stm32f4_pll_div_determine_rate,
0738 .set_rate = stm32f4_pll_div_set_rate,
0739 };
0740
0741 static struct clk_hw *clk_register_pll_div(const char *name,
0742 const char *parent_name, unsigned long flags,
0743 void __iomem *reg, u8 shift, u8 width,
0744 u8 clk_divider_flags, const struct clk_div_table *table,
0745 struct clk_hw *pll_hw, spinlock_t *lock)
0746 {
0747 struct stm32f4_pll_div *pll_div;
0748 struct clk_hw *hw;
0749 struct clk_init_data init;
0750 int ret;
0751
0752
0753 pll_div = kzalloc(sizeof(*pll_div), GFP_KERNEL);
0754 if (!pll_div)
0755 return ERR_PTR(-ENOMEM);
0756
0757 init.name = name;
0758 init.ops = &stm32f4_pll_div_ops;
0759 init.flags = flags;
0760 init.parent_names = (parent_name ? &parent_name : NULL);
0761 init.num_parents = (parent_name ? 1 : 0);
0762
0763
0764 pll_div->div.reg = reg;
0765 pll_div->div.shift = shift;
0766 pll_div->div.width = width;
0767 pll_div->div.flags = clk_divider_flags;
0768 pll_div->div.lock = lock;
0769 pll_div->div.table = table;
0770 pll_div->div.hw.init = &init;
0771
0772 pll_div->hw_pll = pll_hw;
0773
0774
0775 hw = &pll_div->div.hw;
0776 ret = clk_hw_register(NULL, hw);
0777 if (ret) {
0778 kfree(pll_div);
0779 hw = ERR_PTR(ret);
0780 }
0781
0782 return hw;
0783 }
0784
0785 static struct clk_hw *stm32f4_rcc_register_pll(const char *pllsrc,
0786 const struct stm32f4_pll_data *data, spinlock_t *lock)
0787 {
0788 struct stm32f4_pll *pll;
0789 struct clk_init_data init = { NULL };
0790 void __iomem *reg;
0791 struct clk_hw *pll_hw;
0792 int ret;
0793 int i;
0794 const struct stm32f4_vco_data *vco;
0795
0796
0797 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
0798 if (!pll)
0799 return ERR_PTR(-ENOMEM);
0800
0801 vco = &vco_data[data->pll_num];
0802
0803 init.name = vco->vco_name;
0804 init.ops = &stm32f4_pll_gate_ops;
0805 init.flags = CLK_SET_RATE_GATE;
0806 init.parent_names = &pllsrc;
0807 init.num_parents = 1;
0808
0809 pll->gate.lock = lock;
0810 pll->gate.reg = base + STM32F4_RCC_CR;
0811 pll->gate.bit_idx = vco->bit_idx;
0812 pll->gate.hw.init = &init;
0813
0814 pll->offset = vco->offset;
0815 pll->n_start = data->n_start;
0816 pll->bit_rdy_idx = vco->bit_rdy_idx;
0817 pll->status = (readl(base + STM32F4_RCC_CR) >> vco->bit_idx) & 0x1;
0818
0819 reg = base + pll->offset;
0820
0821 pll_hw = &pll->gate.hw;
0822 ret = clk_hw_register(NULL, pll_hw);
0823 if (ret) {
0824 kfree(pll);
0825 return ERR_PTR(ret);
0826 }
0827
0828 for (i = 0; i < MAX_PLL_DIV; i++)
0829 if (data->div_name[i])
0830 clk_register_pll_div(data->div_name[i],
0831 vco->vco_name,
0832 0,
0833 reg,
0834 div_data[i].shift,
0835 div_data[i].width,
0836 div_data[i].flag_div,
0837 div_data[i].div_table,
0838 pll_hw,
0839 lock);
0840 return pll_hw;
0841 }
0842
0843
0844
0845
0846
0847 static int stm32f4_rcc_lookup_clk_idx(u8 primary, u8 secondary)
0848 {
0849 u64 table[MAX_GATE_MAP];
0850
0851 if (primary == 1) {
0852 if (WARN_ON(secondary >= stm32fx_end_primary_clk))
0853 return -EINVAL;
0854 return secondary;
0855 }
0856
0857 memcpy(table, stm32f4_gate_map, sizeof(table));
0858
0859
0860 if (WARN_ON(secondary >= BITS_PER_BYTE * sizeof(table) ||
0861 0 == (table[BIT_ULL_WORD(secondary)] &
0862 BIT_ULL_MASK(secondary))))
0863 return -EINVAL;
0864
0865
0866 table[BIT_ULL_WORD(secondary)] &=
0867 GENMASK_ULL(secondary % BITS_PER_LONG_LONG, 0);
0868
0869 return stm32fx_end_primary_clk - 1 + hweight64(table[0]) +
0870 (BIT_ULL_WORD(secondary) >= 1 ? hweight64(table[1]) : 0) +
0871 (BIT_ULL_WORD(secondary) >= 2 ? hweight64(table[2]) : 0);
0872 }
0873
0874 static struct clk_hw *
0875 stm32f4_rcc_lookup_clk(struct of_phandle_args *clkspec, void *data)
0876 {
0877 int i = stm32f4_rcc_lookup_clk_idx(clkspec->args[0], clkspec->args[1]);
0878
0879 if (i < 0)
0880 return ERR_PTR(-EINVAL);
0881
0882 return clks[i];
0883 }
0884
0885 #define to_rgclk(_rgate) container_of(_rgate, struct stm32_rgate, gate)
0886
0887 static inline void disable_power_domain_write_protection(void)
0888 {
0889 if (pdrm)
0890 regmap_update_bits(pdrm, 0x00, (1 << 8), (1 << 8));
0891 }
0892
0893 static inline void enable_power_domain_write_protection(void)
0894 {
0895 if (pdrm)
0896 regmap_update_bits(pdrm, 0x00, (1 << 8), (0 << 8));
0897 }
0898
0899 static inline void sofware_reset_backup_domain(void)
0900 {
0901 unsigned long val;
0902
0903 val = readl(base + STM32F4_RCC_BDCR);
0904 writel(val | BIT(16), base + STM32F4_RCC_BDCR);
0905 writel(val & ~BIT(16), base + STM32F4_RCC_BDCR);
0906 }
0907
0908 struct stm32_rgate {
0909 struct clk_gate gate;
0910 u8 bit_rdy_idx;
0911 };
0912
0913 #define RGATE_TIMEOUT 50000
0914
0915 static int rgclk_enable(struct clk_hw *hw)
0916 {
0917 struct clk_gate *gate = to_clk_gate(hw);
0918 struct stm32_rgate *rgate = to_rgclk(gate);
0919 int bit_status;
0920 unsigned int timeout = RGATE_TIMEOUT;
0921
0922 if (clk_gate_ops.is_enabled(hw))
0923 return 0;
0924
0925 disable_power_domain_write_protection();
0926
0927 clk_gate_ops.enable(hw);
0928
0929 do {
0930 bit_status = !(readl(gate->reg) & BIT(rgate->bit_rdy_idx));
0931 if (bit_status)
0932 udelay(100);
0933
0934 } while (bit_status && --timeout);
0935
0936 enable_power_domain_write_protection();
0937
0938 return bit_status;
0939 }
0940
0941 static void rgclk_disable(struct clk_hw *hw)
0942 {
0943 clk_gate_ops.disable(hw);
0944 }
0945
0946 static int rgclk_is_enabled(struct clk_hw *hw)
0947 {
0948 return clk_gate_ops.is_enabled(hw);
0949 }
0950
0951 static const struct clk_ops rgclk_ops = {
0952 .enable = rgclk_enable,
0953 .disable = rgclk_disable,
0954 .is_enabled = rgclk_is_enabled,
0955 };
0956
0957 static struct clk_hw *clk_register_rgate(struct device *dev, const char *name,
0958 const char *parent_name, unsigned long flags,
0959 void __iomem *reg, u8 bit_idx, u8 bit_rdy_idx,
0960 u8 clk_gate_flags, spinlock_t *lock)
0961 {
0962 struct stm32_rgate *rgate;
0963 struct clk_init_data init = { NULL };
0964 struct clk_hw *hw;
0965 int ret;
0966
0967 rgate = kzalloc(sizeof(*rgate), GFP_KERNEL);
0968 if (!rgate)
0969 return ERR_PTR(-ENOMEM);
0970
0971 init.name = name;
0972 init.ops = &rgclk_ops;
0973 init.flags = flags;
0974 init.parent_names = &parent_name;
0975 init.num_parents = 1;
0976
0977 rgate->bit_rdy_idx = bit_rdy_idx;
0978
0979 rgate->gate.lock = lock;
0980 rgate->gate.reg = reg;
0981 rgate->gate.bit_idx = bit_idx;
0982 rgate->gate.hw.init = &init;
0983
0984 hw = &rgate->gate.hw;
0985 ret = clk_hw_register(dev, hw);
0986 if (ret) {
0987 kfree(rgate);
0988 hw = ERR_PTR(ret);
0989 }
0990
0991 return hw;
0992 }
0993
0994 static int cclk_gate_enable(struct clk_hw *hw)
0995 {
0996 int ret;
0997
0998 disable_power_domain_write_protection();
0999
1000 ret = clk_gate_ops.enable(hw);
1001
1002 enable_power_domain_write_protection();
1003
1004 return ret;
1005 }
1006
1007 static void cclk_gate_disable(struct clk_hw *hw)
1008 {
1009 disable_power_domain_write_protection();
1010
1011 clk_gate_ops.disable(hw);
1012
1013 enable_power_domain_write_protection();
1014 }
1015
1016 static int cclk_gate_is_enabled(struct clk_hw *hw)
1017 {
1018 return clk_gate_ops.is_enabled(hw);
1019 }
1020
1021 static const struct clk_ops cclk_gate_ops = {
1022 .enable = cclk_gate_enable,
1023 .disable = cclk_gate_disable,
1024 .is_enabled = cclk_gate_is_enabled,
1025 };
1026
1027 static u8 cclk_mux_get_parent(struct clk_hw *hw)
1028 {
1029 return clk_mux_ops.get_parent(hw);
1030 }
1031
1032 static int cclk_mux_set_parent(struct clk_hw *hw, u8 index)
1033 {
1034 int ret;
1035
1036 disable_power_domain_write_protection();
1037
1038 sofware_reset_backup_domain();
1039
1040 ret = clk_mux_ops.set_parent(hw, index);
1041
1042 enable_power_domain_write_protection();
1043
1044 return ret;
1045 }
1046
1047 static const struct clk_ops cclk_mux_ops = {
1048 .get_parent = cclk_mux_get_parent,
1049 .set_parent = cclk_mux_set_parent,
1050 };
1051
1052 static struct clk_hw *stm32_register_cclk(struct device *dev, const char *name,
1053 const char * const *parent_names, int num_parents,
1054 void __iomem *reg, u8 bit_idx, u8 shift, unsigned long flags,
1055 spinlock_t *lock)
1056 {
1057 struct clk_hw *hw;
1058 struct clk_gate *gate;
1059 struct clk_mux *mux;
1060
1061 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
1062 if (!gate) {
1063 hw = ERR_PTR(-EINVAL);
1064 goto fail;
1065 }
1066
1067 mux = kzalloc(sizeof(*mux), GFP_KERNEL);
1068 if (!mux) {
1069 kfree(gate);
1070 hw = ERR_PTR(-EINVAL);
1071 goto fail;
1072 }
1073
1074 gate->reg = reg;
1075 gate->bit_idx = bit_idx;
1076 gate->flags = 0;
1077 gate->lock = lock;
1078
1079 mux->reg = reg;
1080 mux->shift = shift;
1081 mux->mask = 3;
1082 mux->flags = 0;
1083
1084 hw = clk_hw_register_composite(dev, name, parent_names, num_parents,
1085 &mux->hw, &cclk_mux_ops,
1086 NULL, NULL,
1087 &gate->hw, &cclk_gate_ops,
1088 flags);
1089
1090 if (IS_ERR(hw)) {
1091 kfree(gate);
1092 kfree(mux);
1093 }
1094
1095 fail:
1096 return hw;
1097 }
1098
1099 static const char *sys_parents[] __initdata = { "hsi", NULL, "pll" };
1100
1101 static const struct clk_div_table ahb_div_table[] = {
1102 { 0x0, 1 }, { 0x1, 1 }, { 0x2, 1 }, { 0x3, 1 },
1103 { 0x4, 1 }, { 0x5, 1 }, { 0x6, 1 }, { 0x7, 1 },
1104 { 0x8, 2 }, { 0x9, 4 }, { 0xa, 8 }, { 0xb, 16 },
1105 { 0xc, 64 }, { 0xd, 128 }, { 0xe, 256 }, { 0xf, 512 },
1106 { 0 },
1107 };
1108
1109 static const struct clk_div_table apb_div_table[] = {
1110 { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 },
1111 { 4, 2 }, { 5, 4 }, { 6, 8 }, { 7, 16 },
1112 { 0 },
1113 };
1114
1115 static const char *rtc_parents[4] = {
1116 "no-clock", "lse", "lsi", "hse-rtc"
1117 };
1118
1119 static const char *pll_src = "pll-src";
1120
1121 static const char *pllsrc_parent[2] = { "hsi", NULL };
1122
1123 static const char *dsi_parent[2] = { NULL, "pll-r" };
1124
1125 static const char *lcd_parent[1] = { "pllsai-r-div" };
1126
1127 static const char *i2s_parents[2] = { "plli2s-r", NULL };
1128
1129 static const char *sai_parents[4] = { "pllsai-q-div", "plli2s-q-div", NULL,
1130 "no-clock" };
1131
1132 static const char *pll48_parents[2] = { "pll-q", "pllsai-p" };
1133
1134 static const char *sdmux_parents[2] = { "pll48", "sys" };
1135
1136 static const char *hdmi_parents[2] = { "lse", "hsi_div488" };
1137
1138 static const char *spdif_parent[1] = { "plli2s-p" };
1139
1140 static const char *lptim_parent[4] = { "apb1_mul", "lsi", "hsi", "lse" };
1141
1142 static const char *uart_parents1[4] = { "apb2_div", "sys", "hsi", "lse" };
1143 static const char *uart_parents2[4] = { "apb1_div", "sys", "hsi", "lse" };
1144
1145 static const char *i2c_parents[4] = { "apb1_div", "sys", "hsi", "no-clock" };
1146
1147 static const char * const dfsdm1_src[] = { "apb2_div", "sys" };
1148 static const char * const adsfdm1_parent[] = { "sai1_clk", "sai2_clk" };
1149
1150 struct stm32_aux_clk {
1151 int idx;
1152 const char *name;
1153 const char * const *parent_names;
1154 int num_parents;
1155 int offset_mux;
1156 u8 shift;
1157 u8 mask;
1158 int offset_gate;
1159 u8 bit_idx;
1160 unsigned long flags;
1161 };
1162
1163 struct stm32f4_clk_data {
1164 const struct stm32f4_gate_data *gates_data;
1165 const u64 *gates_map;
1166 int gates_num;
1167 const struct stm32f4_pll_data *pll_data;
1168 const struct stm32_aux_clk *aux_clk;
1169 int aux_clk_num;
1170 int end_primary;
1171 };
1172
1173 static const struct stm32_aux_clk stm32f429_aux_clk[] = {
1174 {
1175 CLK_LCD, "lcd-tft", lcd_parent, ARRAY_SIZE(lcd_parent),
1176 NO_MUX, 0, 0,
1177 STM32F4_RCC_APB2ENR, 26,
1178 CLK_SET_RATE_PARENT
1179 },
1180 {
1181 CLK_I2S, "i2s", i2s_parents, ARRAY_SIZE(i2s_parents),
1182 STM32F4_RCC_CFGR, 23, 1,
1183 NO_GATE, 0,
1184 CLK_SET_RATE_PARENT
1185 },
1186 {
1187 CLK_SAI1, "sai1-a", sai_parents, ARRAY_SIZE(sai_parents),
1188 STM32F4_RCC_DCKCFGR, 20, 3,
1189 STM32F4_RCC_APB2ENR, 22,
1190 CLK_SET_RATE_PARENT
1191 },
1192 {
1193 CLK_SAI2, "sai1-b", sai_parents, ARRAY_SIZE(sai_parents),
1194 STM32F4_RCC_DCKCFGR, 22, 3,
1195 STM32F4_RCC_APB2ENR, 22,
1196 CLK_SET_RATE_PARENT
1197 },
1198 };
1199
1200 static const struct stm32_aux_clk stm32f469_aux_clk[] = {
1201 {
1202 CLK_LCD, "lcd-tft", lcd_parent, ARRAY_SIZE(lcd_parent),
1203 NO_MUX, 0, 0,
1204 STM32F4_RCC_APB2ENR, 26,
1205 CLK_SET_RATE_PARENT
1206 },
1207 {
1208 CLK_I2S, "i2s", i2s_parents, ARRAY_SIZE(i2s_parents),
1209 STM32F4_RCC_CFGR, 23, 1,
1210 NO_GATE, 0,
1211 CLK_SET_RATE_PARENT
1212 },
1213 {
1214 CLK_SAI1, "sai1-a", sai_parents, ARRAY_SIZE(sai_parents),
1215 STM32F4_RCC_DCKCFGR, 20, 3,
1216 STM32F4_RCC_APB2ENR, 22,
1217 CLK_SET_RATE_PARENT
1218 },
1219 {
1220 CLK_SAI2, "sai1-b", sai_parents, ARRAY_SIZE(sai_parents),
1221 STM32F4_RCC_DCKCFGR, 22, 3,
1222 STM32F4_RCC_APB2ENR, 22,
1223 CLK_SET_RATE_PARENT
1224 },
1225 {
1226 NO_IDX, "pll48", pll48_parents, ARRAY_SIZE(pll48_parents),
1227 STM32F4_RCC_DCKCFGR, 27, 1,
1228 NO_GATE, 0,
1229 0
1230 },
1231 {
1232 NO_IDX, "sdmux", sdmux_parents, ARRAY_SIZE(sdmux_parents),
1233 STM32F4_RCC_DCKCFGR, 28, 1,
1234 NO_GATE, 0,
1235 0
1236 },
1237 {
1238 CLK_F469_DSI, "dsi", dsi_parent, ARRAY_SIZE(dsi_parent),
1239 STM32F4_RCC_DCKCFGR, 29, 1,
1240 STM32F4_RCC_APB2ENR, 27,
1241 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT
1242 },
1243 };
1244
1245 static const struct stm32_aux_clk stm32f746_aux_clk[] = {
1246 {
1247 CLK_LCD, "lcd-tft", lcd_parent, ARRAY_SIZE(lcd_parent),
1248 NO_MUX, 0, 0,
1249 STM32F4_RCC_APB2ENR, 26,
1250 CLK_SET_RATE_PARENT
1251 },
1252 {
1253 CLK_I2S, "i2s", i2s_parents, ARRAY_SIZE(i2s_parents),
1254 STM32F4_RCC_CFGR, 23, 1,
1255 NO_GATE, 0,
1256 CLK_SET_RATE_PARENT
1257 },
1258 {
1259 CLK_SAI1, "sai1_clk", sai_parents, ARRAY_SIZE(sai_parents),
1260 STM32F4_RCC_DCKCFGR, 20, 3,
1261 STM32F4_RCC_APB2ENR, 22,
1262 CLK_SET_RATE_PARENT
1263 },
1264 {
1265 CLK_SAI2, "sai2_clk", sai_parents, ARRAY_SIZE(sai_parents),
1266 STM32F4_RCC_DCKCFGR, 22, 3,
1267 STM32F4_RCC_APB2ENR, 23,
1268 CLK_SET_RATE_PARENT
1269 },
1270 {
1271 NO_IDX, "pll48", pll48_parents, ARRAY_SIZE(pll48_parents),
1272 STM32F7_RCC_DCKCFGR2, 27, 1,
1273 NO_GATE, 0,
1274 0
1275 },
1276 {
1277 NO_IDX, "sdmux", sdmux_parents, ARRAY_SIZE(sdmux_parents),
1278 STM32F7_RCC_DCKCFGR2, 28, 1,
1279 NO_GATE, 0,
1280 0
1281 },
1282 {
1283 CLK_HDMI_CEC, "hdmi-cec",
1284 hdmi_parents, ARRAY_SIZE(hdmi_parents),
1285 STM32F7_RCC_DCKCFGR2, 26, 1,
1286 NO_GATE, 0,
1287 0
1288 },
1289 {
1290 CLK_SPDIF, "spdif-rx",
1291 spdif_parent, ARRAY_SIZE(spdif_parent),
1292 STM32F7_RCC_DCKCFGR2, 22, 3,
1293 STM32F4_RCC_APB2ENR, 23,
1294 CLK_SET_RATE_PARENT
1295 },
1296 {
1297 CLK_USART1, "usart1",
1298 uart_parents1, ARRAY_SIZE(uart_parents1),
1299 STM32F7_RCC_DCKCFGR2, 0, 3,
1300 STM32F4_RCC_APB2ENR, 4,
1301 CLK_SET_RATE_PARENT,
1302 },
1303 {
1304 CLK_USART2, "usart2",
1305 uart_parents2, ARRAY_SIZE(uart_parents1),
1306 STM32F7_RCC_DCKCFGR2, 2, 3,
1307 STM32F4_RCC_APB1ENR, 17,
1308 CLK_SET_RATE_PARENT,
1309 },
1310 {
1311 CLK_USART3, "usart3",
1312 uart_parents2, ARRAY_SIZE(uart_parents1),
1313 STM32F7_RCC_DCKCFGR2, 4, 3,
1314 STM32F4_RCC_APB1ENR, 18,
1315 CLK_SET_RATE_PARENT,
1316 },
1317 {
1318 CLK_UART4, "uart4",
1319 uart_parents2, ARRAY_SIZE(uart_parents1),
1320 STM32F7_RCC_DCKCFGR2, 6, 3,
1321 STM32F4_RCC_APB1ENR, 19,
1322 CLK_SET_RATE_PARENT,
1323 },
1324 {
1325 CLK_UART5, "uart5",
1326 uart_parents2, ARRAY_SIZE(uart_parents1),
1327 STM32F7_RCC_DCKCFGR2, 8, 3,
1328 STM32F4_RCC_APB1ENR, 20,
1329 CLK_SET_RATE_PARENT,
1330 },
1331 {
1332 CLK_USART6, "usart6",
1333 uart_parents1, ARRAY_SIZE(uart_parents1),
1334 STM32F7_RCC_DCKCFGR2, 10, 3,
1335 STM32F4_RCC_APB2ENR, 5,
1336 CLK_SET_RATE_PARENT,
1337 },
1338
1339 {
1340 CLK_UART7, "uart7",
1341 uart_parents2, ARRAY_SIZE(uart_parents1),
1342 STM32F7_RCC_DCKCFGR2, 12, 3,
1343 STM32F4_RCC_APB1ENR, 30,
1344 CLK_SET_RATE_PARENT,
1345 },
1346 {
1347 CLK_UART8, "uart8",
1348 uart_parents2, ARRAY_SIZE(uart_parents1),
1349 STM32F7_RCC_DCKCFGR2, 14, 3,
1350 STM32F4_RCC_APB1ENR, 31,
1351 CLK_SET_RATE_PARENT,
1352 },
1353 {
1354 CLK_I2C1, "i2c1",
1355 i2c_parents, ARRAY_SIZE(i2c_parents),
1356 STM32F7_RCC_DCKCFGR2, 16, 3,
1357 STM32F4_RCC_APB1ENR, 21,
1358 CLK_SET_RATE_PARENT,
1359 },
1360 {
1361 CLK_I2C2, "i2c2",
1362 i2c_parents, ARRAY_SIZE(i2c_parents),
1363 STM32F7_RCC_DCKCFGR2, 18, 3,
1364 STM32F4_RCC_APB1ENR, 22,
1365 CLK_SET_RATE_PARENT,
1366 },
1367 {
1368 CLK_I2C3, "i2c3",
1369 i2c_parents, ARRAY_SIZE(i2c_parents),
1370 STM32F7_RCC_DCKCFGR2, 20, 3,
1371 STM32F4_RCC_APB1ENR, 23,
1372 CLK_SET_RATE_PARENT,
1373 },
1374 {
1375 CLK_I2C4, "i2c4",
1376 i2c_parents, ARRAY_SIZE(i2c_parents),
1377 STM32F7_RCC_DCKCFGR2, 22, 3,
1378 STM32F4_RCC_APB1ENR, 24,
1379 CLK_SET_RATE_PARENT,
1380 },
1381
1382 {
1383 CLK_LPTIMER, "lptim1",
1384 lptim_parent, ARRAY_SIZE(lptim_parent),
1385 STM32F7_RCC_DCKCFGR2, 24, 3,
1386 STM32F4_RCC_APB1ENR, 9,
1387 CLK_SET_RATE_PARENT
1388 },
1389 };
1390
1391 static const struct stm32_aux_clk stm32f769_aux_clk[] = {
1392 {
1393 CLK_LCD, "lcd-tft", lcd_parent, ARRAY_SIZE(lcd_parent),
1394 NO_MUX, 0, 0,
1395 STM32F4_RCC_APB2ENR, 26,
1396 CLK_SET_RATE_PARENT
1397 },
1398 {
1399 CLK_I2S, "i2s", i2s_parents, ARRAY_SIZE(i2s_parents),
1400 STM32F4_RCC_CFGR, 23, 1,
1401 NO_GATE, 0,
1402 CLK_SET_RATE_PARENT
1403 },
1404 {
1405 CLK_SAI1, "sai1_clk", sai_parents, ARRAY_SIZE(sai_parents),
1406 STM32F4_RCC_DCKCFGR, 20, 3,
1407 STM32F4_RCC_APB2ENR, 22,
1408 CLK_SET_RATE_PARENT
1409 },
1410 {
1411 CLK_SAI2, "sai2_clk", sai_parents, ARRAY_SIZE(sai_parents),
1412 STM32F4_RCC_DCKCFGR, 22, 3,
1413 STM32F4_RCC_APB2ENR, 23,
1414 CLK_SET_RATE_PARENT
1415 },
1416 {
1417 NO_IDX, "pll48", pll48_parents, ARRAY_SIZE(pll48_parents),
1418 STM32F7_RCC_DCKCFGR2, 27, 1,
1419 NO_GATE, 0,
1420 0
1421 },
1422 {
1423 NO_IDX, "sdmux1", sdmux_parents, ARRAY_SIZE(sdmux_parents),
1424 STM32F7_RCC_DCKCFGR2, 28, 1,
1425 NO_GATE, 0,
1426 0
1427 },
1428 {
1429 NO_IDX, "sdmux2", sdmux_parents, ARRAY_SIZE(sdmux_parents),
1430 STM32F7_RCC_DCKCFGR2, 29, 1,
1431 NO_GATE, 0,
1432 0
1433 },
1434 {
1435 CLK_HDMI_CEC, "hdmi-cec",
1436 hdmi_parents, ARRAY_SIZE(hdmi_parents),
1437 STM32F7_RCC_DCKCFGR2, 26, 1,
1438 NO_GATE, 0,
1439 0
1440 },
1441 {
1442 CLK_SPDIF, "spdif-rx",
1443 spdif_parent, ARRAY_SIZE(spdif_parent),
1444 STM32F7_RCC_DCKCFGR2, 22, 3,
1445 STM32F4_RCC_APB2ENR, 23,
1446 CLK_SET_RATE_PARENT
1447 },
1448 {
1449 CLK_USART1, "usart1",
1450 uart_parents1, ARRAY_SIZE(uart_parents1),
1451 STM32F7_RCC_DCKCFGR2, 0, 3,
1452 STM32F4_RCC_APB2ENR, 4,
1453 CLK_SET_RATE_PARENT,
1454 },
1455 {
1456 CLK_USART2, "usart2",
1457 uart_parents2, ARRAY_SIZE(uart_parents1),
1458 STM32F7_RCC_DCKCFGR2, 2, 3,
1459 STM32F4_RCC_APB1ENR, 17,
1460 CLK_SET_RATE_PARENT,
1461 },
1462 {
1463 CLK_USART3, "usart3",
1464 uart_parents2, ARRAY_SIZE(uart_parents1),
1465 STM32F7_RCC_DCKCFGR2, 4, 3,
1466 STM32F4_RCC_APB1ENR, 18,
1467 CLK_SET_RATE_PARENT,
1468 },
1469 {
1470 CLK_UART4, "uart4",
1471 uart_parents2, ARRAY_SIZE(uart_parents1),
1472 STM32F7_RCC_DCKCFGR2, 6, 3,
1473 STM32F4_RCC_APB1ENR, 19,
1474 CLK_SET_RATE_PARENT,
1475 },
1476 {
1477 CLK_UART5, "uart5",
1478 uart_parents2, ARRAY_SIZE(uart_parents1),
1479 STM32F7_RCC_DCKCFGR2, 8, 3,
1480 STM32F4_RCC_APB1ENR, 20,
1481 CLK_SET_RATE_PARENT,
1482 },
1483 {
1484 CLK_USART6, "usart6",
1485 uart_parents1, ARRAY_SIZE(uart_parents1),
1486 STM32F7_RCC_DCKCFGR2, 10, 3,
1487 STM32F4_RCC_APB2ENR, 5,
1488 CLK_SET_RATE_PARENT,
1489 },
1490 {
1491 CLK_UART7, "uart7",
1492 uart_parents2, ARRAY_SIZE(uart_parents1),
1493 STM32F7_RCC_DCKCFGR2, 12, 3,
1494 STM32F4_RCC_APB1ENR, 30,
1495 CLK_SET_RATE_PARENT,
1496 },
1497 {
1498 CLK_UART8, "uart8",
1499 uart_parents2, ARRAY_SIZE(uart_parents1),
1500 STM32F7_RCC_DCKCFGR2, 14, 3,
1501 STM32F4_RCC_APB1ENR, 31,
1502 CLK_SET_RATE_PARENT,
1503 },
1504 {
1505 CLK_I2C1, "i2c1",
1506 i2c_parents, ARRAY_SIZE(i2c_parents),
1507 STM32F7_RCC_DCKCFGR2, 16, 3,
1508 STM32F4_RCC_APB1ENR, 21,
1509 CLK_SET_RATE_PARENT,
1510 },
1511 {
1512 CLK_I2C2, "i2c2",
1513 i2c_parents, ARRAY_SIZE(i2c_parents),
1514 STM32F7_RCC_DCKCFGR2, 18, 3,
1515 STM32F4_RCC_APB1ENR, 22,
1516 CLK_SET_RATE_PARENT,
1517 },
1518 {
1519 CLK_I2C3, "i2c3",
1520 i2c_parents, ARRAY_SIZE(i2c_parents),
1521 STM32F7_RCC_DCKCFGR2, 20, 3,
1522 STM32F4_RCC_APB1ENR, 23,
1523 CLK_SET_RATE_PARENT,
1524 },
1525 {
1526 CLK_I2C4, "i2c4",
1527 i2c_parents, ARRAY_SIZE(i2c_parents),
1528 STM32F7_RCC_DCKCFGR2, 22, 3,
1529 STM32F4_RCC_APB1ENR, 24,
1530 CLK_SET_RATE_PARENT,
1531 },
1532 {
1533 CLK_LPTIMER, "lptim1",
1534 lptim_parent, ARRAY_SIZE(lptim_parent),
1535 STM32F7_RCC_DCKCFGR2, 24, 3,
1536 STM32F4_RCC_APB1ENR, 9,
1537 CLK_SET_RATE_PARENT
1538 },
1539 {
1540 CLK_F769_DSI, "dsi",
1541 dsi_parent, ARRAY_SIZE(dsi_parent),
1542 STM32F7_RCC_DCKCFGR2, 0, 1,
1543 STM32F4_RCC_APB2ENR, 27,
1544 CLK_SET_RATE_PARENT
1545 },
1546 {
1547 CLK_DFSDM1, "dfsdm1",
1548 dfsdm1_src, ARRAY_SIZE(dfsdm1_src),
1549 STM32F4_RCC_DCKCFGR, 25, 1,
1550 STM32F4_RCC_APB2ENR, 29,
1551 CLK_SET_RATE_PARENT
1552 },
1553 {
1554 CLK_ADFSDM1, "adfsdm1",
1555 adsfdm1_parent, ARRAY_SIZE(adsfdm1_parent),
1556 STM32F4_RCC_DCKCFGR, 26, 1,
1557 STM32F4_RCC_APB2ENR, 29,
1558 CLK_SET_RATE_PARENT
1559 },
1560 };
1561
1562 static const struct stm32f4_clk_data stm32f429_clk_data = {
1563 .end_primary = END_PRIMARY_CLK,
1564 .gates_data = stm32f429_gates,
1565 .gates_map = stm32f42xx_gate_map,
1566 .gates_num = ARRAY_SIZE(stm32f429_gates),
1567 .pll_data = stm32f429_pll,
1568 .aux_clk = stm32f429_aux_clk,
1569 .aux_clk_num = ARRAY_SIZE(stm32f429_aux_clk),
1570 };
1571
1572 static const struct stm32f4_clk_data stm32f469_clk_data = {
1573 .end_primary = END_PRIMARY_CLK,
1574 .gates_data = stm32f469_gates,
1575 .gates_map = stm32f46xx_gate_map,
1576 .gates_num = ARRAY_SIZE(stm32f469_gates),
1577 .pll_data = stm32f469_pll,
1578 .aux_clk = stm32f469_aux_clk,
1579 .aux_clk_num = ARRAY_SIZE(stm32f469_aux_clk),
1580 };
1581
1582 static const struct stm32f4_clk_data stm32f746_clk_data = {
1583 .end_primary = END_PRIMARY_CLK_F7,
1584 .gates_data = stm32f746_gates,
1585 .gates_map = stm32f746_gate_map,
1586 .gates_num = ARRAY_SIZE(stm32f746_gates),
1587 .pll_data = stm32f469_pll,
1588 .aux_clk = stm32f746_aux_clk,
1589 .aux_clk_num = ARRAY_SIZE(stm32f746_aux_clk),
1590 };
1591
1592 static const struct stm32f4_clk_data stm32f769_clk_data = {
1593 .end_primary = END_PRIMARY_CLK_F7,
1594 .gates_data = stm32f769_gates,
1595 .gates_map = stm32f769_gate_map,
1596 .gates_num = ARRAY_SIZE(stm32f769_gates),
1597 .pll_data = stm32f469_pll,
1598 .aux_clk = stm32f769_aux_clk,
1599 .aux_clk_num = ARRAY_SIZE(stm32f769_aux_clk),
1600 };
1601
1602 static const struct of_device_id stm32f4_of_match[] = {
1603 {
1604 .compatible = "st,stm32f42xx-rcc",
1605 .data = &stm32f429_clk_data
1606 },
1607 {
1608 .compatible = "st,stm32f469-rcc",
1609 .data = &stm32f469_clk_data
1610 },
1611 {
1612 .compatible = "st,stm32f746-rcc",
1613 .data = &stm32f746_clk_data
1614 },
1615 {
1616 .compatible = "st,stm32f769-rcc",
1617 .data = &stm32f769_clk_data
1618 },
1619 {}
1620 };
1621
1622 static struct clk_hw *stm32_register_aux_clk(const char *name,
1623 const char * const *parent_names, int num_parents,
1624 int offset_mux, u8 shift, u8 mask,
1625 int offset_gate, u8 bit_idx,
1626 unsigned long flags, spinlock_t *lock)
1627 {
1628 struct clk_hw *hw;
1629 struct clk_gate *gate = NULL;
1630 struct clk_mux *mux = NULL;
1631 struct clk_hw *mux_hw = NULL, *gate_hw = NULL;
1632 const struct clk_ops *mux_ops = NULL, *gate_ops = NULL;
1633
1634 if (offset_gate != NO_GATE) {
1635 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
1636 if (!gate) {
1637 hw = ERR_PTR(-EINVAL);
1638 goto fail;
1639 }
1640
1641 gate->reg = base + offset_gate;
1642 gate->bit_idx = bit_idx;
1643 gate->flags = 0;
1644 gate->lock = lock;
1645 gate_hw = &gate->hw;
1646 gate_ops = &clk_gate_ops;
1647 }
1648
1649 if (offset_mux != NO_MUX) {
1650 mux = kzalloc(sizeof(*mux), GFP_KERNEL);
1651 if (!mux) {
1652 hw = ERR_PTR(-EINVAL);
1653 goto fail;
1654 }
1655
1656 mux->reg = base + offset_mux;
1657 mux->shift = shift;
1658 mux->mask = mask;
1659 mux->flags = 0;
1660 mux_hw = &mux->hw;
1661 mux_ops = &clk_mux_ops;
1662 }
1663
1664 if (mux_hw == NULL && gate_hw == NULL) {
1665 hw = ERR_PTR(-EINVAL);
1666 goto fail;
1667 }
1668
1669 hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
1670 mux_hw, mux_ops,
1671 NULL, NULL,
1672 gate_hw, gate_ops,
1673 flags);
1674
1675 fail:
1676 if (IS_ERR(hw)) {
1677 kfree(gate);
1678 kfree(mux);
1679 }
1680
1681 return hw;
1682 }
1683
1684 static void __init stm32f4_rcc_init(struct device_node *np)
1685 {
1686 const char *hse_clk, *i2s_in_clk;
1687 int n;
1688 const struct of_device_id *match;
1689 const struct stm32f4_clk_data *data;
1690 unsigned long pllm;
1691 struct clk_hw *pll_src_hw;
1692
1693 base = of_iomap(np, 0);
1694 if (!base) {
1695 pr_err("%pOFn: unable to map resource\n", np);
1696 return;
1697 }
1698
1699 pdrm = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
1700 if (IS_ERR(pdrm)) {
1701 pdrm = NULL;
1702 pr_warn("%s: Unable to get syscfg\n", __func__);
1703 }
1704
1705 match = of_match_node(stm32f4_of_match, np);
1706 if (WARN_ON(!match))
1707 return;
1708
1709 data = match->data;
1710
1711 stm32fx_end_primary_clk = data->end_primary;
1712
1713 clks = kmalloc_array(data->gates_num + stm32fx_end_primary_clk,
1714 sizeof(*clks), GFP_KERNEL);
1715 if (!clks)
1716 goto fail;
1717
1718 stm32f4_gate_map = data->gates_map;
1719
1720 hse_clk = of_clk_get_parent_name(np, 0);
1721 dsi_parent[0] = hse_clk;
1722 pllsrc_parent[1] = hse_clk;
1723
1724 i2s_in_clk = of_clk_get_parent_name(np, 1);
1725
1726 i2s_parents[1] = i2s_in_clk;
1727 sai_parents[2] = i2s_in_clk;
1728
1729 if (of_device_is_compatible(np, "st,stm32f769-rcc")) {
1730 clk_hw_register_gate(NULL, "dfsdm1_apb", "apb2_div", 0,
1731 base + STM32F4_RCC_APB2ENR, 29,
1732 CLK_IGNORE_UNUSED, &stm32f4_clk_lock);
1733 dsi_parent[0] = pll_src;
1734 sai_parents[3] = pll_src;
1735 }
1736
1737 clks[CLK_HSI] = clk_hw_register_fixed_rate_with_accuracy(NULL, "hsi",
1738 NULL, 0, 16000000, 160000);
1739
1740 pll_src_hw = clk_hw_register_mux(NULL, pll_src, pllsrc_parent,
1741 ARRAY_SIZE(pllsrc_parent), 0,
1742 base + STM32F4_RCC_PLLCFGR, 22, 1, 0,
1743 &stm32f4_clk_lock);
1744
1745 pllm = readl(base + STM32F4_RCC_PLLCFGR) & 0x3f;
1746
1747 clk_hw_register_fixed_factor(NULL, "vco_in", pll_src,
1748 0, 1, pllm);
1749
1750 stm32f4_rcc_register_pll("vco_in", &data->pll_data[0],
1751 &stm32f4_clk_lock);
1752
1753 clks[PLL_VCO_I2S] = stm32f4_rcc_register_pll("vco_in",
1754 &data->pll_data[1], &stm32f4_clk_lock);
1755
1756 clks[PLL_VCO_SAI] = stm32f4_rcc_register_pll("vco_in",
1757 &data->pll_data[2], &stm32f4_clk_lock);
1758
1759 for (n = 0; n < MAX_POST_DIV; n++) {
1760 const struct stm32f4_pll_post_div_data *post_div;
1761 struct clk_hw *hw;
1762
1763 post_div = &post_div_data[n];
1764
1765 hw = clk_register_pll_div(post_div->name,
1766 post_div->parent,
1767 post_div->flag,
1768 base + post_div->offset,
1769 post_div->shift,
1770 post_div->width,
1771 post_div->flag_div,
1772 post_div->div_table,
1773 clks[post_div->pll_idx],
1774 &stm32f4_clk_lock);
1775
1776 if (post_div->idx != NO_IDX)
1777 clks[post_div->idx] = hw;
1778 }
1779
1780 sys_parents[1] = hse_clk;
1781
1782 clks[CLK_SYSCLK] = clk_hw_register_mux_table(
1783 NULL, "sys", sys_parents, ARRAY_SIZE(sys_parents), 0,
1784 base + STM32F4_RCC_CFGR, 0, 3, 0, NULL, &stm32f4_clk_lock);
1785
1786 clk_register_divider_table(NULL, "ahb_div", "sys",
1787 CLK_SET_RATE_PARENT, base + STM32F4_RCC_CFGR,
1788 4, 4, 0, ahb_div_table, &stm32f4_clk_lock);
1789
1790 clk_register_divider_table(NULL, "apb1_div", "ahb_div",
1791 CLK_SET_RATE_PARENT, base + STM32F4_RCC_CFGR,
1792 10, 3, 0, apb_div_table, &stm32f4_clk_lock);
1793 clk_register_apb_mul(NULL, "apb1_mul", "apb1_div",
1794 CLK_SET_RATE_PARENT, 12);
1795
1796 clk_register_divider_table(NULL, "apb2_div", "ahb_div",
1797 CLK_SET_RATE_PARENT, base + STM32F4_RCC_CFGR,
1798 13, 3, 0, apb_div_table, &stm32f4_clk_lock);
1799 clk_register_apb_mul(NULL, "apb2_mul", "apb2_div",
1800 CLK_SET_RATE_PARENT, 15);
1801
1802 clks[SYSTICK] = clk_hw_register_fixed_factor(NULL, "systick", "ahb_div",
1803 0, 1, 8);
1804 clks[FCLK] = clk_hw_register_fixed_factor(NULL, "fclk", "ahb_div",
1805 0, 1, 1);
1806
1807 for (n = 0; n < data->gates_num; n++) {
1808 const struct stm32f4_gate_data *gd;
1809 unsigned int secondary;
1810 int idx;
1811
1812 gd = &data->gates_data[n];
1813 secondary = 8 * (gd->offset - STM32F4_RCC_AHB1ENR) +
1814 gd->bit_idx;
1815 idx = stm32f4_rcc_lookup_clk_idx(0, secondary);
1816
1817 if (idx < 0)
1818 goto fail;
1819
1820 clks[idx] = clk_hw_register_gate(
1821 NULL, gd->name, gd->parent_name, gd->flags,
1822 base + gd->offset, gd->bit_idx, 0, &stm32f4_clk_lock);
1823
1824 if (IS_ERR(clks[idx])) {
1825 pr_err("%pOF: Unable to register leaf clock %s\n",
1826 np, gd->name);
1827 goto fail;
1828 }
1829 }
1830
1831 clks[CLK_LSI] = clk_register_rgate(NULL, "lsi", "clk-lsi", 0,
1832 base + STM32F4_RCC_CSR, 0, 1, 0, &stm32f4_clk_lock);
1833
1834 if (IS_ERR(clks[CLK_LSI])) {
1835 pr_err("Unable to register lsi clock\n");
1836 goto fail;
1837 }
1838
1839 clks[CLK_LSE] = clk_register_rgate(NULL, "lse", "clk-lse", 0,
1840 base + STM32F4_RCC_BDCR, 0, 1, 0, &stm32f4_clk_lock);
1841
1842 if (IS_ERR(clks[CLK_LSE])) {
1843 pr_err("Unable to register lse clock\n");
1844 goto fail;
1845 }
1846
1847 clks[CLK_HSE_RTC] = clk_hw_register_divider(NULL, "hse-rtc", "clk-hse",
1848 0, base + STM32F4_RCC_CFGR, 16, 5, 0,
1849 &stm32f4_clk_lock);
1850
1851 if (IS_ERR(clks[CLK_HSE_RTC])) {
1852 pr_err("Unable to register hse-rtc clock\n");
1853 goto fail;
1854 }
1855
1856 clks[CLK_RTC] = stm32_register_cclk(NULL, "rtc", rtc_parents, 4,
1857 base + STM32F4_RCC_BDCR, 15, 8, 0, &stm32f4_clk_lock);
1858
1859 if (IS_ERR(clks[CLK_RTC])) {
1860 pr_err("Unable to register rtc clock\n");
1861 goto fail;
1862 }
1863
1864 for (n = 0; n < data->aux_clk_num; n++) {
1865 const struct stm32_aux_clk *aux_clk;
1866 struct clk_hw *hw;
1867
1868 aux_clk = &data->aux_clk[n];
1869
1870 hw = stm32_register_aux_clk(aux_clk->name,
1871 aux_clk->parent_names, aux_clk->num_parents,
1872 aux_clk->offset_mux, aux_clk->shift,
1873 aux_clk->mask, aux_clk->offset_gate,
1874 aux_clk->bit_idx, aux_clk->flags,
1875 &stm32f4_clk_lock);
1876
1877 if (IS_ERR(hw)) {
1878 pr_warn("Unable to register %s clk\n", aux_clk->name);
1879 continue;
1880 }
1881
1882 if (aux_clk->idx != NO_IDX)
1883 clks[aux_clk->idx] = hw;
1884 }
1885
1886 if (of_device_is_compatible(np, "st,stm32f746-rcc")) {
1887
1888 clk_hw_register_fixed_factor(NULL, "hsi_div488", "hsi", 0,
1889 1, 488);
1890
1891 clks[CLK_PLL_SRC] = pll_src_hw;
1892 }
1893
1894 of_clk_add_hw_provider(np, stm32f4_rcc_lookup_clk, NULL);
1895
1896 return;
1897 fail:
1898 kfree(clks);
1899 iounmap(base);
1900 }
1901 CLK_OF_DECLARE_DRIVER(stm32f42xx_rcc, "st,stm32f42xx-rcc", stm32f4_rcc_init);
1902 CLK_OF_DECLARE_DRIVER(stm32f46xx_rcc, "st,stm32f469-rcc", stm32f4_rcc_init);
1903 CLK_OF_DECLARE_DRIVER(stm32f746_rcc, "st,stm32f746-rcc", stm32f4_rcc_init);
1904 CLK_OF_DECLARE_DRIVER(stm32f769_rcc, "st,stm32f769-rcc", stm32f4_rcc_init);
