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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * clk-si5351.c: Skyworks / Silicon Labs Si5351A/B/C I2C Clock Generator
0004  *
0005  * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
0006  * Rabeeh Khoury <rabeeh@solid-run.com>
0007  *
0008  * References:
0009  * [1] "Si5351A/B/C Data Sheet"
0010  *     https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/Si5351-B.pdf
0011  * [2] "AN619: Manually Generating an Si5351 Register Map"
0012  *     https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/application-notes/AN619.pdf
0013  */
0014 
0015 #include <linux/module.h>
0016 #include <linux/kernel.h>
0017 #include <linux/clk.h>
0018 #include <linux/clk-provider.h>
0019 #include <linux/delay.h>
0020 #include <linux/err.h>
0021 #include <linux/errno.h>
0022 #include <linux/rational.h>
0023 #include <linux/i2c.h>
0024 #include <linux/of_platform.h>
0025 #include <linux/platform_data/si5351.h>
0026 #include <linux/regmap.h>
0027 #include <linux/slab.h>
0028 #include <linux/string.h>
0029 #include <asm/div64.h>
0030 
0031 #include "clk-si5351.h"
0032 
0033 struct si5351_driver_data;
0034 
0035 struct si5351_parameters {
0036     unsigned long   p1;
0037     unsigned long   p2;
0038     unsigned long   p3;
0039     int     valid;
0040 };
0041 
0042 struct si5351_hw_data {
0043     struct clk_hw           hw;
0044     struct si5351_driver_data   *drvdata;
0045     struct si5351_parameters    params;
0046     unsigned char           num;
0047 };
0048 
0049 struct si5351_driver_data {
0050     enum si5351_variant variant;
0051     struct i2c_client   *client;
0052     struct regmap       *regmap;
0053 
0054     struct clk      *pxtal;
0055     const char      *pxtal_name;
0056     struct clk_hw       xtal;
0057     struct clk      *pclkin;
0058     const char      *pclkin_name;
0059     struct clk_hw       clkin;
0060 
0061     struct si5351_hw_data   pll[2];
0062     struct si5351_hw_data   *msynth;
0063     struct si5351_hw_data   *clkout;
0064     size_t          num_clkout;
0065 };
0066 
0067 static const char * const si5351_input_names[] = {
0068     "xtal", "clkin"
0069 };
0070 static const char * const si5351_pll_names[] = {
0071     "si5351_plla", "si5351_pllb", "si5351_vxco"
0072 };
0073 static const char * const si5351_msynth_names[] = {
0074     "ms0", "ms1", "ms2", "ms3", "ms4", "ms5", "ms6", "ms7"
0075 };
0076 static const char * const si5351_clkout_names[] = {
0077     "clk0", "clk1", "clk2", "clk3", "clk4", "clk5", "clk6", "clk7"
0078 };
0079 
0080 /*
0081  * Si5351 i2c regmap
0082  */
0083 static inline u8 si5351_reg_read(struct si5351_driver_data *drvdata, u8 reg)
0084 {
0085     u32 val;
0086     int ret;
0087 
0088     ret = regmap_read(drvdata->regmap, reg, &val);
0089     if (ret) {
0090         dev_err(&drvdata->client->dev,
0091             "unable to read from reg%02x\n", reg);
0092         return 0;
0093     }
0094 
0095     return (u8)val;
0096 }
0097 
0098 static inline int si5351_bulk_read(struct si5351_driver_data *drvdata,
0099                    u8 reg, u8 count, u8 *buf)
0100 {
0101     return regmap_bulk_read(drvdata->regmap, reg, buf, count);
0102 }
0103 
0104 static inline int si5351_reg_write(struct si5351_driver_data *drvdata,
0105                    u8 reg, u8 val)
0106 {
0107     return regmap_write(drvdata->regmap, reg, val);
0108 }
0109 
0110 static inline int si5351_bulk_write(struct si5351_driver_data *drvdata,
0111                     u8 reg, u8 count, const u8 *buf)
0112 {
0113     return regmap_raw_write(drvdata->regmap, reg, buf, count);
0114 }
0115 
0116 static inline int si5351_set_bits(struct si5351_driver_data *drvdata,
0117                   u8 reg, u8 mask, u8 val)
0118 {
0119     return regmap_update_bits(drvdata->regmap, reg, mask, val);
0120 }
0121 
0122 static inline u8 si5351_msynth_params_address(int num)
0123 {
0124     if (num > 5)
0125         return SI5351_CLK6_PARAMETERS + (num - 6);
0126     return SI5351_CLK0_PARAMETERS + (SI5351_PARAMETERS_LENGTH * num);
0127 }
0128 
0129 static void si5351_read_parameters(struct si5351_driver_data *drvdata,
0130                    u8 reg, struct si5351_parameters *params)
0131 {
0132     u8 buf[SI5351_PARAMETERS_LENGTH];
0133 
0134     switch (reg) {
0135     case SI5351_CLK6_PARAMETERS:
0136     case SI5351_CLK7_PARAMETERS:
0137         buf[0] = si5351_reg_read(drvdata, reg);
0138         params->p1 = buf[0];
0139         params->p2 = 0;
0140         params->p3 = 1;
0141         break;
0142     default:
0143         si5351_bulk_read(drvdata, reg, SI5351_PARAMETERS_LENGTH, buf);
0144         params->p1 = ((buf[2] & 0x03) << 16) | (buf[3] << 8) | buf[4];
0145         params->p2 = ((buf[5] & 0x0f) << 16) | (buf[6] << 8) | buf[7];
0146         params->p3 = ((buf[5] & 0xf0) << 12) | (buf[0] << 8) | buf[1];
0147     }
0148     params->valid = 1;
0149 }
0150 
0151 static void si5351_write_parameters(struct si5351_driver_data *drvdata,
0152                     u8 reg, struct si5351_parameters *params)
0153 {
0154     u8 buf[SI5351_PARAMETERS_LENGTH];
0155 
0156     switch (reg) {
0157     case SI5351_CLK6_PARAMETERS:
0158     case SI5351_CLK7_PARAMETERS:
0159         buf[0] = params->p1 & 0xff;
0160         si5351_reg_write(drvdata, reg, buf[0]);
0161         break;
0162     default:
0163         buf[0] = ((params->p3 & 0x0ff00) >> 8) & 0xff;
0164         buf[1] = params->p3 & 0xff;
0165         /* save rdiv and divby4 */
0166         buf[2] = si5351_reg_read(drvdata, reg + 2) & ~0x03;
0167         buf[2] |= ((params->p1 & 0x30000) >> 16) & 0x03;
0168         buf[3] = ((params->p1 & 0x0ff00) >> 8) & 0xff;
0169         buf[4] = params->p1 & 0xff;
0170         buf[5] = ((params->p3 & 0xf0000) >> 12) |
0171             ((params->p2 & 0xf0000) >> 16);
0172         buf[6] = ((params->p2 & 0x0ff00) >> 8) & 0xff;
0173         buf[7] = params->p2 & 0xff;
0174         si5351_bulk_write(drvdata, reg, SI5351_PARAMETERS_LENGTH, buf);
0175     }
0176 }
0177 
0178 static bool si5351_regmap_is_volatile(struct device *dev, unsigned int reg)
0179 {
0180     switch (reg) {
0181     case SI5351_DEVICE_STATUS:
0182     case SI5351_INTERRUPT_STATUS:
0183     case SI5351_PLL_RESET:
0184         return true;
0185     }
0186     return false;
0187 }
0188 
0189 static bool si5351_regmap_is_writeable(struct device *dev, unsigned int reg)
0190 {
0191     /* reserved registers */
0192     if (reg >= 4 && reg <= 8)
0193         return false;
0194     if (reg >= 10 && reg <= 14)
0195         return false;
0196     if (reg >= 173 && reg <= 176)
0197         return false;
0198     if (reg >= 178 && reg <= 182)
0199         return false;
0200     /* read-only */
0201     if (reg == SI5351_DEVICE_STATUS)
0202         return false;
0203     return true;
0204 }
0205 
0206 static const struct regmap_config si5351_regmap_config = {
0207     .reg_bits = 8,
0208     .val_bits = 8,
0209     .cache_type = REGCACHE_RBTREE,
0210     .max_register = 187,
0211     .writeable_reg = si5351_regmap_is_writeable,
0212     .volatile_reg = si5351_regmap_is_volatile,
0213 };
0214 
0215 /*
0216  * Si5351 xtal clock input
0217  */
0218 static int si5351_xtal_prepare(struct clk_hw *hw)
0219 {
0220     struct si5351_driver_data *drvdata =
0221         container_of(hw, struct si5351_driver_data, xtal);
0222     si5351_set_bits(drvdata, SI5351_FANOUT_ENABLE,
0223             SI5351_XTAL_ENABLE, SI5351_XTAL_ENABLE);
0224     return 0;
0225 }
0226 
0227 static void si5351_xtal_unprepare(struct clk_hw *hw)
0228 {
0229     struct si5351_driver_data *drvdata =
0230         container_of(hw, struct si5351_driver_data, xtal);
0231     si5351_set_bits(drvdata, SI5351_FANOUT_ENABLE,
0232             SI5351_XTAL_ENABLE, 0);
0233 }
0234 
0235 static const struct clk_ops si5351_xtal_ops = {
0236     .prepare = si5351_xtal_prepare,
0237     .unprepare = si5351_xtal_unprepare,
0238 };
0239 
0240 /*
0241  * Si5351 clkin clock input (Si5351C only)
0242  */
0243 static int si5351_clkin_prepare(struct clk_hw *hw)
0244 {
0245     struct si5351_driver_data *drvdata =
0246         container_of(hw, struct si5351_driver_data, clkin);
0247     si5351_set_bits(drvdata, SI5351_FANOUT_ENABLE,
0248             SI5351_CLKIN_ENABLE, SI5351_CLKIN_ENABLE);
0249     return 0;
0250 }
0251 
0252 static void si5351_clkin_unprepare(struct clk_hw *hw)
0253 {
0254     struct si5351_driver_data *drvdata =
0255         container_of(hw, struct si5351_driver_data, clkin);
0256     si5351_set_bits(drvdata, SI5351_FANOUT_ENABLE,
0257             SI5351_CLKIN_ENABLE, 0);
0258 }
0259 
0260 /*
0261  * CMOS clock source constraints:
0262  * The input frequency range of the PLL is 10Mhz to 40MHz.
0263  * If CLKIN is >40MHz, the input divider must be used.
0264  */
0265 static unsigned long si5351_clkin_recalc_rate(struct clk_hw *hw,
0266                           unsigned long parent_rate)
0267 {
0268     struct si5351_driver_data *drvdata =
0269         container_of(hw, struct si5351_driver_data, clkin);
0270     unsigned long rate;
0271     unsigned char idiv;
0272 
0273     rate = parent_rate;
0274     if (parent_rate > 160000000) {
0275         idiv = SI5351_CLKIN_DIV_8;
0276         rate /= 8;
0277     } else if (parent_rate > 80000000) {
0278         idiv = SI5351_CLKIN_DIV_4;
0279         rate /= 4;
0280     } else if (parent_rate > 40000000) {
0281         idiv = SI5351_CLKIN_DIV_2;
0282         rate /= 2;
0283     } else {
0284         idiv = SI5351_CLKIN_DIV_1;
0285     }
0286 
0287     si5351_set_bits(drvdata, SI5351_PLL_INPUT_SOURCE,
0288             SI5351_CLKIN_DIV_MASK, idiv);
0289 
0290     dev_dbg(&drvdata->client->dev, "%s - clkin div = %d, rate = %lu\n",
0291         __func__, (1 << (idiv >> 6)), rate);
0292 
0293     return rate;
0294 }
0295 
0296 static const struct clk_ops si5351_clkin_ops = {
0297     .prepare = si5351_clkin_prepare,
0298     .unprepare = si5351_clkin_unprepare,
0299     .recalc_rate = si5351_clkin_recalc_rate,
0300 };
0301 
0302 /*
0303  * Si5351 vxco clock input (Si5351B only)
0304  */
0305 
0306 static int si5351_vxco_prepare(struct clk_hw *hw)
0307 {
0308     struct si5351_hw_data *hwdata =
0309         container_of(hw, struct si5351_hw_data, hw);
0310 
0311     dev_warn(&hwdata->drvdata->client->dev, "VXCO currently unsupported\n");
0312 
0313     return 0;
0314 }
0315 
0316 static void si5351_vxco_unprepare(struct clk_hw *hw)
0317 {
0318 }
0319 
0320 static unsigned long si5351_vxco_recalc_rate(struct clk_hw *hw,
0321                          unsigned long parent_rate)
0322 {
0323     return 0;
0324 }
0325 
0326 static int si5351_vxco_set_rate(struct clk_hw *hw, unsigned long rate,
0327                 unsigned long parent)
0328 {
0329     return 0;
0330 }
0331 
0332 static const struct clk_ops si5351_vxco_ops = {
0333     .prepare = si5351_vxco_prepare,
0334     .unprepare = si5351_vxco_unprepare,
0335     .recalc_rate = si5351_vxco_recalc_rate,
0336     .set_rate = si5351_vxco_set_rate,
0337 };
0338 
0339 /*
0340  * Si5351 pll a/b
0341  *
0342  * Feedback Multisynth Divider Equations [2]
0343  *
0344  * fVCO = fIN * (a + b/c)
0345  *
0346  * with 15 + 0/1048575 <= (a + b/c) <= 90 + 0/1048575 and
0347  * fIN = fXTAL or fIN = fCLKIN/CLKIN_DIV
0348  *
0349  * Feedback Multisynth Register Equations
0350  *
0351  * (1) MSNx_P1[17:0] = 128 * a + floor(128 * b/c) - 512
0352  * (2) MSNx_P2[19:0] = 128 * b - c * floor(128 * b/c) = (128*b) mod c
0353  * (3) MSNx_P3[19:0] = c
0354  *
0355  * Transposing (2) yields: (4) floor(128 * b/c) = (128 * b / MSNx_P2)/c
0356  *
0357  * Using (4) on (1) yields:
0358  * MSNx_P1 = 128 * a + (128 * b/MSNx_P2)/c - 512
0359  * MSNx_P1 + 512 + MSNx_P2/c = 128 * a + 128 * b/c
0360  *
0361  * a + b/c = (MSNx_P1 + MSNx_P2/MSNx_P3 + 512)/128
0362  *         = (MSNx_P1*MSNx_P3 + MSNx_P2 + 512*MSNx_P3)/(128*MSNx_P3)
0363  *
0364  */
0365 static int _si5351_pll_reparent(struct si5351_driver_data *drvdata,
0366                 int num, enum si5351_pll_src parent)
0367 {
0368     u8 mask = (num == 0) ? SI5351_PLLA_SOURCE : SI5351_PLLB_SOURCE;
0369 
0370     if (parent == SI5351_PLL_SRC_DEFAULT)
0371         return 0;
0372 
0373     if (num > 2)
0374         return -EINVAL;
0375 
0376     if (drvdata->variant != SI5351_VARIANT_C &&
0377         parent != SI5351_PLL_SRC_XTAL)
0378         return -EINVAL;
0379 
0380     si5351_set_bits(drvdata, SI5351_PLL_INPUT_SOURCE, mask,
0381             (parent == SI5351_PLL_SRC_XTAL) ? 0 : mask);
0382     return 0;
0383 }
0384 
0385 static unsigned char si5351_pll_get_parent(struct clk_hw *hw)
0386 {
0387     struct si5351_hw_data *hwdata =
0388         container_of(hw, struct si5351_hw_data, hw);
0389     u8 mask = (hwdata->num == 0) ? SI5351_PLLA_SOURCE : SI5351_PLLB_SOURCE;
0390     u8 val;
0391 
0392     val = si5351_reg_read(hwdata->drvdata, SI5351_PLL_INPUT_SOURCE);
0393 
0394     return (val & mask) ? 1 : 0;
0395 }
0396 
0397 static int si5351_pll_set_parent(struct clk_hw *hw, u8 index)
0398 {
0399     struct si5351_hw_data *hwdata =
0400         container_of(hw, struct si5351_hw_data, hw);
0401 
0402     if (hwdata->drvdata->variant != SI5351_VARIANT_C &&
0403         index > 0)
0404         return -EPERM;
0405 
0406     if (index > 1)
0407         return -EINVAL;
0408 
0409     return _si5351_pll_reparent(hwdata->drvdata, hwdata->num,
0410                  (index == 0) ? SI5351_PLL_SRC_XTAL :
0411                  SI5351_PLL_SRC_CLKIN);
0412 }
0413 
0414 static unsigned long si5351_pll_recalc_rate(struct clk_hw *hw,
0415                         unsigned long parent_rate)
0416 {
0417     struct si5351_hw_data *hwdata =
0418         container_of(hw, struct si5351_hw_data, hw);
0419     u8 reg = (hwdata->num == 0) ? SI5351_PLLA_PARAMETERS :
0420         SI5351_PLLB_PARAMETERS;
0421     unsigned long long rate;
0422 
0423     if (!hwdata->params.valid)
0424         si5351_read_parameters(hwdata->drvdata, reg, &hwdata->params);
0425 
0426     if (hwdata->params.p3 == 0)
0427         return parent_rate;
0428 
0429     /* fVCO = fIN * (P1*P3 + 512*P3 + P2)/(128*P3) */
0430     rate  = hwdata->params.p1 * hwdata->params.p3;
0431     rate += 512 * hwdata->params.p3;
0432     rate += hwdata->params.p2;
0433     rate *= parent_rate;
0434     do_div(rate, 128 * hwdata->params.p3);
0435 
0436     dev_dbg(&hwdata->drvdata->client->dev,
0437         "%s - %s: p1 = %lu, p2 = %lu, p3 = %lu, parent_rate = %lu, rate = %lu\n",
0438         __func__, clk_hw_get_name(hw),
0439         hwdata->params.p1, hwdata->params.p2, hwdata->params.p3,
0440         parent_rate, (unsigned long)rate);
0441 
0442     return (unsigned long)rate;
0443 }
0444 
0445 static long si5351_pll_round_rate(struct clk_hw *hw, unsigned long rate,
0446                   unsigned long *parent_rate)
0447 {
0448     struct si5351_hw_data *hwdata =
0449         container_of(hw, struct si5351_hw_data, hw);
0450     unsigned long rfrac, denom, a, b, c;
0451     unsigned long long lltmp;
0452 
0453     if (rate < SI5351_PLL_VCO_MIN)
0454         rate = SI5351_PLL_VCO_MIN;
0455     if (rate > SI5351_PLL_VCO_MAX)
0456         rate = SI5351_PLL_VCO_MAX;
0457 
0458     /* determine integer part of feedback equation */
0459     a = rate / *parent_rate;
0460 
0461     if (a < SI5351_PLL_A_MIN)
0462         rate = *parent_rate * SI5351_PLL_A_MIN;
0463     if (a > SI5351_PLL_A_MAX)
0464         rate = *parent_rate * SI5351_PLL_A_MAX;
0465 
0466     /* find best approximation for b/c = fVCO mod fIN */
0467     denom = 1000 * 1000;
0468     lltmp = rate % (*parent_rate);
0469     lltmp *= denom;
0470     do_div(lltmp, *parent_rate);
0471     rfrac = (unsigned long)lltmp;
0472 
0473     b = 0;
0474     c = 1;
0475     if (rfrac)
0476         rational_best_approximation(rfrac, denom,
0477                     SI5351_PLL_B_MAX, SI5351_PLL_C_MAX, &b, &c);
0478 
0479     /* calculate parameters */
0480     hwdata->params.p3  = c;
0481     hwdata->params.p2  = (128 * b) % c;
0482     hwdata->params.p1  = 128 * a;
0483     hwdata->params.p1 += (128 * b / c);
0484     hwdata->params.p1 -= 512;
0485 
0486     /* recalculate rate by fIN * (a + b/c) */
0487     lltmp  = *parent_rate;
0488     lltmp *= b;
0489     do_div(lltmp, c);
0490 
0491     rate  = (unsigned long)lltmp;
0492     rate += *parent_rate * a;
0493 
0494     dev_dbg(&hwdata->drvdata->client->dev,
0495         "%s - %s: a = %lu, b = %lu, c = %lu, parent_rate = %lu, rate = %lu\n",
0496         __func__, clk_hw_get_name(hw), a, b, c,
0497         *parent_rate, rate);
0498 
0499     return rate;
0500 }
0501 
0502 static int si5351_pll_set_rate(struct clk_hw *hw, unsigned long rate,
0503                    unsigned long parent_rate)
0504 {
0505     struct si5351_hw_data *hwdata =
0506         container_of(hw, struct si5351_hw_data, hw);
0507     u8 reg = (hwdata->num == 0) ? SI5351_PLLA_PARAMETERS :
0508         SI5351_PLLB_PARAMETERS;
0509 
0510     /* write multisynth parameters */
0511     si5351_write_parameters(hwdata->drvdata, reg, &hwdata->params);
0512 
0513     /* plla/pllb ctrl is in clk6/clk7 ctrl registers */
0514     si5351_set_bits(hwdata->drvdata, SI5351_CLK6_CTRL + hwdata->num,
0515         SI5351_CLK_INTEGER_MODE,
0516         (hwdata->params.p2 == 0) ? SI5351_CLK_INTEGER_MODE : 0);
0517 
0518     /* Do a pll soft reset on the affected pll */
0519     si5351_reg_write(hwdata->drvdata, SI5351_PLL_RESET,
0520              hwdata->num == 0 ? SI5351_PLL_RESET_A :
0521                         SI5351_PLL_RESET_B);
0522 
0523     dev_dbg(&hwdata->drvdata->client->dev,
0524         "%s - %s: p1 = %lu, p2 = %lu, p3 = %lu, parent_rate = %lu, rate = %lu\n",
0525         __func__, clk_hw_get_name(hw),
0526         hwdata->params.p1, hwdata->params.p2, hwdata->params.p3,
0527         parent_rate, rate);
0528 
0529     return 0;
0530 }
0531 
0532 static const struct clk_ops si5351_pll_ops = {
0533     .set_parent = si5351_pll_set_parent,
0534     .get_parent = si5351_pll_get_parent,
0535     .recalc_rate = si5351_pll_recalc_rate,
0536     .round_rate = si5351_pll_round_rate,
0537     .set_rate = si5351_pll_set_rate,
0538 };
0539 
0540 /*
0541  * Si5351 multisync divider
0542  *
0543  * for fOUT <= 150 MHz:
0544  *
0545  * fOUT = (fIN * (a + b/c)) / CLKOUTDIV
0546  *
0547  * with 6 + 0/1048575 <= (a + b/c) <= 1800 + 0/1048575 and
0548  * fIN = fVCO0, fVCO1
0549  *
0550  * Output Clock Multisynth Register Equations
0551  *
0552  * MSx_P1[17:0] = 128 * a + floor(128 * b/c) - 512
0553  * MSx_P2[19:0] = 128 * b - c * floor(128 * b/c) = (128*b) mod c
0554  * MSx_P3[19:0] = c
0555  *
0556  * MS[6,7] are integer (P1) divide only, P1 = divide value,
0557  * P2 and P3 are not applicable
0558  *
0559  * for 150MHz < fOUT <= 160MHz:
0560  *
0561  * MSx_P1 = 0, MSx_P2 = 0, MSx_P3 = 1, MSx_INT = 1, MSx_DIVBY4 = 11b
0562  */
0563 static int _si5351_msynth_reparent(struct si5351_driver_data *drvdata,
0564                    int num, enum si5351_multisynth_src parent)
0565 {
0566     if (parent == SI5351_MULTISYNTH_SRC_DEFAULT)
0567         return 0;
0568 
0569     if (num > 8)
0570         return -EINVAL;
0571 
0572     si5351_set_bits(drvdata, SI5351_CLK0_CTRL + num, SI5351_CLK_PLL_SELECT,
0573             (parent == SI5351_MULTISYNTH_SRC_VCO0) ? 0 :
0574             SI5351_CLK_PLL_SELECT);
0575     return 0;
0576 }
0577 
0578 static unsigned char si5351_msynth_get_parent(struct clk_hw *hw)
0579 {
0580     struct si5351_hw_data *hwdata =
0581         container_of(hw, struct si5351_hw_data, hw);
0582     u8 val;
0583 
0584     val = si5351_reg_read(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num);
0585 
0586     return (val & SI5351_CLK_PLL_SELECT) ? 1 : 0;
0587 }
0588 
0589 static int si5351_msynth_set_parent(struct clk_hw *hw, u8 index)
0590 {
0591     struct si5351_hw_data *hwdata =
0592         container_of(hw, struct si5351_hw_data, hw);
0593 
0594     return _si5351_msynth_reparent(hwdata->drvdata, hwdata->num,
0595                    (index == 0) ? SI5351_MULTISYNTH_SRC_VCO0 :
0596                    SI5351_MULTISYNTH_SRC_VCO1);
0597 }
0598 
0599 static unsigned long si5351_msynth_recalc_rate(struct clk_hw *hw,
0600                            unsigned long parent_rate)
0601 {
0602     struct si5351_hw_data *hwdata =
0603         container_of(hw, struct si5351_hw_data, hw);
0604     u8 reg = si5351_msynth_params_address(hwdata->num);
0605     unsigned long long rate;
0606     unsigned long m;
0607 
0608     if (!hwdata->params.valid)
0609         si5351_read_parameters(hwdata->drvdata, reg, &hwdata->params);
0610 
0611     /*
0612      * multisync0-5: fOUT = (128 * P3 * fIN) / (P1*P3 + P2 + 512*P3)
0613      * multisync6-7: fOUT = fIN / P1
0614      */
0615     rate = parent_rate;
0616     if (hwdata->num > 5) {
0617         m = hwdata->params.p1;
0618     } else if (hwdata->params.p3 == 0) {
0619         return parent_rate;
0620     } else if ((si5351_reg_read(hwdata->drvdata, reg + 2) &
0621             SI5351_OUTPUT_CLK_DIVBY4) == SI5351_OUTPUT_CLK_DIVBY4) {
0622         m = 4;
0623     } else {
0624         rate *= 128 * hwdata->params.p3;
0625         m = hwdata->params.p1 * hwdata->params.p3;
0626         m += hwdata->params.p2;
0627         m += 512 * hwdata->params.p3;
0628     }
0629 
0630     if (m == 0)
0631         return 0;
0632     do_div(rate, m);
0633 
0634     dev_dbg(&hwdata->drvdata->client->dev,
0635         "%s - %s: p1 = %lu, p2 = %lu, p3 = %lu, m = %lu, parent_rate = %lu, rate = %lu\n",
0636         __func__, clk_hw_get_name(hw),
0637         hwdata->params.p1, hwdata->params.p2, hwdata->params.p3,
0638         m, parent_rate, (unsigned long)rate);
0639 
0640     return (unsigned long)rate;
0641 }
0642 
0643 static long si5351_msynth_round_rate(struct clk_hw *hw, unsigned long rate,
0644                      unsigned long *parent_rate)
0645 {
0646     struct si5351_hw_data *hwdata =
0647         container_of(hw, struct si5351_hw_data, hw);
0648     unsigned long long lltmp;
0649     unsigned long a, b, c;
0650     int divby4;
0651 
0652     /* multisync6-7 can only handle freqencies < 150MHz */
0653     if (hwdata->num >= 6 && rate > SI5351_MULTISYNTH67_MAX_FREQ)
0654         rate = SI5351_MULTISYNTH67_MAX_FREQ;
0655 
0656     /* multisync frequency is 1MHz .. 160MHz */
0657     if (rate > SI5351_MULTISYNTH_MAX_FREQ)
0658         rate = SI5351_MULTISYNTH_MAX_FREQ;
0659     if (rate < SI5351_MULTISYNTH_MIN_FREQ)
0660         rate = SI5351_MULTISYNTH_MIN_FREQ;
0661 
0662     divby4 = 0;
0663     if (rate > SI5351_MULTISYNTH_DIVBY4_FREQ)
0664         divby4 = 1;
0665 
0666     /* multisync can set pll */
0667     if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
0668         /*
0669          * find largest integer divider for max
0670          * vco frequency and given target rate
0671          */
0672         if (divby4 == 0) {
0673             lltmp = SI5351_PLL_VCO_MAX;
0674             do_div(lltmp, rate);
0675             a = (unsigned long)lltmp;
0676         } else
0677             a = 4;
0678 
0679         b = 0;
0680         c = 1;
0681 
0682         *parent_rate = a * rate;
0683     } else if (hwdata->num >= 6) {
0684         /* determine the closest integer divider */
0685         a = DIV_ROUND_CLOSEST(*parent_rate, rate);
0686         if (a < SI5351_MULTISYNTH_A_MIN)
0687             a = SI5351_MULTISYNTH_A_MIN;
0688         if (a > SI5351_MULTISYNTH67_A_MAX)
0689             a = SI5351_MULTISYNTH67_A_MAX;
0690 
0691         b = 0;
0692         c = 1;
0693     } else {
0694         unsigned long rfrac, denom;
0695 
0696         /* disable divby4 */
0697         if (divby4) {
0698             rate = SI5351_MULTISYNTH_DIVBY4_FREQ;
0699             divby4 = 0;
0700         }
0701 
0702         /* determine integer part of divider equation */
0703         a = *parent_rate / rate;
0704         if (a < SI5351_MULTISYNTH_A_MIN)
0705             a = SI5351_MULTISYNTH_A_MIN;
0706         if (a > SI5351_MULTISYNTH_A_MAX)
0707             a = SI5351_MULTISYNTH_A_MAX;
0708 
0709         /* find best approximation for b/c = fVCO mod fOUT */
0710         denom = 1000 * 1000;
0711         lltmp = (*parent_rate) % rate;
0712         lltmp *= denom;
0713         do_div(lltmp, rate);
0714         rfrac = (unsigned long)lltmp;
0715 
0716         b = 0;
0717         c = 1;
0718         if (rfrac)
0719             rational_best_approximation(rfrac, denom,
0720                 SI5351_MULTISYNTH_B_MAX, SI5351_MULTISYNTH_C_MAX,
0721                 &b, &c);
0722     }
0723 
0724     /* recalculate rate by fOUT = fIN / (a + b/c) */
0725     lltmp  = *parent_rate;
0726     lltmp *= c;
0727     do_div(lltmp, a * c + b);
0728     rate  = (unsigned long)lltmp;
0729 
0730     /* calculate parameters */
0731     if (divby4) {
0732         hwdata->params.p3 = 1;
0733         hwdata->params.p2 = 0;
0734         hwdata->params.p1 = 0;
0735     } else if (hwdata->num >= 6) {
0736         hwdata->params.p3 = 0;
0737         hwdata->params.p2 = 0;
0738         hwdata->params.p1 = a;
0739     } else {
0740         hwdata->params.p3  = c;
0741         hwdata->params.p2  = (128 * b) % c;
0742         hwdata->params.p1  = 128 * a;
0743         hwdata->params.p1 += (128 * b / c);
0744         hwdata->params.p1 -= 512;
0745     }
0746 
0747     dev_dbg(&hwdata->drvdata->client->dev,
0748         "%s - %s: a = %lu, b = %lu, c = %lu, divby4 = %d, parent_rate = %lu, rate = %lu\n",
0749         __func__, clk_hw_get_name(hw), a, b, c, divby4,
0750         *parent_rate, rate);
0751 
0752     return rate;
0753 }
0754 
0755 static int si5351_msynth_set_rate(struct clk_hw *hw, unsigned long rate,
0756                   unsigned long parent_rate)
0757 {
0758     struct si5351_hw_data *hwdata =
0759         container_of(hw, struct si5351_hw_data, hw);
0760     u8 reg = si5351_msynth_params_address(hwdata->num);
0761     int divby4 = 0;
0762 
0763     /* write multisynth parameters */
0764     si5351_write_parameters(hwdata->drvdata, reg, &hwdata->params);
0765 
0766     if (rate > SI5351_MULTISYNTH_DIVBY4_FREQ)
0767         divby4 = 1;
0768 
0769     /* enable/disable integer mode and divby4 on multisynth0-5 */
0770     if (hwdata->num < 6) {
0771         si5351_set_bits(hwdata->drvdata, reg + 2,
0772                 SI5351_OUTPUT_CLK_DIVBY4,
0773                 (divby4) ? SI5351_OUTPUT_CLK_DIVBY4 : 0);
0774         si5351_set_bits(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num,
0775             SI5351_CLK_INTEGER_MODE,
0776             (hwdata->params.p2 == 0) ? SI5351_CLK_INTEGER_MODE : 0);
0777     }
0778 
0779     dev_dbg(&hwdata->drvdata->client->dev,
0780         "%s - %s: p1 = %lu, p2 = %lu, p3 = %lu, divby4 = %d, parent_rate = %lu, rate = %lu\n",
0781         __func__, clk_hw_get_name(hw),
0782         hwdata->params.p1, hwdata->params.p2, hwdata->params.p3,
0783         divby4, parent_rate, rate);
0784 
0785     return 0;
0786 }
0787 
0788 static const struct clk_ops si5351_msynth_ops = {
0789     .set_parent = si5351_msynth_set_parent,
0790     .get_parent = si5351_msynth_get_parent,
0791     .recalc_rate = si5351_msynth_recalc_rate,
0792     .round_rate = si5351_msynth_round_rate,
0793     .set_rate = si5351_msynth_set_rate,
0794 };
0795 
0796 /*
0797  * Si5351 clkout divider
0798  */
0799 static int _si5351_clkout_reparent(struct si5351_driver_data *drvdata,
0800                    int num, enum si5351_clkout_src parent)
0801 {
0802     u8 val;
0803 
0804     if (num > 8)
0805         return -EINVAL;
0806 
0807     switch (parent) {
0808     case SI5351_CLKOUT_SRC_MSYNTH_N:
0809         val = SI5351_CLK_INPUT_MULTISYNTH_N;
0810         break;
0811     case SI5351_CLKOUT_SRC_MSYNTH_0_4:
0812         /* clk0/clk4 can only connect to its own multisync */
0813         if (num == 0 || num == 4)
0814             val = SI5351_CLK_INPUT_MULTISYNTH_N;
0815         else
0816             val = SI5351_CLK_INPUT_MULTISYNTH_0_4;
0817         break;
0818     case SI5351_CLKOUT_SRC_XTAL:
0819         val = SI5351_CLK_INPUT_XTAL;
0820         break;
0821     case SI5351_CLKOUT_SRC_CLKIN:
0822         if (drvdata->variant != SI5351_VARIANT_C)
0823             return -EINVAL;
0824 
0825         val = SI5351_CLK_INPUT_CLKIN;
0826         break;
0827     default:
0828         return 0;
0829     }
0830 
0831     si5351_set_bits(drvdata, SI5351_CLK0_CTRL + num,
0832             SI5351_CLK_INPUT_MASK, val);
0833     return 0;
0834 }
0835 
0836 static int _si5351_clkout_set_drive_strength(
0837     struct si5351_driver_data *drvdata, int num,
0838     enum si5351_drive_strength drive)
0839 {
0840     u8 mask;
0841 
0842     if (num > 8)
0843         return -EINVAL;
0844 
0845     switch (drive) {
0846     case SI5351_DRIVE_2MA:
0847         mask = SI5351_CLK_DRIVE_STRENGTH_2MA;
0848         break;
0849     case SI5351_DRIVE_4MA:
0850         mask = SI5351_CLK_DRIVE_STRENGTH_4MA;
0851         break;
0852     case SI5351_DRIVE_6MA:
0853         mask = SI5351_CLK_DRIVE_STRENGTH_6MA;
0854         break;
0855     case SI5351_DRIVE_8MA:
0856         mask = SI5351_CLK_DRIVE_STRENGTH_8MA;
0857         break;
0858     default:
0859         return 0;
0860     }
0861 
0862     si5351_set_bits(drvdata, SI5351_CLK0_CTRL + num,
0863             SI5351_CLK_DRIVE_STRENGTH_MASK, mask);
0864     return 0;
0865 }
0866 
0867 static int _si5351_clkout_set_disable_state(
0868     struct si5351_driver_data *drvdata, int num,
0869     enum si5351_disable_state state)
0870 {
0871     u8 reg = (num < 4) ? SI5351_CLK3_0_DISABLE_STATE :
0872         SI5351_CLK7_4_DISABLE_STATE;
0873     u8 shift = (num < 4) ? (2 * num) : (2 * (num-4));
0874     u8 mask = SI5351_CLK_DISABLE_STATE_MASK << shift;
0875     u8 val;
0876 
0877     if (num > 8)
0878         return -EINVAL;
0879 
0880     switch (state) {
0881     case SI5351_DISABLE_LOW:
0882         val = SI5351_CLK_DISABLE_STATE_LOW;
0883         break;
0884     case SI5351_DISABLE_HIGH:
0885         val = SI5351_CLK_DISABLE_STATE_HIGH;
0886         break;
0887     case SI5351_DISABLE_FLOATING:
0888         val = SI5351_CLK_DISABLE_STATE_FLOAT;
0889         break;
0890     case SI5351_DISABLE_NEVER:
0891         val = SI5351_CLK_DISABLE_STATE_NEVER;
0892         break;
0893     default:
0894         return 0;
0895     }
0896 
0897     si5351_set_bits(drvdata, reg, mask, val << shift);
0898 
0899     return 0;
0900 }
0901 
0902 static void _si5351_clkout_reset_pll(struct si5351_driver_data *drvdata, int num)
0903 {
0904     u8 val = si5351_reg_read(drvdata, SI5351_CLK0_CTRL + num);
0905     u8 mask = val & SI5351_CLK_PLL_SELECT ? SI5351_PLL_RESET_B :
0906                                SI5351_PLL_RESET_A;
0907     unsigned int v;
0908     int err;
0909 
0910     switch (val & SI5351_CLK_INPUT_MASK) {
0911     case SI5351_CLK_INPUT_XTAL:
0912     case SI5351_CLK_INPUT_CLKIN:
0913         return;  /* pll not used, no need to reset */
0914     }
0915 
0916     si5351_reg_write(drvdata, SI5351_PLL_RESET, mask);
0917 
0918     err = regmap_read_poll_timeout(drvdata->regmap, SI5351_PLL_RESET, v,
0919                  !(v & mask), 0, 20000);
0920     if (err < 0)
0921         dev_err(&drvdata->client->dev, "Reset bit didn't clear\n");
0922 
0923     dev_dbg(&drvdata->client->dev, "%s - %s: pll = %d\n",
0924         __func__, clk_hw_get_name(&drvdata->clkout[num].hw),
0925         (val & SI5351_CLK_PLL_SELECT) ? 1 : 0);
0926 }
0927 
0928 static int si5351_clkout_prepare(struct clk_hw *hw)
0929 {
0930     struct si5351_hw_data *hwdata =
0931         container_of(hw, struct si5351_hw_data, hw);
0932     struct si5351_platform_data *pdata =
0933         hwdata->drvdata->client->dev.platform_data;
0934 
0935     si5351_set_bits(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num,
0936             SI5351_CLK_POWERDOWN, 0);
0937 
0938     /*
0939      * Do a pll soft reset on the parent pll -- needed to get a
0940      * deterministic phase relationship between the output clocks.
0941      */
0942     if (pdata->clkout[hwdata->num].pll_reset)
0943         _si5351_clkout_reset_pll(hwdata->drvdata, hwdata->num);
0944 
0945     si5351_set_bits(hwdata->drvdata, SI5351_OUTPUT_ENABLE_CTRL,
0946             (1 << hwdata->num), 0);
0947     return 0;
0948 }
0949 
0950 static void si5351_clkout_unprepare(struct clk_hw *hw)
0951 {
0952     struct si5351_hw_data *hwdata =
0953         container_of(hw, struct si5351_hw_data, hw);
0954 
0955     si5351_set_bits(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num,
0956             SI5351_CLK_POWERDOWN, SI5351_CLK_POWERDOWN);
0957     si5351_set_bits(hwdata->drvdata, SI5351_OUTPUT_ENABLE_CTRL,
0958             (1 << hwdata->num), (1 << hwdata->num));
0959 }
0960 
0961 static u8 si5351_clkout_get_parent(struct clk_hw *hw)
0962 {
0963     struct si5351_hw_data *hwdata =
0964         container_of(hw, struct si5351_hw_data, hw);
0965     int index = 0;
0966     unsigned char val;
0967 
0968     val = si5351_reg_read(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num);
0969     switch (val & SI5351_CLK_INPUT_MASK) {
0970     case SI5351_CLK_INPUT_MULTISYNTH_N:
0971         index = 0;
0972         break;
0973     case SI5351_CLK_INPUT_MULTISYNTH_0_4:
0974         index = 1;
0975         break;
0976     case SI5351_CLK_INPUT_XTAL:
0977         index = 2;
0978         break;
0979     case SI5351_CLK_INPUT_CLKIN:
0980         index = 3;
0981         break;
0982     }
0983 
0984     return index;
0985 }
0986 
0987 static int si5351_clkout_set_parent(struct clk_hw *hw, u8 index)
0988 {
0989     struct si5351_hw_data *hwdata =
0990         container_of(hw, struct si5351_hw_data, hw);
0991     enum si5351_clkout_src parent = SI5351_CLKOUT_SRC_DEFAULT;
0992 
0993     switch (index) {
0994     case 0:
0995         parent = SI5351_CLKOUT_SRC_MSYNTH_N;
0996         break;
0997     case 1:
0998         parent = SI5351_CLKOUT_SRC_MSYNTH_0_4;
0999         break;
1000     case 2:
1001         parent = SI5351_CLKOUT_SRC_XTAL;
1002         break;
1003     case 3:
1004         parent = SI5351_CLKOUT_SRC_CLKIN;
1005         break;
1006     }
1007 
1008     return _si5351_clkout_reparent(hwdata->drvdata, hwdata->num, parent);
1009 }
1010 
1011 static unsigned long si5351_clkout_recalc_rate(struct clk_hw *hw,
1012                            unsigned long parent_rate)
1013 {
1014     struct si5351_hw_data *hwdata =
1015         container_of(hw, struct si5351_hw_data, hw);
1016     unsigned char reg;
1017     unsigned char rdiv;
1018 
1019     if (hwdata->num <= 5)
1020         reg = si5351_msynth_params_address(hwdata->num) + 2;
1021     else
1022         reg = SI5351_CLK6_7_OUTPUT_DIVIDER;
1023 
1024     rdiv = si5351_reg_read(hwdata->drvdata, reg);
1025     if (hwdata->num == 6) {
1026         rdiv &= SI5351_OUTPUT_CLK6_DIV_MASK;
1027     } else {
1028         rdiv &= SI5351_OUTPUT_CLK_DIV_MASK;
1029         rdiv >>= SI5351_OUTPUT_CLK_DIV_SHIFT;
1030     }
1031 
1032     return parent_rate >> rdiv;
1033 }
1034 
1035 static long si5351_clkout_round_rate(struct clk_hw *hw, unsigned long rate,
1036                      unsigned long *parent_rate)
1037 {
1038     struct si5351_hw_data *hwdata =
1039         container_of(hw, struct si5351_hw_data, hw);
1040     unsigned char rdiv;
1041 
1042     /* clkout6/7 can only handle output freqencies < 150MHz */
1043     if (hwdata->num >= 6 && rate > SI5351_CLKOUT67_MAX_FREQ)
1044         rate = SI5351_CLKOUT67_MAX_FREQ;
1045 
1046     /* clkout freqency is 8kHz - 160MHz */
1047     if (rate > SI5351_CLKOUT_MAX_FREQ)
1048         rate = SI5351_CLKOUT_MAX_FREQ;
1049     if (rate < SI5351_CLKOUT_MIN_FREQ)
1050         rate = SI5351_CLKOUT_MIN_FREQ;
1051 
1052     /* request frequency if multisync master */
1053     if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
1054         /* use r divider for frequencies below 1MHz */
1055         rdiv = SI5351_OUTPUT_CLK_DIV_1;
1056         while (rate < SI5351_MULTISYNTH_MIN_FREQ &&
1057                rdiv < SI5351_OUTPUT_CLK_DIV_128) {
1058             rdiv += 1;
1059             rate *= 2;
1060         }
1061         *parent_rate = rate;
1062     } else {
1063         unsigned long new_rate, new_err, err;
1064 
1065         /* round to closed rdiv */
1066         rdiv = SI5351_OUTPUT_CLK_DIV_1;
1067         new_rate = *parent_rate;
1068         err = abs(new_rate - rate);
1069         do {
1070             new_rate >>= 1;
1071             new_err = abs(new_rate - rate);
1072             if (new_err > err || rdiv == SI5351_OUTPUT_CLK_DIV_128)
1073                 break;
1074             rdiv++;
1075             err = new_err;
1076         } while (1);
1077     }
1078     rate = *parent_rate >> rdiv;
1079 
1080     dev_dbg(&hwdata->drvdata->client->dev,
1081         "%s - %s: rdiv = %u, parent_rate = %lu, rate = %lu\n",
1082         __func__, clk_hw_get_name(hw), (1 << rdiv),
1083         *parent_rate, rate);
1084 
1085     return rate;
1086 }
1087 
1088 static int si5351_clkout_set_rate(struct clk_hw *hw, unsigned long rate,
1089                   unsigned long parent_rate)
1090 {
1091     struct si5351_hw_data *hwdata =
1092         container_of(hw, struct si5351_hw_data, hw);
1093     unsigned long new_rate, new_err, err;
1094     unsigned char rdiv;
1095 
1096     /* round to closed rdiv */
1097     rdiv = SI5351_OUTPUT_CLK_DIV_1;
1098     new_rate = parent_rate;
1099     err = abs(new_rate - rate);
1100     do {
1101         new_rate >>= 1;
1102         new_err = abs(new_rate - rate);
1103         if (new_err > err || rdiv == SI5351_OUTPUT_CLK_DIV_128)
1104             break;
1105         rdiv++;
1106         err = new_err;
1107     } while (1);
1108 
1109     /* write output divider */
1110     switch (hwdata->num) {
1111     case 6:
1112         si5351_set_bits(hwdata->drvdata, SI5351_CLK6_7_OUTPUT_DIVIDER,
1113                 SI5351_OUTPUT_CLK6_DIV_MASK, rdiv);
1114         break;
1115     case 7:
1116         si5351_set_bits(hwdata->drvdata, SI5351_CLK6_7_OUTPUT_DIVIDER,
1117                 SI5351_OUTPUT_CLK_DIV_MASK,
1118                 rdiv << SI5351_OUTPUT_CLK_DIV_SHIFT);
1119         break;
1120     default:
1121         si5351_set_bits(hwdata->drvdata,
1122                 si5351_msynth_params_address(hwdata->num) + 2,
1123                 SI5351_OUTPUT_CLK_DIV_MASK,
1124                 rdiv << SI5351_OUTPUT_CLK_DIV_SHIFT);
1125     }
1126 
1127     /* powerup clkout */
1128     si5351_set_bits(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num,
1129             SI5351_CLK_POWERDOWN, 0);
1130 
1131     dev_dbg(&hwdata->drvdata->client->dev,
1132         "%s - %s: rdiv = %u, parent_rate = %lu, rate = %lu\n",
1133         __func__, clk_hw_get_name(hw), (1 << rdiv),
1134         parent_rate, rate);
1135 
1136     return 0;
1137 }
1138 
1139 static const struct clk_ops si5351_clkout_ops = {
1140     .prepare = si5351_clkout_prepare,
1141     .unprepare = si5351_clkout_unprepare,
1142     .set_parent = si5351_clkout_set_parent,
1143     .get_parent = si5351_clkout_get_parent,
1144     .recalc_rate = si5351_clkout_recalc_rate,
1145     .round_rate = si5351_clkout_round_rate,
1146     .set_rate = si5351_clkout_set_rate,
1147 };
1148 
1149 /*
1150  * Si5351 i2c probe and DT
1151  */
1152 #ifdef CONFIG_OF
1153 static const struct of_device_id si5351_dt_ids[] = {
1154     { .compatible = "silabs,si5351a", .data = (void *)SI5351_VARIANT_A, },
1155     { .compatible = "silabs,si5351a-msop",
1156                      .data = (void *)SI5351_VARIANT_A3, },
1157     { .compatible = "silabs,si5351b", .data = (void *)SI5351_VARIANT_B, },
1158     { .compatible = "silabs,si5351c", .data = (void *)SI5351_VARIANT_C, },
1159     { }
1160 };
1161 MODULE_DEVICE_TABLE(of, si5351_dt_ids);
1162 
1163 static int si5351_dt_parse(struct i2c_client *client,
1164                enum si5351_variant variant)
1165 {
1166     struct device_node *child, *np = client->dev.of_node;
1167     struct si5351_platform_data *pdata;
1168     struct property *prop;
1169     const __be32 *p;
1170     int num = 0;
1171     u32 val;
1172 
1173     if (np == NULL)
1174         return 0;
1175 
1176     pdata = devm_kzalloc(&client->dev, sizeof(*pdata), GFP_KERNEL);
1177     if (!pdata)
1178         return -ENOMEM;
1179 
1180     /*
1181      * property silabs,pll-source : <num src>, [<..>]
1182      * allow to selectively set pll source
1183      */
1184     of_property_for_each_u32(np, "silabs,pll-source", prop, p, num) {
1185         if (num >= 2) {
1186             dev_err(&client->dev,
1187                 "invalid pll %d on pll-source prop\n", num);
1188             return -EINVAL;
1189         }
1190 
1191         p = of_prop_next_u32(prop, p, &val);
1192         if (!p) {
1193             dev_err(&client->dev,
1194                 "missing pll-source for pll %d\n", num);
1195             return -EINVAL;
1196         }
1197 
1198         switch (val) {
1199         case 0:
1200             pdata->pll_src[num] = SI5351_PLL_SRC_XTAL;
1201             break;
1202         case 1:
1203             if (variant != SI5351_VARIANT_C) {
1204                 dev_err(&client->dev,
1205                     "invalid parent %d for pll %d\n",
1206                     val, num);
1207                 return -EINVAL;
1208             }
1209             pdata->pll_src[num] = SI5351_PLL_SRC_CLKIN;
1210             break;
1211         default:
1212             dev_err(&client->dev,
1213                  "invalid parent %d for pll %d\n", val, num);
1214             return -EINVAL;
1215         }
1216     }
1217 
1218     /* per clkout properties */
1219     for_each_child_of_node(np, child) {
1220         if (of_property_read_u32(child, "reg", &num)) {
1221             dev_err(&client->dev, "missing reg property of %pOFn\n",
1222                 child);
1223             goto put_child;
1224         }
1225 
1226         if (num >= 8 ||
1227             (variant == SI5351_VARIANT_A3 && num >= 3)) {
1228             dev_err(&client->dev, "invalid clkout %d\n", num);
1229             goto put_child;
1230         }
1231 
1232         if (!of_property_read_u32(child, "silabs,multisynth-source",
1233                       &val)) {
1234             switch (val) {
1235             case 0:
1236                 pdata->clkout[num].multisynth_src =
1237                     SI5351_MULTISYNTH_SRC_VCO0;
1238                 break;
1239             case 1:
1240                 pdata->clkout[num].multisynth_src =
1241                     SI5351_MULTISYNTH_SRC_VCO1;
1242                 break;
1243             default:
1244                 dev_err(&client->dev,
1245                     "invalid parent %d for multisynth %d\n",
1246                     val, num);
1247                 goto put_child;
1248             }
1249         }
1250 
1251         if (!of_property_read_u32(child, "silabs,clock-source", &val)) {
1252             switch (val) {
1253             case 0:
1254                 pdata->clkout[num].clkout_src =
1255                     SI5351_CLKOUT_SRC_MSYNTH_N;
1256                 break;
1257             case 1:
1258                 pdata->clkout[num].clkout_src =
1259                     SI5351_CLKOUT_SRC_MSYNTH_0_4;
1260                 break;
1261             case 2:
1262                 pdata->clkout[num].clkout_src =
1263                     SI5351_CLKOUT_SRC_XTAL;
1264                 break;
1265             case 3:
1266                 if (variant != SI5351_VARIANT_C) {
1267                     dev_err(&client->dev,
1268                         "invalid parent %d for clkout %d\n",
1269                         val, num);
1270                     goto put_child;
1271                 }
1272                 pdata->clkout[num].clkout_src =
1273                     SI5351_CLKOUT_SRC_CLKIN;
1274                 break;
1275             default:
1276                 dev_err(&client->dev,
1277                     "invalid parent %d for clkout %d\n",
1278                     val, num);
1279                 goto put_child;
1280             }
1281         }
1282 
1283         if (!of_property_read_u32(child, "silabs,drive-strength",
1284                       &val)) {
1285             switch (val) {
1286             case SI5351_DRIVE_2MA:
1287             case SI5351_DRIVE_4MA:
1288             case SI5351_DRIVE_6MA:
1289             case SI5351_DRIVE_8MA:
1290                 pdata->clkout[num].drive = val;
1291                 break;
1292             default:
1293                 dev_err(&client->dev,
1294                     "invalid drive strength %d for clkout %d\n",
1295                     val, num);
1296                 goto put_child;
1297             }
1298         }
1299 
1300         if (!of_property_read_u32(child, "silabs,disable-state",
1301                       &val)) {
1302             switch (val) {
1303             case 0:
1304                 pdata->clkout[num].disable_state =
1305                     SI5351_DISABLE_LOW;
1306                 break;
1307             case 1:
1308                 pdata->clkout[num].disable_state =
1309                     SI5351_DISABLE_HIGH;
1310                 break;
1311             case 2:
1312                 pdata->clkout[num].disable_state =
1313                     SI5351_DISABLE_FLOATING;
1314                 break;
1315             case 3:
1316                 pdata->clkout[num].disable_state =
1317                     SI5351_DISABLE_NEVER;
1318                 break;
1319             default:
1320                 dev_err(&client->dev,
1321                     "invalid disable state %d for clkout %d\n",
1322                     val, num);
1323                 goto put_child;
1324             }
1325         }
1326 
1327         if (!of_property_read_u32(child, "clock-frequency", &val))
1328             pdata->clkout[num].rate = val;
1329 
1330         pdata->clkout[num].pll_master =
1331             of_property_read_bool(child, "silabs,pll-master");
1332 
1333         pdata->clkout[num].pll_reset =
1334             of_property_read_bool(child, "silabs,pll-reset");
1335     }
1336     client->dev.platform_data = pdata;
1337 
1338     return 0;
1339 put_child:
1340     of_node_put(child);
1341     return -EINVAL;
1342 }
1343 
1344 static struct clk_hw *
1345 si53351_of_clk_get(struct of_phandle_args *clkspec, void *data)
1346 {
1347     struct si5351_driver_data *drvdata = data;
1348     unsigned int idx = clkspec->args[0];
1349 
1350     if (idx >= drvdata->num_clkout) {
1351         pr_err("%s: invalid index %u\n", __func__, idx);
1352         return ERR_PTR(-EINVAL);
1353     }
1354 
1355     return &drvdata->clkout[idx].hw;
1356 }
1357 #else
1358 static int si5351_dt_parse(struct i2c_client *client, enum si5351_variant variant)
1359 {
1360     return 0;
1361 }
1362 
1363 static struct clk_hw *
1364 si53351_of_clk_get(struct of_phandle_args *clkspec, void *data)
1365 {
1366     return NULL;
1367 }
1368 #endif /* CONFIG_OF */
1369 
1370 static const struct i2c_device_id si5351_i2c_ids[] = {
1371     { "si5351a", SI5351_VARIANT_A },
1372     { "si5351a-msop", SI5351_VARIANT_A3 },
1373     { "si5351b", SI5351_VARIANT_B },
1374     { "si5351c", SI5351_VARIANT_C },
1375     { }
1376 };
1377 MODULE_DEVICE_TABLE(i2c, si5351_i2c_ids);
1378 
1379 static int si5351_i2c_probe(struct i2c_client *client)
1380 {
1381     const struct i2c_device_id *id = i2c_match_id(si5351_i2c_ids, client);
1382     enum si5351_variant variant = (enum si5351_variant)id->driver_data;
1383     struct si5351_platform_data *pdata;
1384     struct si5351_driver_data *drvdata;
1385     struct clk_init_data init;
1386     const char *parent_names[4];
1387     u8 num_parents, num_clocks;
1388     int ret, n;
1389 
1390     ret = si5351_dt_parse(client, variant);
1391     if (ret)
1392         return ret;
1393 
1394     pdata = client->dev.platform_data;
1395     if (!pdata)
1396         return -EINVAL;
1397 
1398     drvdata = devm_kzalloc(&client->dev, sizeof(*drvdata), GFP_KERNEL);
1399     if (!drvdata)
1400         return -ENOMEM;
1401 
1402     i2c_set_clientdata(client, drvdata);
1403     drvdata->client = client;
1404     drvdata->variant = variant;
1405     drvdata->pxtal = devm_clk_get(&client->dev, "xtal");
1406     drvdata->pclkin = devm_clk_get(&client->dev, "clkin");
1407 
1408     if (PTR_ERR(drvdata->pxtal) == -EPROBE_DEFER ||
1409         PTR_ERR(drvdata->pclkin) == -EPROBE_DEFER)
1410         return -EPROBE_DEFER;
1411 
1412     /*
1413      * Check for valid parent clock: VARIANT_A and VARIANT_B need XTAL,
1414      *   VARIANT_C can have CLKIN instead.
1415      */
1416     if (IS_ERR(drvdata->pxtal) &&
1417         (drvdata->variant != SI5351_VARIANT_C || IS_ERR(drvdata->pclkin))) {
1418         dev_err(&client->dev, "missing parent clock\n");
1419         return -EINVAL;
1420     }
1421 
1422     drvdata->regmap = devm_regmap_init_i2c(client, &si5351_regmap_config);
1423     if (IS_ERR(drvdata->regmap)) {
1424         dev_err(&client->dev, "failed to allocate register map\n");
1425         return PTR_ERR(drvdata->regmap);
1426     }
1427 
1428     /* Disable interrupts */
1429     si5351_reg_write(drvdata, SI5351_INTERRUPT_MASK, 0xf0);
1430     /* Ensure pll select is on XTAL for Si5351A/B */
1431     if (drvdata->variant != SI5351_VARIANT_C)
1432         si5351_set_bits(drvdata, SI5351_PLL_INPUT_SOURCE,
1433                 SI5351_PLLA_SOURCE | SI5351_PLLB_SOURCE, 0);
1434 
1435     /* setup clock configuration */
1436     for (n = 0; n < 2; n++) {
1437         ret = _si5351_pll_reparent(drvdata, n, pdata->pll_src[n]);
1438         if (ret) {
1439             dev_err(&client->dev,
1440                 "failed to reparent pll %d to %d\n",
1441                 n, pdata->pll_src[n]);
1442             return ret;
1443         }
1444     }
1445 
1446     for (n = 0; n < 8; n++) {
1447         ret = _si5351_msynth_reparent(drvdata, n,
1448                           pdata->clkout[n].multisynth_src);
1449         if (ret) {
1450             dev_err(&client->dev,
1451                 "failed to reparent multisynth %d to %d\n",
1452                 n, pdata->clkout[n].multisynth_src);
1453             return ret;
1454         }
1455 
1456         ret = _si5351_clkout_reparent(drvdata, n,
1457                           pdata->clkout[n].clkout_src);
1458         if (ret) {
1459             dev_err(&client->dev,
1460                 "failed to reparent clkout %d to %d\n",
1461                 n, pdata->clkout[n].clkout_src);
1462             return ret;
1463         }
1464 
1465         ret = _si5351_clkout_set_drive_strength(drvdata, n,
1466                             pdata->clkout[n].drive);
1467         if (ret) {
1468             dev_err(&client->dev,
1469                 "failed set drive strength of clkout%d to %d\n",
1470                 n, pdata->clkout[n].drive);
1471             return ret;
1472         }
1473 
1474         ret = _si5351_clkout_set_disable_state(drvdata, n,
1475                         pdata->clkout[n].disable_state);
1476         if (ret) {
1477             dev_err(&client->dev,
1478                 "failed set disable state of clkout%d to %d\n",
1479                 n, pdata->clkout[n].disable_state);
1480             return ret;
1481         }
1482     }
1483 
1484     /* register xtal input clock gate */
1485     memset(&init, 0, sizeof(init));
1486     init.name = si5351_input_names[0];
1487     init.ops = &si5351_xtal_ops;
1488     init.flags = 0;
1489     if (!IS_ERR(drvdata->pxtal)) {
1490         drvdata->pxtal_name = __clk_get_name(drvdata->pxtal);
1491         init.parent_names = &drvdata->pxtal_name;
1492         init.num_parents = 1;
1493     }
1494     drvdata->xtal.init = &init;
1495     ret = devm_clk_hw_register(&client->dev, &drvdata->xtal);
1496     if (ret) {
1497         dev_err(&client->dev, "unable to register %s\n", init.name);
1498         return ret;
1499     }
1500 
1501     /* register clkin input clock gate */
1502     if (drvdata->variant == SI5351_VARIANT_C) {
1503         memset(&init, 0, sizeof(init));
1504         init.name = si5351_input_names[1];
1505         init.ops = &si5351_clkin_ops;
1506         if (!IS_ERR(drvdata->pclkin)) {
1507             drvdata->pclkin_name = __clk_get_name(drvdata->pclkin);
1508             init.parent_names = &drvdata->pclkin_name;
1509             init.num_parents = 1;
1510         }
1511         drvdata->clkin.init = &init;
1512         ret = devm_clk_hw_register(&client->dev, &drvdata->clkin);
1513         if (ret) {
1514             dev_err(&client->dev, "unable to register %s\n",
1515                 init.name);
1516             return ret;
1517         }
1518     }
1519 
1520     /* Si5351C allows to mux either xtal or clkin to PLL input */
1521     num_parents = (drvdata->variant == SI5351_VARIANT_C) ? 2 : 1;
1522     parent_names[0] = si5351_input_names[0];
1523     parent_names[1] = si5351_input_names[1];
1524 
1525     /* register PLLA */
1526     drvdata->pll[0].num = 0;
1527     drvdata->pll[0].drvdata = drvdata;
1528     drvdata->pll[0].hw.init = &init;
1529     memset(&init, 0, sizeof(init));
1530     init.name = si5351_pll_names[0];
1531     init.ops = &si5351_pll_ops;
1532     init.flags = 0;
1533     init.parent_names = parent_names;
1534     init.num_parents = num_parents;
1535     ret = devm_clk_hw_register(&client->dev, &drvdata->pll[0].hw);
1536     if (ret) {
1537         dev_err(&client->dev, "unable to register %s\n", init.name);
1538         return ret;
1539     }
1540 
1541     /* register PLLB or VXCO (Si5351B) */
1542     drvdata->pll[1].num = 1;
1543     drvdata->pll[1].drvdata = drvdata;
1544     drvdata->pll[1].hw.init = &init;
1545     memset(&init, 0, sizeof(init));
1546     if (drvdata->variant == SI5351_VARIANT_B) {
1547         init.name = si5351_pll_names[2];
1548         init.ops = &si5351_vxco_ops;
1549         init.flags = 0;
1550         init.parent_names = NULL;
1551         init.num_parents = 0;
1552     } else {
1553         init.name = si5351_pll_names[1];
1554         init.ops = &si5351_pll_ops;
1555         init.flags = 0;
1556         init.parent_names = parent_names;
1557         init.num_parents = num_parents;
1558     }
1559     ret = devm_clk_hw_register(&client->dev, &drvdata->pll[1].hw);
1560     if (ret) {
1561         dev_err(&client->dev, "unable to register %s\n", init.name);
1562         return ret;
1563     }
1564 
1565     /* register clk multisync and clk out divider */
1566     num_clocks = (drvdata->variant == SI5351_VARIANT_A3) ? 3 : 8;
1567     parent_names[0] = si5351_pll_names[0];
1568     if (drvdata->variant == SI5351_VARIANT_B)
1569         parent_names[1] = si5351_pll_names[2];
1570     else
1571         parent_names[1] = si5351_pll_names[1];
1572 
1573     drvdata->msynth = devm_kcalloc(&client->dev, num_clocks,
1574                        sizeof(*drvdata->msynth), GFP_KERNEL);
1575     drvdata->clkout = devm_kcalloc(&client->dev, num_clocks,
1576                        sizeof(*drvdata->clkout), GFP_KERNEL);
1577     drvdata->num_clkout = num_clocks;
1578 
1579     if (WARN_ON(!drvdata->msynth || !drvdata->clkout)) {
1580         ret = -ENOMEM;
1581         return ret;
1582     }
1583 
1584     for (n = 0; n < num_clocks; n++) {
1585         drvdata->msynth[n].num = n;
1586         drvdata->msynth[n].drvdata = drvdata;
1587         drvdata->msynth[n].hw.init = &init;
1588         memset(&init, 0, sizeof(init));
1589         init.name = si5351_msynth_names[n];
1590         init.ops = &si5351_msynth_ops;
1591         init.flags = 0;
1592         if (pdata->clkout[n].pll_master)
1593             init.flags |= CLK_SET_RATE_PARENT;
1594         init.parent_names = parent_names;
1595         init.num_parents = 2;
1596         ret = devm_clk_hw_register(&client->dev,
1597                        &drvdata->msynth[n].hw);
1598         if (ret) {
1599             dev_err(&client->dev, "unable to register %s\n",
1600                 init.name);
1601             return ret;
1602         }
1603     }
1604 
1605     num_parents = (drvdata->variant == SI5351_VARIANT_C) ? 4 : 3;
1606     parent_names[2] = si5351_input_names[0];
1607     parent_names[3] = si5351_input_names[1];
1608     for (n = 0; n < num_clocks; n++) {
1609         parent_names[0] = si5351_msynth_names[n];
1610         parent_names[1] = (n < 4) ? si5351_msynth_names[0] :
1611             si5351_msynth_names[4];
1612 
1613         drvdata->clkout[n].num = n;
1614         drvdata->clkout[n].drvdata = drvdata;
1615         drvdata->clkout[n].hw.init = &init;
1616         memset(&init, 0, sizeof(init));
1617         init.name = si5351_clkout_names[n];
1618         init.ops = &si5351_clkout_ops;
1619         init.flags = 0;
1620         if (pdata->clkout[n].clkout_src == SI5351_CLKOUT_SRC_MSYNTH_N)
1621             init.flags |= CLK_SET_RATE_PARENT;
1622         init.parent_names = parent_names;
1623         init.num_parents = num_parents;
1624         ret = devm_clk_hw_register(&client->dev,
1625                        &drvdata->clkout[n].hw);
1626         if (ret) {
1627             dev_err(&client->dev, "unable to register %s\n",
1628                 init.name);
1629             return ret;
1630         }
1631 
1632         /* set initial clkout rate */
1633         if (pdata->clkout[n].rate != 0) {
1634             int ret;
1635             ret = clk_set_rate(drvdata->clkout[n].hw.clk,
1636                        pdata->clkout[n].rate);
1637             if (ret != 0) {
1638                 dev_err(&client->dev, "Cannot set rate : %d\n",
1639                     ret);
1640             }
1641         }
1642     }
1643 
1644     ret = of_clk_add_hw_provider(client->dev.of_node, si53351_of_clk_get,
1645                      drvdata);
1646     if (ret) {
1647         dev_err(&client->dev, "unable to add clk provider\n");
1648         return ret;
1649     }
1650 
1651     return 0;
1652 }
1653 
1654 static int si5351_i2c_remove(struct i2c_client *client)
1655 {
1656     of_clk_del_provider(client->dev.of_node);
1657 
1658     return 0;
1659 }
1660 
1661 static struct i2c_driver si5351_driver = {
1662     .driver = {
1663         .name = "si5351",
1664         .of_match_table = of_match_ptr(si5351_dt_ids),
1665     },
1666     .probe_new = si5351_i2c_probe,
1667     .remove = si5351_i2c_remove,
1668     .id_table = si5351_i2c_ids,
1669 };
1670 module_i2c_driver(si5351_driver);
1671 
1672 MODULE_AUTHOR("Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com");
1673 MODULE_DESCRIPTION("Silicon Labs Si5351A/B/C clock generator driver");
1674 MODULE_LICENSE("GPL");
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