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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Driver for Silicon Labs Si5340, Si5341, Si5342, Si5344 and Si5345
0004  * Copyright (C) 2019 Topic Embedded Products
0005  * Author: Mike Looijmans <mike.looijmans@topic.nl>
0006  *
0007  * The Si5341 has 10 outputs and 5 synthesizers.
0008  * The Si5340 is a smaller version of the Si5341 with only 4 outputs.
0009  * The Si5345 is similar to the Si5341, with the addition of fractional input
0010  * dividers and automatic input selection.
0011  * The Si5342 and Si5344 are smaller versions of the Si5345.
0012  */
0013 
0014 #include <linux/clk.h>
0015 #include <linux/clk-provider.h>
0016 #include <linux/delay.h>
0017 #include <linux/gcd.h>
0018 #include <linux/math64.h>
0019 #include <linux/i2c.h>
0020 #include <linux/module.h>
0021 #include <linux/regmap.h>
0022 #include <linux/regulator/consumer.h>
0023 #include <linux/slab.h>
0024 #include <asm/unaligned.h>
0025 
0026 #define SI5341_NUM_INPUTS 4
0027 
0028 #define SI5340_MAX_NUM_OUTPUTS 4
0029 #define SI5341_MAX_NUM_OUTPUTS 10
0030 #define SI5342_MAX_NUM_OUTPUTS 2
0031 #define SI5344_MAX_NUM_OUTPUTS 4
0032 #define SI5345_MAX_NUM_OUTPUTS 10
0033 
0034 #define SI5340_NUM_SYNTH 4
0035 #define SI5341_NUM_SYNTH 5
0036 #define SI5342_NUM_SYNTH 2
0037 #define SI5344_NUM_SYNTH 4
0038 #define SI5345_NUM_SYNTH 5
0039 
0040 /* Range of the synthesizer fractional divider */
0041 #define SI5341_SYNTH_N_MIN  10
0042 #define SI5341_SYNTH_N_MAX  4095
0043 
0044 /* The chip can get its input clock from 3 input pins or an XTAL */
0045 
0046 /* There is one PLL running at 13500–14256 MHz */
0047 #define SI5341_PLL_VCO_MIN 13500000000ull
0048 #define SI5341_PLL_VCO_MAX 14256000000ull
0049 
0050 /* The 5 frequency synthesizers obtain their input from the PLL */
0051 struct clk_si5341_synth {
0052     struct clk_hw hw;
0053     struct clk_si5341 *data;
0054     u8 index;
0055 };
0056 #define to_clk_si5341_synth(_hw) \
0057     container_of(_hw, struct clk_si5341_synth, hw)
0058 
0059 /* The output stages can be connected to any synth (full mux) */
0060 struct clk_si5341_output {
0061     struct clk_hw hw;
0062     struct clk_si5341 *data;
0063     struct regulator *vddo_reg;
0064     u8 index;
0065 };
0066 #define to_clk_si5341_output(_hw) \
0067     container_of(_hw, struct clk_si5341_output, hw)
0068 
0069 struct clk_si5341 {
0070     struct clk_hw hw;
0071     struct regmap *regmap;
0072     struct i2c_client *i2c_client;
0073     struct clk_si5341_synth synth[SI5341_NUM_SYNTH];
0074     struct clk_si5341_output clk[SI5341_MAX_NUM_OUTPUTS];
0075     struct clk *input_clk[SI5341_NUM_INPUTS];
0076     const char *input_clk_name[SI5341_NUM_INPUTS];
0077     const u16 *reg_output_offset;
0078     const u16 *reg_rdiv_offset;
0079     u64 freq_vco; /* 13500–14256 MHz */
0080     u8 num_outputs;
0081     u8 num_synth;
0082     u16 chip_id;
0083     bool xaxb_ext_clk;
0084     bool iovdd_33;
0085 };
0086 #define to_clk_si5341(_hw)  container_of(_hw, struct clk_si5341, hw)
0087 
0088 struct clk_si5341_output_config {
0089     u8 out_format_drv_bits;
0090     u8 out_cm_ampl_bits;
0091     u8 vdd_sel_bits;
0092     bool synth_master;
0093     bool always_on;
0094 };
0095 
0096 #define SI5341_PAGE     0x0001
0097 #define SI5341_PN_BASE      0x0002
0098 #define SI5341_DEVICE_REV   0x0005
0099 #define SI5341_STATUS       0x000C
0100 #define SI5341_LOS      0x000D
0101 #define SI5341_STATUS_STICKY    0x0011
0102 #define SI5341_LOS_STICKY   0x0012
0103 #define SI5341_SOFT_RST     0x001C
0104 #define SI5341_IN_SEL       0x0021
0105 #define SI5341_DEVICE_READY 0x00FE
0106 #define SI5341_XAXB_CFG     0x090E
0107 #define SI5341_IO_VDD_SEL   0x0943
0108 #define SI5341_IN_EN        0x0949
0109 #define SI5341_INX_TO_PFD_EN    0x094A
0110 
0111 /* Status bits */
0112 #define SI5341_STATUS_SYSINCAL  BIT(0)
0113 #define SI5341_STATUS_LOSXAXB   BIT(1)
0114 #define SI5341_STATUS_LOSREF    BIT(2)
0115 #define SI5341_STATUS_LOL   BIT(3)
0116 
0117 /* Input selection */
0118 #define SI5341_IN_SEL_MASK  0x06
0119 #define SI5341_IN_SEL_SHIFT 1
0120 #define SI5341_IN_SEL_REGCTRL   0x01
0121 #define SI5341_INX_TO_PFD_SHIFT 4
0122 
0123 /* XTAL config bits */
0124 #define SI5341_XAXB_CFG_EXTCLK_EN   BIT(0)
0125 #define SI5341_XAXB_CFG_PDNB        BIT(1)
0126 
0127 /* Input dividers (48-bit) */
0128 #define SI5341_IN_PDIV(x)   (0x0208 + ((x) * 10))
0129 #define SI5341_IN_PSET(x)   (0x020E + ((x) * 10))
0130 #define SI5341_PX_UPD       0x0230
0131 
0132 /* PLL configuration */
0133 #define SI5341_PLL_M_NUM    0x0235
0134 #define SI5341_PLL_M_DEN    0x023B
0135 
0136 /* Output configuration */
0137 #define SI5341_OUT_CONFIG(output)   \
0138             ((output)->data->reg_output_offset[(output)->index])
0139 #define SI5341_OUT_FORMAT(output)   (SI5341_OUT_CONFIG(output) + 1)
0140 #define SI5341_OUT_CM(output)       (SI5341_OUT_CONFIG(output) + 2)
0141 #define SI5341_OUT_MUX_SEL(output)  (SI5341_OUT_CONFIG(output) + 3)
0142 #define SI5341_OUT_R_REG(output)    \
0143             ((output)->data->reg_rdiv_offset[(output)->index])
0144 
0145 #define SI5341_OUT_MUX_VDD_SEL_MASK 0x38
0146 
0147 /* Synthesize N divider */
0148 #define SI5341_SYNTH_N_NUM(x)   (0x0302 + ((x) * 11))
0149 #define SI5341_SYNTH_N_DEN(x)   (0x0308 + ((x) * 11))
0150 #define SI5341_SYNTH_N_UPD(x)   (0x030C + ((x) * 11))
0151 
0152 /* Synthesizer output enable, phase bypass, power mode */
0153 #define SI5341_SYNTH_N_CLK_TO_OUTX_EN   0x0A03
0154 #define SI5341_SYNTH_N_PIBYP        0x0A04
0155 #define SI5341_SYNTH_N_PDNB     0x0A05
0156 #define SI5341_SYNTH_N_CLK_DIS      0x0B4A
0157 
0158 #define SI5341_REGISTER_MAX 0xBFF
0159 
0160 /* SI5341_OUT_CONFIG bits */
0161 #define SI5341_OUT_CFG_PDN      BIT(0)
0162 #define SI5341_OUT_CFG_OE       BIT(1)
0163 #define SI5341_OUT_CFG_RDIV_FORCE2  BIT(2)
0164 
0165 /* Static configuration (to be moved to firmware) */
0166 struct si5341_reg_default {
0167     u16 address;
0168     u8 value;
0169 };
0170 
0171 static const char * const si5341_input_clock_names[] = {
0172     "in0", "in1", "in2", "xtal"
0173 };
0174 
0175 /* Output configuration registers 0..9 are not quite logically organized */
0176 /* Also for si5345 */
0177 static const u16 si5341_reg_output_offset[] = {
0178     0x0108,
0179     0x010D,
0180     0x0112,
0181     0x0117,
0182     0x011C,
0183     0x0121,
0184     0x0126,
0185     0x012B,
0186     0x0130,
0187     0x013A,
0188 };
0189 
0190 /* for si5340, si5342 and si5344 */
0191 static const u16 si5340_reg_output_offset[] = {
0192     0x0112,
0193     0x0117,
0194     0x0126,
0195     0x012B,
0196 };
0197 
0198 /* The location of the R divider registers */
0199 static const u16 si5341_reg_rdiv_offset[] = {
0200     0x024A,
0201     0x024D,
0202     0x0250,
0203     0x0253,
0204     0x0256,
0205     0x0259,
0206     0x025C,
0207     0x025F,
0208     0x0262,
0209     0x0268,
0210 };
0211 static const u16 si5340_reg_rdiv_offset[] = {
0212     0x0250,
0213     0x0253,
0214     0x025C,
0215     0x025F,
0216 };
0217 
0218 /*
0219  * Programming sequence from ClockBuilder, settings to initialize the system
0220  * using only the XTAL input, without pre-divider.
0221  * This also contains settings that aren't mentioned anywhere in the datasheet.
0222  * The "known" settings like synth and output configuration are done later.
0223  */
0224 static const struct si5341_reg_default si5341_reg_defaults[] = {
0225     { 0x0017, 0x3A }, /* INT mask (disable interrupts) */
0226     { 0x0018, 0xFF }, /* INT mask */
0227     { 0x0021, 0x0F }, /* Select XTAL as input */
0228     { 0x0022, 0x00 }, /* Not in datasheet */
0229     { 0x002B, 0x02 }, /* SPI config */
0230     { 0x002C, 0x20 }, /* LOS enable for XTAL */
0231     { 0x002D, 0x00 }, /* LOS timing */
0232     { 0x002E, 0x00 },
0233     { 0x002F, 0x00 },
0234     { 0x0030, 0x00 },
0235     { 0x0031, 0x00 },
0236     { 0x0032, 0x00 },
0237     { 0x0033, 0x00 },
0238     { 0x0034, 0x00 },
0239     { 0x0035, 0x00 },
0240     { 0x0036, 0x00 },
0241     { 0x0037, 0x00 },
0242     { 0x0038, 0x00 }, /* LOS setting (thresholds) */
0243     { 0x0039, 0x00 },
0244     { 0x003A, 0x00 },
0245     { 0x003B, 0x00 },
0246     { 0x003C, 0x00 },
0247     { 0x003D, 0x00 }, /* LOS setting (thresholds) end */
0248     { 0x0041, 0x00 }, /* LOS0_DIV_SEL */
0249     { 0x0042, 0x00 }, /* LOS1_DIV_SEL */
0250     { 0x0043, 0x00 }, /* LOS2_DIV_SEL */
0251     { 0x0044, 0x00 }, /* LOS3_DIV_SEL */
0252     { 0x009E, 0x00 }, /* Not in datasheet */
0253     { 0x0102, 0x01 }, /* Enable outputs */
0254     { 0x013F, 0x00 }, /* Not in datasheet */
0255     { 0x0140, 0x00 }, /* Not in datasheet */
0256     { 0x0141, 0x40 }, /* OUT LOS */
0257     { 0x0202, 0x00 }, /* XAXB_FREQ_OFFSET (=0)*/
0258     { 0x0203, 0x00 },
0259     { 0x0204, 0x00 },
0260     { 0x0205, 0x00 },
0261     { 0x0206, 0x00 }, /* PXAXB (2^x) */
0262     { 0x0208, 0x00 }, /* Px divider setting (usually 0) */
0263     { 0x0209, 0x00 },
0264     { 0x020A, 0x00 },
0265     { 0x020B, 0x00 },
0266     { 0x020C, 0x00 },
0267     { 0x020D, 0x00 },
0268     { 0x020E, 0x00 },
0269     { 0x020F, 0x00 },
0270     { 0x0210, 0x00 },
0271     { 0x0211, 0x00 },
0272     { 0x0212, 0x00 },
0273     { 0x0213, 0x00 },
0274     { 0x0214, 0x00 },
0275     { 0x0215, 0x00 },
0276     { 0x0216, 0x00 },
0277     { 0x0217, 0x00 },
0278     { 0x0218, 0x00 },
0279     { 0x0219, 0x00 },
0280     { 0x021A, 0x00 },
0281     { 0x021B, 0x00 },
0282     { 0x021C, 0x00 },
0283     { 0x021D, 0x00 },
0284     { 0x021E, 0x00 },
0285     { 0x021F, 0x00 },
0286     { 0x0220, 0x00 },
0287     { 0x0221, 0x00 },
0288     { 0x0222, 0x00 },
0289     { 0x0223, 0x00 },
0290     { 0x0224, 0x00 },
0291     { 0x0225, 0x00 },
0292     { 0x0226, 0x00 },
0293     { 0x0227, 0x00 },
0294     { 0x0228, 0x00 },
0295     { 0x0229, 0x00 },
0296     { 0x022A, 0x00 },
0297     { 0x022B, 0x00 },
0298     { 0x022C, 0x00 },
0299     { 0x022D, 0x00 },
0300     { 0x022E, 0x00 },
0301     { 0x022F, 0x00 }, /* Px divider setting (usually 0) end */
0302     { 0x026B, 0x00 }, /* DESIGN_ID (ASCII string) */
0303     { 0x026C, 0x00 },
0304     { 0x026D, 0x00 },
0305     { 0x026E, 0x00 },
0306     { 0x026F, 0x00 },
0307     { 0x0270, 0x00 },
0308     { 0x0271, 0x00 },
0309     { 0x0272, 0x00 }, /* DESIGN_ID (ASCII string) end */
0310     { 0x0339, 0x1F }, /* N_FSTEP_MSK */
0311     { 0x033B, 0x00 }, /* Nx_FSTEPW (Frequency step) */
0312     { 0x033C, 0x00 },
0313     { 0x033D, 0x00 },
0314     { 0x033E, 0x00 },
0315     { 0x033F, 0x00 },
0316     { 0x0340, 0x00 },
0317     { 0x0341, 0x00 },
0318     { 0x0342, 0x00 },
0319     { 0x0343, 0x00 },
0320     { 0x0344, 0x00 },
0321     { 0x0345, 0x00 },
0322     { 0x0346, 0x00 },
0323     { 0x0347, 0x00 },
0324     { 0x0348, 0x00 },
0325     { 0x0349, 0x00 },
0326     { 0x034A, 0x00 },
0327     { 0x034B, 0x00 },
0328     { 0x034C, 0x00 },
0329     { 0x034D, 0x00 },
0330     { 0x034E, 0x00 },
0331     { 0x034F, 0x00 },
0332     { 0x0350, 0x00 },
0333     { 0x0351, 0x00 },
0334     { 0x0352, 0x00 },
0335     { 0x0353, 0x00 },
0336     { 0x0354, 0x00 },
0337     { 0x0355, 0x00 },
0338     { 0x0356, 0x00 },
0339     { 0x0357, 0x00 },
0340     { 0x0358, 0x00 }, /* Nx_FSTEPW (Frequency step) end */
0341     { 0x0359, 0x00 }, /* Nx_DELAY */
0342     { 0x035A, 0x00 },
0343     { 0x035B, 0x00 },
0344     { 0x035C, 0x00 },
0345     { 0x035D, 0x00 },
0346     { 0x035E, 0x00 },
0347     { 0x035F, 0x00 },
0348     { 0x0360, 0x00 },
0349     { 0x0361, 0x00 },
0350     { 0x0362, 0x00 }, /* Nx_DELAY end */
0351     { 0x0802, 0x00 }, /* Not in datasheet */
0352     { 0x0803, 0x00 }, /* Not in datasheet */
0353     { 0x0804, 0x00 }, /* Not in datasheet */
0354     { 0x090E, 0x02 }, /* XAXB_EXTCLK_EN=0 XAXB_PDNB=1 (use XTAL) */
0355     { 0x091C, 0x04 }, /* ZDM_EN=4 (Normal mode) */
0356     { 0x0949, 0x00 }, /* IN_EN (disable input clocks) */
0357     { 0x094A, 0x00 }, /* INx_TO_PFD_EN (disabled) */
0358     { 0x0A02, 0x00 }, /* Not in datasheet */
0359     { 0x0B44, 0x0F }, /* PDIV_ENB (datasheet does not mention what it is) */
0360     { 0x0B57, 0x10 }, /* VCO_RESET_CALCODE (not described in datasheet) */
0361     { 0x0B58, 0x05 }, /* VCO_RESET_CALCODE (not described in datasheet) */
0362 };
0363 
0364 /* Read and interpret a 44-bit followed by a 32-bit value in the regmap */
0365 static int si5341_decode_44_32(struct regmap *regmap, unsigned int reg,
0366     u64 *val1, u32 *val2)
0367 {
0368     int err;
0369     u8 r[10];
0370 
0371     err = regmap_bulk_read(regmap, reg, r, 10);
0372     if (err < 0)
0373         return err;
0374 
0375     *val1 = ((u64)((r[5] & 0x0f) << 8 | r[4]) << 32) |
0376          (get_unaligned_le32(r));
0377     *val2 = get_unaligned_le32(&r[6]);
0378 
0379     return 0;
0380 }
0381 
0382 static int si5341_encode_44_32(struct regmap *regmap, unsigned int reg,
0383     u64 n_num, u32 n_den)
0384 {
0385     u8 r[10];
0386 
0387     /* Shift left as far as possible without overflowing */
0388     while (!(n_num & BIT_ULL(43)) && !(n_den & BIT(31))) {
0389         n_num <<= 1;
0390         n_den <<= 1;
0391     }
0392 
0393     /* 44 bits (6 bytes) numerator */
0394     put_unaligned_le32(n_num, r);
0395     r[4] = (n_num >> 32) & 0xff;
0396     r[5] = (n_num >> 40) & 0x0f;
0397     /* 32 bits denominator */
0398     put_unaligned_le32(n_den, &r[6]);
0399 
0400     /* Program the fraction */
0401     return regmap_bulk_write(regmap, reg, r, sizeof(r));
0402 }
0403 
0404 /* VCO, we assume it runs at a constant frequency */
0405 static unsigned long si5341_clk_recalc_rate(struct clk_hw *hw,
0406         unsigned long parent_rate)
0407 {
0408     struct clk_si5341 *data = to_clk_si5341(hw);
0409     int err;
0410     u64 res;
0411     u64 m_num;
0412     u32 m_den;
0413     unsigned int shift;
0414 
0415     /* Assume that PDIV is not being used, just read the PLL setting */
0416     err = si5341_decode_44_32(data->regmap, SI5341_PLL_M_NUM,
0417                 &m_num, &m_den);
0418     if (err < 0)
0419         return 0;
0420 
0421     if (!m_num || !m_den)
0422         return 0;
0423 
0424     /*
0425      * Though m_num is 64-bit, only the upper bits are actually used. While
0426      * calculating m_num and m_den, they are shifted as far as possible to
0427      * the left. To avoid 96-bit division here, we just shift them back so
0428      * we can do with just 64 bits.
0429      */
0430     shift = 0;
0431     res = m_num;
0432     while (res & 0xffff00000000ULL) {
0433         ++shift;
0434         res >>= 1;
0435     }
0436     res *= parent_rate;
0437     do_div(res, (m_den >> shift));
0438 
0439     /* We cannot return the actual frequency in 32 bit, store it locally */
0440     data->freq_vco = res;
0441 
0442     /* Report kHz since the value is out of range */
0443     do_div(res, 1000);
0444 
0445     return (unsigned long)res;
0446 }
0447 
0448 static int si5341_clk_get_selected_input(struct clk_si5341 *data)
0449 {
0450     int err;
0451     u32 val;
0452 
0453     err = regmap_read(data->regmap, SI5341_IN_SEL, &val);
0454     if (err < 0)
0455         return err;
0456 
0457     return (val & SI5341_IN_SEL_MASK) >> SI5341_IN_SEL_SHIFT;
0458 }
0459 
0460 static u8 si5341_clk_get_parent(struct clk_hw *hw)
0461 {
0462     struct clk_si5341 *data = to_clk_si5341(hw);
0463     int res = si5341_clk_get_selected_input(data);
0464 
0465     if (res < 0)
0466         return 0; /* Apparently we cannot report errors */
0467 
0468     return res;
0469 }
0470 
0471 static int si5341_clk_reparent(struct clk_si5341 *data, u8 index)
0472 {
0473     int err;
0474     u8 val;
0475 
0476     val = (index << SI5341_IN_SEL_SHIFT) & SI5341_IN_SEL_MASK;
0477     /* Enable register-based input selection */
0478     val |= SI5341_IN_SEL_REGCTRL;
0479 
0480     err = regmap_update_bits(data->regmap,
0481         SI5341_IN_SEL, SI5341_IN_SEL_REGCTRL | SI5341_IN_SEL_MASK, val);
0482     if (err < 0)
0483         return err;
0484 
0485     if (index < 3) {
0486         /* Enable input buffer for selected input */
0487         err = regmap_update_bits(data->regmap,
0488                 SI5341_IN_EN, 0x07, BIT(index));
0489         if (err < 0)
0490             return err;
0491 
0492         /* Enables the input to phase detector */
0493         err = regmap_update_bits(data->regmap, SI5341_INX_TO_PFD_EN,
0494                 0x7 << SI5341_INX_TO_PFD_SHIFT,
0495                 BIT(index + SI5341_INX_TO_PFD_SHIFT));
0496         if (err < 0)
0497             return err;
0498 
0499         /* Power down XTAL oscillator and buffer */
0500         err = regmap_update_bits(data->regmap, SI5341_XAXB_CFG,
0501                 SI5341_XAXB_CFG_PDNB, 0);
0502         if (err < 0)
0503             return err;
0504 
0505         /*
0506          * Set the P divider to "1". There's no explanation in the
0507          * datasheet of these registers, but the clockbuilder software
0508          * programs a "1" when the input is being used.
0509          */
0510         err = regmap_write(data->regmap, SI5341_IN_PDIV(index), 1);
0511         if (err < 0)
0512             return err;
0513 
0514         err = regmap_write(data->regmap, SI5341_IN_PSET(index), 1);
0515         if (err < 0)
0516             return err;
0517 
0518         /* Set update PDIV bit */
0519         err = regmap_write(data->regmap, SI5341_PX_UPD, BIT(index));
0520         if (err < 0)
0521             return err;
0522     } else {
0523         /* Disable all input buffers */
0524         err = regmap_update_bits(data->regmap, SI5341_IN_EN, 0x07, 0);
0525         if (err < 0)
0526             return err;
0527 
0528         /* Disable input to phase detector */
0529         err = regmap_update_bits(data->regmap, SI5341_INX_TO_PFD_EN,
0530                 0x7 << SI5341_INX_TO_PFD_SHIFT, 0);
0531         if (err < 0)
0532             return err;
0533 
0534         /* Power up XTAL oscillator and buffer, select clock mode */
0535         err = regmap_update_bits(data->regmap, SI5341_XAXB_CFG,
0536                 SI5341_XAXB_CFG_PDNB | SI5341_XAXB_CFG_EXTCLK_EN,
0537                 SI5341_XAXB_CFG_PDNB | (data->xaxb_ext_clk ?
0538                     SI5341_XAXB_CFG_EXTCLK_EN : 0));
0539         if (err < 0)
0540             return err;
0541     }
0542 
0543     return 0;
0544 }
0545 
0546 static int si5341_clk_set_parent(struct clk_hw *hw, u8 index)
0547 {
0548     struct clk_si5341 *data = to_clk_si5341(hw);
0549 
0550     return si5341_clk_reparent(data, index);
0551 }
0552 
0553 static const struct clk_ops si5341_clk_ops = {
0554     .set_parent = si5341_clk_set_parent,
0555     .get_parent = si5341_clk_get_parent,
0556     .recalc_rate = si5341_clk_recalc_rate,
0557 };
0558 
0559 /* Synthesizers, there are 5 synthesizers that connect to any of the outputs */
0560 
0561 /* The synthesizer is on if all power and enable bits are set */
0562 static int si5341_synth_clk_is_on(struct clk_hw *hw)
0563 {
0564     struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
0565     int err;
0566     u32 val;
0567     u8 index = synth->index;
0568 
0569     err = regmap_read(synth->data->regmap,
0570             SI5341_SYNTH_N_CLK_TO_OUTX_EN, &val);
0571     if (err < 0)
0572         return 0;
0573 
0574     if (!(val & BIT(index)))
0575         return 0;
0576 
0577     err = regmap_read(synth->data->regmap, SI5341_SYNTH_N_PDNB, &val);
0578     if (err < 0)
0579         return 0;
0580 
0581     if (!(val & BIT(index)))
0582         return 0;
0583 
0584     /* This bit must be 0 for the synthesizer to receive clock input */
0585     err = regmap_read(synth->data->regmap, SI5341_SYNTH_N_CLK_DIS, &val);
0586     if (err < 0)
0587         return 0;
0588 
0589     return !(val & BIT(index));
0590 }
0591 
0592 static void si5341_synth_clk_unprepare(struct clk_hw *hw)
0593 {
0594     struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
0595     u8 index = synth->index; /* In range 0..5 */
0596     u8 mask = BIT(index);
0597 
0598     /* Disable output */
0599     regmap_update_bits(synth->data->regmap,
0600         SI5341_SYNTH_N_CLK_TO_OUTX_EN, mask, 0);
0601     /* Power down */
0602     regmap_update_bits(synth->data->regmap,
0603         SI5341_SYNTH_N_PDNB, mask, 0);
0604     /* Disable clock input to synth (set to 1 to disable) */
0605     regmap_update_bits(synth->data->regmap,
0606         SI5341_SYNTH_N_CLK_DIS, mask, mask);
0607 }
0608 
0609 static int si5341_synth_clk_prepare(struct clk_hw *hw)
0610 {
0611     struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
0612     int err;
0613     u8 index = synth->index;
0614     u8 mask = BIT(index);
0615 
0616     /* Power up */
0617     err = regmap_update_bits(synth->data->regmap,
0618         SI5341_SYNTH_N_PDNB, mask, mask);
0619     if (err < 0)
0620         return err;
0621 
0622     /* Enable clock input to synth (set bit to 0 to enable) */
0623     err = regmap_update_bits(synth->data->regmap,
0624         SI5341_SYNTH_N_CLK_DIS, mask, 0);
0625     if (err < 0)
0626         return err;
0627 
0628     /* Enable output */
0629     return regmap_update_bits(synth->data->regmap,
0630         SI5341_SYNTH_N_CLK_TO_OUTX_EN, mask, mask);
0631 }
0632 
0633 /* Synth clock frequency: Fvco * n_den / n_den, with Fvco in 13500-14256 MHz */
0634 static unsigned long si5341_synth_clk_recalc_rate(struct clk_hw *hw,
0635         unsigned long parent_rate)
0636 {
0637     struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
0638     u64 f;
0639     u64 n_num;
0640     u32 n_den;
0641     int err;
0642 
0643     err = si5341_decode_44_32(synth->data->regmap,
0644             SI5341_SYNTH_N_NUM(synth->index), &n_num, &n_den);
0645     if (err < 0)
0646         return err;
0647     /* Check for bogus/uninitialized settings */
0648     if (!n_num || !n_den)
0649         return 0;
0650 
0651     /*
0652      * n_num and n_den are shifted left as much as possible, so to prevent
0653      * overflow in 64-bit math, we shift n_den 4 bits to the right
0654      */
0655     f = synth->data->freq_vco;
0656     f *= n_den >> 4;
0657 
0658     /* Now we need to do 64-bit division: f/n_num */
0659     /* And compensate for the 4 bits we dropped */
0660     f = div64_u64(f, (n_num >> 4));
0661 
0662     return f;
0663 }
0664 
0665 static long si5341_synth_clk_round_rate(struct clk_hw *hw, unsigned long rate,
0666         unsigned long *parent_rate)
0667 {
0668     struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
0669     u64 f;
0670 
0671     /* The synthesizer accuracy is such that anything in range will work */
0672     f = synth->data->freq_vco;
0673     do_div(f, SI5341_SYNTH_N_MAX);
0674     if (rate < f)
0675         return f;
0676 
0677     f = synth->data->freq_vco;
0678     do_div(f, SI5341_SYNTH_N_MIN);
0679     if (rate > f)
0680         return f;
0681 
0682     return rate;
0683 }
0684 
0685 static int si5341_synth_program(struct clk_si5341_synth *synth,
0686     u64 n_num, u32 n_den, bool is_integer)
0687 {
0688     int err;
0689     u8 index = synth->index;
0690 
0691     err = si5341_encode_44_32(synth->data->regmap,
0692             SI5341_SYNTH_N_NUM(index), n_num, n_den);
0693 
0694     err = regmap_update_bits(synth->data->regmap,
0695         SI5341_SYNTH_N_PIBYP, BIT(index), is_integer ? BIT(index) : 0);
0696     if (err < 0)
0697         return err;
0698 
0699     return regmap_write(synth->data->regmap,
0700         SI5341_SYNTH_N_UPD(index), 0x01);
0701 }
0702 
0703 
0704 static int si5341_synth_clk_set_rate(struct clk_hw *hw, unsigned long rate,
0705         unsigned long parent_rate)
0706 {
0707     struct clk_si5341_synth *synth = to_clk_si5341_synth(hw);
0708     u64 n_num;
0709     u32 n_den;
0710     u32 r;
0711     u32 g;
0712     bool is_integer;
0713 
0714     n_num = synth->data->freq_vco;
0715 
0716     /* see if there's an integer solution */
0717     r = do_div(n_num, rate);
0718     is_integer = (r == 0);
0719     if (is_integer) {
0720         /* Integer divider equal to n_num */
0721         n_den = 1;
0722     } else {
0723         /* Calculate a fractional solution */
0724         g = gcd(r, rate);
0725         n_den = rate / g;
0726         n_num *= n_den;
0727         n_num += r / g;
0728     }
0729 
0730     dev_dbg(&synth->data->i2c_client->dev,
0731             "%s(%u): n=0x%llx d=0x%x %s\n", __func__,
0732                 synth->index, n_num, n_den,
0733                 is_integer ? "int" : "frac");
0734 
0735     return si5341_synth_program(synth, n_num, n_den, is_integer);
0736 }
0737 
0738 static const struct clk_ops si5341_synth_clk_ops = {
0739     .is_prepared = si5341_synth_clk_is_on,
0740     .prepare = si5341_synth_clk_prepare,
0741     .unprepare = si5341_synth_clk_unprepare,
0742     .recalc_rate = si5341_synth_clk_recalc_rate,
0743     .round_rate = si5341_synth_clk_round_rate,
0744     .set_rate = si5341_synth_clk_set_rate,
0745 };
0746 
0747 static int si5341_output_clk_is_on(struct clk_hw *hw)
0748 {
0749     struct clk_si5341_output *output = to_clk_si5341_output(hw);
0750     int err;
0751     u32 val;
0752 
0753     err = regmap_read(output->data->regmap,
0754             SI5341_OUT_CONFIG(output), &val);
0755     if (err < 0)
0756         return err;
0757 
0758     /* Bit 0=PDN, 1=OE so only a value of 0x2 enables the output */
0759     return (val & 0x03) == SI5341_OUT_CFG_OE;
0760 }
0761 
0762 /* Disables and then powers down the output */
0763 static void si5341_output_clk_unprepare(struct clk_hw *hw)
0764 {
0765     struct clk_si5341_output *output = to_clk_si5341_output(hw);
0766 
0767     regmap_update_bits(output->data->regmap,
0768             SI5341_OUT_CONFIG(output),
0769             SI5341_OUT_CFG_OE, 0);
0770     regmap_update_bits(output->data->regmap,
0771             SI5341_OUT_CONFIG(output),
0772             SI5341_OUT_CFG_PDN, SI5341_OUT_CFG_PDN);
0773 }
0774 
0775 /* Powers up and then enables the output */
0776 static int si5341_output_clk_prepare(struct clk_hw *hw)
0777 {
0778     struct clk_si5341_output *output = to_clk_si5341_output(hw);
0779     int err;
0780 
0781     err = regmap_update_bits(output->data->regmap,
0782             SI5341_OUT_CONFIG(output),
0783             SI5341_OUT_CFG_PDN, 0);
0784     if (err < 0)
0785         return err;
0786 
0787     return regmap_update_bits(output->data->regmap,
0788             SI5341_OUT_CONFIG(output),
0789             SI5341_OUT_CFG_OE, SI5341_OUT_CFG_OE);
0790 }
0791 
0792 static unsigned long si5341_output_clk_recalc_rate(struct clk_hw *hw,
0793         unsigned long parent_rate)
0794 {
0795     struct clk_si5341_output *output = to_clk_si5341_output(hw);
0796     int err;
0797     u32 val;
0798     u32 r_divider;
0799     u8 r[3];
0800 
0801     err = regmap_read(output->data->regmap,
0802             SI5341_OUT_CONFIG(output), &val);
0803     if (err < 0)
0804         return err;
0805 
0806     /* If SI5341_OUT_CFG_RDIV_FORCE2 is set, r_divider is 2 */
0807     if (val & SI5341_OUT_CFG_RDIV_FORCE2)
0808         return parent_rate / 2;
0809 
0810     err = regmap_bulk_read(output->data->regmap,
0811             SI5341_OUT_R_REG(output), r, 3);
0812     if (err < 0)
0813         return err;
0814 
0815     /* Calculate value as 24-bit integer*/
0816     r_divider = r[2] << 16 | r[1] << 8 | r[0];
0817 
0818     /* If Rx_REG is zero, the divider is disabled, so return a "0" rate */
0819     if (!r_divider)
0820         return 0;
0821 
0822     /* Divider is 2*(Rx_REG+1) */
0823     r_divider += 1;
0824     r_divider <<= 1;
0825 
0826 
0827     return parent_rate / r_divider;
0828 }
0829 
0830 static long si5341_output_clk_round_rate(struct clk_hw *hw, unsigned long rate,
0831         unsigned long *parent_rate)
0832 {
0833     unsigned long r;
0834 
0835     if (!rate)
0836         return 0;
0837 
0838     r = *parent_rate >> 1;
0839 
0840     /* If rate is an even divisor, no changes to parent required */
0841     if (r && !(r % rate))
0842         return (long)rate;
0843 
0844     if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
0845         if (rate > 200000000) {
0846             /* minimum r-divider is 2 */
0847             r = 2;
0848         } else {
0849             /* Take a parent frequency near 400 MHz */
0850             r = (400000000u / rate) & ~1;
0851         }
0852         *parent_rate = r * rate;
0853     } else {
0854         /* We cannot change our parent's rate, report what we can do */
0855         r /= rate;
0856         rate = *parent_rate / (r << 1);
0857     }
0858 
0859     return rate;
0860 }
0861 
0862 static int si5341_output_clk_set_rate(struct clk_hw *hw, unsigned long rate,
0863         unsigned long parent_rate)
0864 {
0865     struct clk_si5341_output *output = to_clk_si5341_output(hw);
0866     u32 r_div;
0867     int err;
0868     u8 r[3];
0869 
0870     if (!rate)
0871         return -EINVAL;
0872 
0873     /* Frequency divider is (r_div + 1) * 2 */
0874     r_div = (parent_rate / rate) >> 1;
0875 
0876     if (r_div <= 1)
0877         r_div = 0;
0878     else if (r_div >= BIT(24))
0879         r_div = BIT(24) - 1;
0880     else
0881         --r_div;
0882 
0883     /* For a value of "2", we set the "OUT0_RDIV_FORCE2" bit */
0884     err = regmap_update_bits(output->data->regmap,
0885             SI5341_OUT_CONFIG(output),
0886             SI5341_OUT_CFG_RDIV_FORCE2,
0887             (r_div == 0) ? SI5341_OUT_CFG_RDIV_FORCE2 : 0);
0888     if (err < 0)
0889         return err;
0890 
0891     /* Always write Rx_REG, because a zero value disables the divider */
0892     r[0] = r_div ? (r_div & 0xff) : 1;
0893     r[1] = (r_div >> 8) & 0xff;
0894     r[2] = (r_div >> 16) & 0xff;
0895     err = regmap_bulk_write(output->data->regmap,
0896             SI5341_OUT_R_REG(output), r, 3);
0897 
0898     return 0;
0899 }
0900 
0901 static int si5341_output_reparent(struct clk_si5341_output *output, u8 index)
0902 {
0903     return regmap_update_bits(output->data->regmap,
0904         SI5341_OUT_MUX_SEL(output), 0x07, index);
0905 }
0906 
0907 static int si5341_output_set_parent(struct clk_hw *hw, u8 index)
0908 {
0909     struct clk_si5341_output *output = to_clk_si5341_output(hw);
0910 
0911     if (index >= output->data->num_synth)
0912         return -EINVAL;
0913 
0914     return si5341_output_reparent(output, index);
0915 }
0916 
0917 static u8 si5341_output_get_parent(struct clk_hw *hw)
0918 {
0919     struct clk_si5341_output *output = to_clk_si5341_output(hw);
0920     u32 val;
0921 
0922     regmap_read(output->data->regmap, SI5341_OUT_MUX_SEL(output), &val);
0923 
0924     return val & 0x7;
0925 }
0926 
0927 static const struct clk_ops si5341_output_clk_ops = {
0928     .is_prepared = si5341_output_clk_is_on,
0929     .prepare = si5341_output_clk_prepare,
0930     .unprepare = si5341_output_clk_unprepare,
0931     .recalc_rate = si5341_output_clk_recalc_rate,
0932     .round_rate = si5341_output_clk_round_rate,
0933     .set_rate = si5341_output_clk_set_rate,
0934     .set_parent = si5341_output_set_parent,
0935     .get_parent = si5341_output_get_parent,
0936 };
0937 
0938 /*
0939  * The chip can be bought in a pre-programmed version, or one can program the
0940  * NVM in the chip to boot up in a preset mode. This routine tries to determine
0941  * if that's the case, or if we need to reset and program everything from
0942  * scratch. Returns negative error, or true/false.
0943  */
0944 static int si5341_is_programmed_already(struct clk_si5341 *data)
0945 {
0946     int err;
0947     u8 r[4];
0948 
0949     /* Read the PLL divider value, it must have a non-zero value */
0950     err = regmap_bulk_read(data->regmap, SI5341_PLL_M_DEN,
0951             r, ARRAY_SIZE(r));
0952     if (err < 0)
0953         return err;
0954 
0955     return !!get_unaligned_le32(r);
0956 }
0957 
0958 static struct clk_hw *
0959 of_clk_si5341_get(struct of_phandle_args *clkspec, void *_data)
0960 {
0961     struct clk_si5341 *data = _data;
0962     unsigned int idx = clkspec->args[1];
0963     unsigned int group = clkspec->args[0];
0964 
0965     switch (group) {
0966     case 0:
0967         if (idx >= data->num_outputs) {
0968             dev_err(&data->i2c_client->dev,
0969                 "invalid output index %u\n", idx);
0970             return ERR_PTR(-EINVAL);
0971         }
0972         return &data->clk[idx].hw;
0973     case 1:
0974         if (idx >= data->num_synth) {
0975             dev_err(&data->i2c_client->dev,
0976                 "invalid synthesizer index %u\n", idx);
0977             return ERR_PTR(-EINVAL);
0978         }
0979         return &data->synth[idx].hw;
0980     case 2:
0981         if (idx > 0) {
0982             dev_err(&data->i2c_client->dev,
0983                 "invalid PLL index %u\n", idx);
0984             return ERR_PTR(-EINVAL);
0985         }
0986         return &data->hw;
0987     default:
0988         dev_err(&data->i2c_client->dev, "invalid group %u\n", group);
0989         return ERR_PTR(-EINVAL);
0990     }
0991 }
0992 
0993 static int si5341_probe_chip_id(struct clk_si5341 *data)
0994 {
0995     int err;
0996     u8 reg[4];
0997     u16 model;
0998 
0999     err = regmap_bulk_read(data->regmap, SI5341_PN_BASE, reg,
1000                 ARRAY_SIZE(reg));
1001     if (err < 0) {
1002         dev_err(&data->i2c_client->dev, "Failed to read chip ID\n");
1003         return err;
1004     }
1005 
1006     model = get_unaligned_le16(reg);
1007 
1008     dev_info(&data->i2c_client->dev, "Chip: %x Grade: %u Rev: %u\n",
1009          model, reg[2], reg[3]);
1010 
1011     switch (model) {
1012     case 0x5340:
1013         data->num_outputs = SI5340_MAX_NUM_OUTPUTS;
1014         data->num_synth = SI5340_NUM_SYNTH;
1015         data->reg_output_offset = si5340_reg_output_offset;
1016         data->reg_rdiv_offset = si5340_reg_rdiv_offset;
1017         break;
1018     case 0x5341:
1019         data->num_outputs = SI5341_MAX_NUM_OUTPUTS;
1020         data->num_synth = SI5341_NUM_SYNTH;
1021         data->reg_output_offset = si5341_reg_output_offset;
1022         data->reg_rdiv_offset = si5341_reg_rdiv_offset;
1023         break;
1024     case 0x5342:
1025         data->num_outputs = SI5342_MAX_NUM_OUTPUTS;
1026         data->num_synth = SI5342_NUM_SYNTH;
1027         data->reg_output_offset = si5340_reg_output_offset;
1028         data->reg_rdiv_offset = si5340_reg_rdiv_offset;
1029         break;
1030     case 0x5344:
1031         data->num_outputs = SI5344_MAX_NUM_OUTPUTS;
1032         data->num_synth = SI5344_NUM_SYNTH;
1033         data->reg_output_offset = si5340_reg_output_offset;
1034         data->reg_rdiv_offset = si5340_reg_rdiv_offset;
1035         break;
1036     case 0x5345:
1037         data->num_outputs = SI5345_MAX_NUM_OUTPUTS;
1038         data->num_synth = SI5345_NUM_SYNTH;
1039         data->reg_output_offset = si5341_reg_output_offset;
1040         data->reg_rdiv_offset = si5341_reg_rdiv_offset;
1041         break;
1042     default:
1043         dev_err(&data->i2c_client->dev, "Model '%x' not supported\n",
1044             model);
1045         return -EINVAL;
1046     }
1047 
1048     data->chip_id = model;
1049 
1050     return 0;
1051 }
1052 
1053 /* Read active settings into the regmap cache for later reference */
1054 static int si5341_read_settings(struct clk_si5341 *data)
1055 {
1056     int err;
1057     u8 i;
1058     u8 r[10];
1059 
1060     err = regmap_bulk_read(data->regmap, SI5341_PLL_M_NUM, r, 10);
1061     if (err < 0)
1062         return err;
1063 
1064     err = regmap_bulk_read(data->regmap,
1065                 SI5341_SYNTH_N_CLK_TO_OUTX_EN, r, 3);
1066     if (err < 0)
1067         return err;
1068 
1069     err = regmap_bulk_read(data->regmap,
1070                 SI5341_SYNTH_N_CLK_DIS, r, 1);
1071     if (err < 0)
1072         return err;
1073 
1074     for (i = 0; i < data->num_synth; ++i) {
1075         err = regmap_bulk_read(data->regmap,
1076                     SI5341_SYNTH_N_NUM(i), r, 10);
1077         if (err < 0)
1078             return err;
1079     }
1080 
1081     for (i = 0; i < data->num_outputs; ++i) {
1082         err = regmap_bulk_read(data->regmap,
1083                     data->reg_output_offset[i], r, 4);
1084         if (err < 0)
1085             return err;
1086 
1087         err = regmap_bulk_read(data->regmap,
1088                     data->reg_rdiv_offset[i], r, 3);
1089         if (err < 0)
1090             return err;
1091     }
1092 
1093     return 0;
1094 }
1095 
1096 static int si5341_write_multiple(struct clk_si5341 *data,
1097     const struct si5341_reg_default *values, unsigned int num_values)
1098 {
1099     unsigned int i;
1100     int res;
1101 
1102     for (i = 0; i < num_values; ++i) {
1103         res = regmap_write(data->regmap,
1104             values[i].address, values[i].value);
1105         if (res < 0) {
1106             dev_err(&data->i2c_client->dev,
1107                 "Failed to write %#x:%#x\n",
1108                 values[i].address, values[i].value);
1109             return res;
1110         }
1111     }
1112 
1113     return 0;
1114 }
1115 
1116 static const struct si5341_reg_default si5341_preamble[] = {
1117     { 0x0B25, 0x00 },
1118     { 0x0502, 0x01 },
1119     { 0x0505, 0x03 },
1120     { 0x0957, 0x17 },
1121     { 0x0B4E, 0x1A },
1122 };
1123 
1124 static const struct si5341_reg_default si5345_preamble[] = {
1125     { 0x0B25, 0x00 },
1126     { 0x0540, 0x01 },
1127 };
1128 
1129 static int si5341_send_preamble(struct clk_si5341 *data)
1130 {
1131     int res;
1132     u32 revision;
1133 
1134     /* For revision 2 and up, the values are slightly different */
1135     res = regmap_read(data->regmap, SI5341_DEVICE_REV, &revision);
1136     if (res < 0)
1137         return res;
1138 
1139     /* Write "preamble" as specified by datasheet */
1140     res = regmap_write(data->regmap, 0xB24, revision < 2 ? 0xD8 : 0xC0);
1141     if (res < 0)
1142         return res;
1143 
1144     /* The si5342..si5345 require a different preamble */
1145     if (data->chip_id > 0x5341)
1146         res = si5341_write_multiple(data,
1147             si5345_preamble, ARRAY_SIZE(si5345_preamble));
1148     else
1149         res = si5341_write_multiple(data,
1150             si5341_preamble, ARRAY_SIZE(si5341_preamble));
1151     if (res < 0)
1152         return res;
1153 
1154     /* Datasheet specifies a 300ms wait after sending the preamble */
1155     msleep(300);
1156 
1157     return 0;
1158 }
1159 
1160 /* Perform a soft reset and write post-amble */
1161 static int si5341_finalize_defaults(struct clk_si5341 *data)
1162 {
1163     int res;
1164     u32 revision;
1165 
1166     res = regmap_write(data->regmap, SI5341_IO_VDD_SEL,
1167                data->iovdd_33 ? 1 : 0);
1168     if (res < 0)
1169         return res;
1170 
1171     res = regmap_read(data->regmap, SI5341_DEVICE_REV, &revision);
1172     if (res < 0)
1173         return res;
1174 
1175     dev_dbg(&data->i2c_client->dev, "%s rev=%u\n", __func__, revision);
1176 
1177     res = regmap_write(data->regmap, SI5341_SOFT_RST, 0x01);
1178     if (res < 0)
1179         return res;
1180 
1181     /* The si5342..si5345 have an additional post-amble */
1182     if (data->chip_id > 0x5341) {
1183         res = regmap_write(data->regmap, 0x540, 0x0);
1184         if (res < 0)
1185             return res;
1186     }
1187 
1188     /* Datasheet does not explain these nameless registers */
1189     res = regmap_write(data->regmap, 0xB24, revision < 2 ? 0xDB : 0xC3);
1190     if (res < 0)
1191         return res;
1192     res = regmap_write(data->regmap, 0x0B25, 0x02);
1193     if (res < 0)
1194         return res;
1195 
1196     return 0;
1197 }
1198 
1199 
1200 static const struct regmap_range si5341_regmap_volatile_range[] = {
1201     regmap_reg_range(0x000C, 0x0012), /* Status */
1202     regmap_reg_range(0x001C, 0x001E), /* reset, finc/fdec */
1203     regmap_reg_range(0x00E2, 0x00FE), /* NVM, interrupts, device ready */
1204     /* Update bits for P divider and synth config */
1205     regmap_reg_range(SI5341_PX_UPD, SI5341_PX_UPD),
1206     regmap_reg_range(SI5341_SYNTH_N_UPD(0), SI5341_SYNTH_N_UPD(0)),
1207     regmap_reg_range(SI5341_SYNTH_N_UPD(1), SI5341_SYNTH_N_UPD(1)),
1208     regmap_reg_range(SI5341_SYNTH_N_UPD(2), SI5341_SYNTH_N_UPD(2)),
1209     regmap_reg_range(SI5341_SYNTH_N_UPD(3), SI5341_SYNTH_N_UPD(3)),
1210     regmap_reg_range(SI5341_SYNTH_N_UPD(4), SI5341_SYNTH_N_UPD(4)),
1211 };
1212 
1213 static const struct regmap_access_table si5341_regmap_volatile = {
1214     .yes_ranges = si5341_regmap_volatile_range,
1215     .n_yes_ranges = ARRAY_SIZE(si5341_regmap_volatile_range),
1216 };
1217 
1218 /* Pages 0, 1, 2, 3, 9, A, B are valid, so there are 12 pages */
1219 static const struct regmap_range_cfg si5341_regmap_ranges[] = {
1220     {
1221         .range_min = 0,
1222         .range_max = SI5341_REGISTER_MAX,
1223         .selector_reg = SI5341_PAGE,
1224         .selector_mask = 0xff,
1225         .selector_shift = 0,
1226         .window_start = 0,
1227         .window_len = 256,
1228     },
1229 };
1230 
1231 static int si5341_wait_device_ready(struct i2c_client *client)
1232 {
1233     int count;
1234 
1235     /* Datasheet warns: Any attempt to read or write any register other
1236      * than DEVICE_READY before DEVICE_READY reads as 0x0F may corrupt the
1237      * NVM programming and may corrupt the register contents, as they are
1238      * read from NVM. Note that this includes accesses to the PAGE register.
1239      * Also: DEVICE_READY is available on every register page, so no page
1240      * change is needed to read it.
1241      * Do this outside regmap to avoid automatic PAGE register access.
1242      * May take up to 300ms to complete.
1243      */
1244     for (count = 0; count < 15; ++count) {
1245         s32 result = i2c_smbus_read_byte_data(client,
1246                               SI5341_DEVICE_READY);
1247         if (result < 0)
1248             return result;
1249         if (result == 0x0F)
1250             return 0;
1251         msleep(20);
1252     }
1253     dev_err(&client->dev, "timeout waiting for DEVICE_READY\n");
1254     return -EIO;
1255 }
1256 
1257 static const struct regmap_config si5341_regmap_config = {
1258     .reg_bits = 8,
1259     .val_bits = 8,
1260     .cache_type = REGCACHE_RBTREE,
1261     .ranges = si5341_regmap_ranges,
1262     .num_ranges = ARRAY_SIZE(si5341_regmap_ranges),
1263     .max_register = SI5341_REGISTER_MAX,
1264     .volatile_table = &si5341_regmap_volatile,
1265 };
1266 
1267 static int si5341_dt_parse_dt(struct clk_si5341 *data,
1268                   struct clk_si5341_output_config *config)
1269 {
1270     struct device_node *child;
1271     struct device_node *np = data->i2c_client->dev.of_node;
1272     u32 num;
1273     u32 val;
1274 
1275     memset(config, 0, sizeof(struct clk_si5341_output_config) *
1276                 SI5341_MAX_NUM_OUTPUTS);
1277 
1278     for_each_child_of_node(np, child) {
1279         if (of_property_read_u32(child, "reg", &num)) {
1280             dev_err(&data->i2c_client->dev, "missing reg property of %s\n",
1281                 child->name);
1282             goto put_child;
1283         }
1284 
1285         if (num >= SI5341_MAX_NUM_OUTPUTS) {
1286             dev_err(&data->i2c_client->dev, "invalid clkout %d\n", num);
1287             goto put_child;
1288         }
1289 
1290         if (!of_property_read_u32(child, "silabs,format", &val)) {
1291             /* Set cm and ampl conservatively to 3v3 settings */
1292             switch (val) {
1293             case 1: /* normal differential */
1294                 config[num].out_cm_ampl_bits = 0x33;
1295                 break;
1296             case 2: /* low-power differential */
1297                 config[num].out_cm_ampl_bits = 0x13;
1298                 break;
1299             case 4: /* LVCMOS */
1300                 config[num].out_cm_ampl_bits = 0x33;
1301                 /* Set SI recommended impedance for LVCMOS */
1302                 config[num].out_format_drv_bits |= 0xc0;
1303                 break;
1304             default:
1305                 dev_err(&data->i2c_client->dev,
1306                     "invalid silabs,format %u for %u\n",
1307                     val, num);
1308                 goto put_child;
1309             }
1310             config[num].out_format_drv_bits &= ~0x07;
1311             config[num].out_format_drv_bits |= val & 0x07;
1312             /* Always enable the SYNC feature */
1313             config[num].out_format_drv_bits |= 0x08;
1314         }
1315 
1316         if (!of_property_read_u32(child, "silabs,common-mode", &val)) {
1317             if (val > 0xf) {
1318                 dev_err(&data->i2c_client->dev,
1319                     "invalid silabs,common-mode %u\n",
1320                     val);
1321                 goto put_child;
1322             }
1323             config[num].out_cm_ampl_bits &= 0xf0;
1324             config[num].out_cm_ampl_bits |= val & 0x0f;
1325         }
1326 
1327         if (!of_property_read_u32(child, "silabs,amplitude", &val)) {
1328             if (val > 0xf) {
1329                 dev_err(&data->i2c_client->dev,
1330                     "invalid silabs,amplitude %u\n",
1331                     val);
1332                 goto put_child;
1333             }
1334             config[num].out_cm_ampl_bits &= 0x0f;
1335             config[num].out_cm_ampl_bits |= (val << 4) & 0xf0;
1336         }
1337 
1338         if (of_property_read_bool(child, "silabs,disable-high"))
1339             config[num].out_format_drv_bits |= 0x10;
1340 
1341         config[num].synth_master =
1342             of_property_read_bool(child, "silabs,synth-master");
1343 
1344         config[num].always_on =
1345             of_property_read_bool(child, "always-on");
1346 
1347         config[num].vdd_sel_bits = 0x08;
1348         if (data->clk[num].vddo_reg) {
1349             int vdd = regulator_get_voltage(data->clk[num].vddo_reg);
1350 
1351             switch (vdd) {
1352             case 3300000:
1353                 config[num].vdd_sel_bits |= 0 << 4;
1354                 break;
1355             case 1800000:
1356                 config[num].vdd_sel_bits |= 1 << 4;
1357                 break;
1358             case 2500000:
1359                 config[num].vdd_sel_bits |= 2 << 4;
1360                 break;
1361             default:
1362                 dev_err(&data->i2c_client->dev,
1363                     "unsupported vddo voltage %d for %s\n",
1364                     vdd, child->name);
1365                 goto put_child;
1366             }
1367         } else {
1368             /* chip seems to default to 2.5V when not set */
1369             dev_warn(&data->i2c_client->dev,
1370                 "no regulator set, defaulting vdd_sel to 2.5V for %s\n",
1371                 child->name);
1372             config[num].vdd_sel_bits |= 2 << 4;
1373         }
1374     }
1375 
1376     return 0;
1377 
1378 put_child:
1379     of_node_put(child);
1380     return -EINVAL;
1381 }
1382 
1383 /*
1384  * If not pre-configured, calculate and set the PLL configuration manually.
1385  * For low-jitter performance, the PLL should be set such that the synthesizers
1386  * only need integer division.
1387  * Without any user guidance, we'll set the PLL to 14GHz, which still allows
1388  * the chip to generate any frequency on its outputs, but jitter performance
1389  * may be sub-optimal.
1390  */
1391 static int si5341_initialize_pll(struct clk_si5341 *data)
1392 {
1393     struct device_node *np = data->i2c_client->dev.of_node;
1394     u32 m_num = 0;
1395     u32 m_den = 0;
1396     int sel;
1397 
1398     if (of_property_read_u32(np, "silabs,pll-m-num", &m_num)) {
1399         dev_err(&data->i2c_client->dev,
1400             "PLL configuration requires silabs,pll-m-num\n");
1401     }
1402     if (of_property_read_u32(np, "silabs,pll-m-den", &m_den)) {
1403         dev_err(&data->i2c_client->dev,
1404             "PLL configuration requires silabs,pll-m-den\n");
1405     }
1406 
1407     if (!m_num || !m_den) {
1408         dev_err(&data->i2c_client->dev,
1409             "PLL configuration invalid, assume 14GHz\n");
1410         sel = si5341_clk_get_selected_input(data);
1411         if (sel < 0)
1412             return sel;
1413 
1414         m_den = clk_get_rate(data->input_clk[sel]) / 10;
1415         m_num = 1400000000;
1416     }
1417 
1418     return si5341_encode_44_32(data->regmap,
1419             SI5341_PLL_M_NUM, m_num, m_den);
1420 }
1421 
1422 static int si5341_clk_select_active_input(struct clk_si5341 *data)
1423 {
1424     int res;
1425     int err;
1426     int i;
1427 
1428     res = si5341_clk_get_selected_input(data);
1429     if (res < 0)
1430         return res;
1431 
1432     /* If the current register setting is invalid, pick the first input */
1433     if (!data->input_clk[res]) {
1434         dev_dbg(&data->i2c_client->dev,
1435             "Input %d not connected, rerouting\n", res);
1436         res = -ENODEV;
1437         for (i = 0; i < SI5341_NUM_INPUTS; ++i) {
1438             if (data->input_clk[i]) {
1439                 res = i;
1440                 break;
1441             }
1442         }
1443         if (res < 0) {
1444             dev_err(&data->i2c_client->dev,
1445                 "No clock input available\n");
1446             return res;
1447         }
1448     }
1449 
1450     /* Make sure the selected clock is also enabled and routed */
1451     err = si5341_clk_reparent(data, res);
1452     if (err < 0)
1453         return err;
1454 
1455     err = clk_prepare_enable(data->input_clk[res]);
1456     if (err < 0)
1457         return err;
1458 
1459     return res;
1460 }
1461 
1462 static ssize_t input_present_show(struct device *dev,
1463                   struct device_attribute *attr,
1464                   char *buf)
1465 {
1466     struct clk_si5341 *data = dev_get_drvdata(dev);
1467     u32 status;
1468     int res = regmap_read(data->regmap, SI5341_STATUS, &status);
1469 
1470     if (res < 0)
1471         return res;
1472     res = !(status & SI5341_STATUS_LOSREF);
1473     return sysfs_emit(buf, "%d\n", res);
1474 }
1475 static DEVICE_ATTR_RO(input_present);
1476 
1477 static ssize_t input_present_sticky_show(struct device *dev,
1478                      struct device_attribute *attr,
1479                      char *buf)
1480 {
1481     struct clk_si5341 *data = dev_get_drvdata(dev);
1482     u32 status;
1483     int res = regmap_read(data->regmap, SI5341_STATUS_STICKY, &status);
1484 
1485     if (res < 0)
1486         return res;
1487     res = !(status & SI5341_STATUS_LOSREF);
1488     return sysfs_emit(buf, "%d\n", res);
1489 }
1490 static DEVICE_ATTR_RO(input_present_sticky);
1491 
1492 static ssize_t pll_locked_show(struct device *dev,
1493                    struct device_attribute *attr,
1494                    char *buf)
1495 {
1496     struct clk_si5341 *data = dev_get_drvdata(dev);
1497     u32 status;
1498     int res = regmap_read(data->regmap, SI5341_STATUS, &status);
1499 
1500     if (res < 0)
1501         return res;
1502     res = !(status & SI5341_STATUS_LOL);
1503     return sysfs_emit(buf, "%d\n", res);
1504 }
1505 static DEVICE_ATTR_RO(pll_locked);
1506 
1507 static ssize_t pll_locked_sticky_show(struct device *dev,
1508                       struct device_attribute *attr,
1509                       char *buf)
1510 {
1511     struct clk_si5341 *data = dev_get_drvdata(dev);
1512     u32 status;
1513     int res = regmap_read(data->regmap, SI5341_STATUS_STICKY, &status);
1514 
1515     if (res < 0)
1516         return res;
1517     res = !(status & SI5341_STATUS_LOL);
1518     return sysfs_emit(buf, "%d\n", res);
1519 }
1520 static DEVICE_ATTR_RO(pll_locked_sticky);
1521 
1522 static ssize_t clear_sticky_store(struct device *dev,
1523                   struct device_attribute *attr,
1524                   const char *buf, size_t count)
1525 {
1526     struct clk_si5341 *data = dev_get_drvdata(dev);
1527     long val;
1528 
1529     if (kstrtol(buf, 10, &val))
1530         return -EINVAL;
1531     if (val) {
1532         int res = regmap_write(data->regmap, SI5341_STATUS_STICKY, 0);
1533 
1534         if (res < 0)
1535             return res;
1536     }
1537     return count;
1538 }
1539 static DEVICE_ATTR_WO(clear_sticky);
1540 
1541 static const struct attribute *si5341_attributes[] = {
1542     &dev_attr_input_present.attr,
1543     &dev_attr_input_present_sticky.attr,
1544     &dev_attr_pll_locked.attr,
1545     &dev_attr_pll_locked_sticky.attr,
1546     &dev_attr_clear_sticky.attr,
1547     NULL
1548 };
1549 
1550 static int si5341_probe(struct i2c_client *client)
1551 {
1552     struct clk_si5341 *data;
1553     struct clk_init_data init;
1554     struct clk *input;
1555     const char *root_clock_name;
1556     const char *synth_clock_names[SI5341_NUM_SYNTH];
1557     int err;
1558     unsigned int i;
1559     struct clk_si5341_output_config config[SI5341_MAX_NUM_OUTPUTS];
1560     bool initialization_required;
1561     u32 status;
1562 
1563     data = devm_kzalloc(&client->dev, sizeof(*data), GFP_KERNEL);
1564     if (!data)
1565         return -ENOMEM;
1566 
1567     data->i2c_client = client;
1568 
1569     /* Must be done before otherwise touching hardware */
1570     err = si5341_wait_device_ready(client);
1571     if (err)
1572         return err;
1573 
1574     for (i = 0; i < SI5341_NUM_INPUTS; ++i) {
1575         input = devm_clk_get(&client->dev, si5341_input_clock_names[i]);
1576         if (IS_ERR(input)) {
1577             if (PTR_ERR(input) == -EPROBE_DEFER)
1578                 return -EPROBE_DEFER;
1579             data->input_clk_name[i] = si5341_input_clock_names[i];
1580         } else {
1581             data->input_clk[i] = input;
1582             data->input_clk_name[i] = __clk_get_name(input);
1583         }
1584     }
1585 
1586     for (i = 0; i < SI5341_MAX_NUM_OUTPUTS; ++i) {
1587         char reg_name[10];
1588 
1589         snprintf(reg_name, sizeof(reg_name), "vddo%d", i);
1590         data->clk[i].vddo_reg = devm_regulator_get_optional(
1591             &client->dev, reg_name);
1592         if (IS_ERR(data->clk[i].vddo_reg)) {
1593             err = PTR_ERR(data->clk[i].vddo_reg);
1594             data->clk[i].vddo_reg = NULL;
1595             if (err == -ENODEV)
1596                 continue;
1597             goto cleanup;
1598         } else {
1599             err = regulator_enable(data->clk[i].vddo_reg);
1600             if (err) {
1601                 dev_err(&client->dev,
1602                     "failed to enable %s regulator: %d\n",
1603                     reg_name, err);
1604                 data->clk[i].vddo_reg = NULL;
1605                 goto cleanup;
1606             }
1607         }
1608     }
1609 
1610     err = si5341_dt_parse_dt(data, config);
1611     if (err)
1612         goto cleanup;
1613 
1614     if (of_property_read_string(client->dev.of_node, "clock-output-names",
1615             &init.name))
1616         init.name = client->dev.of_node->name;
1617     root_clock_name = init.name;
1618 
1619     data->regmap = devm_regmap_init_i2c(client, &si5341_regmap_config);
1620     if (IS_ERR(data->regmap)) {
1621         err = PTR_ERR(data->regmap);
1622         goto cleanup;
1623     }
1624 
1625     i2c_set_clientdata(client, data);
1626 
1627     err = si5341_probe_chip_id(data);
1628     if (err < 0)
1629         goto cleanup;
1630 
1631     if (of_property_read_bool(client->dev.of_node, "silabs,reprogram")) {
1632         initialization_required = true;
1633     } else {
1634         err = si5341_is_programmed_already(data);
1635         if (err < 0)
1636             goto cleanup;
1637 
1638         initialization_required = !err;
1639     }
1640     data->xaxb_ext_clk = of_property_read_bool(client->dev.of_node,
1641                            "silabs,xaxb-ext-clk");
1642     data->iovdd_33 = of_property_read_bool(client->dev.of_node,
1643                            "silabs,iovdd-33");
1644 
1645     if (initialization_required) {
1646         /* Populate the regmap cache in preparation for "cache only" */
1647         err = si5341_read_settings(data);
1648         if (err < 0)
1649             goto cleanup;
1650 
1651         err = si5341_send_preamble(data);
1652         if (err < 0)
1653             goto cleanup;
1654 
1655         /*
1656          * We intend to send all 'final' register values in a single
1657          * transaction. So cache all register writes until we're done
1658          * configuring.
1659          */
1660         regcache_cache_only(data->regmap, true);
1661 
1662         /* Write the configuration pairs from the firmware blob */
1663         err = si5341_write_multiple(data, si5341_reg_defaults,
1664                     ARRAY_SIZE(si5341_reg_defaults));
1665         if (err < 0)
1666             goto cleanup;
1667     }
1668 
1669     /* Input must be up and running at this point */
1670     err = si5341_clk_select_active_input(data);
1671     if (err < 0)
1672         goto cleanup;
1673 
1674     if (initialization_required) {
1675         /* PLL configuration is required */
1676         err = si5341_initialize_pll(data);
1677         if (err < 0)
1678             goto cleanup;
1679     }
1680 
1681     /* Register the PLL */
1682     init.parent_names = data->input_clk_name;
1683     init.num_parents = SI5341_NUM_INPUTS;
1684     init.ops = &si5341_clk_ops;
1685     init.flags = 0;
1686     data->hw.init = &init;
1687 
1688     err = devm_clk_hw_register(&client->dev, &data->hw);
1689     if (err) {
1690         dev_err(&client->dev, "clock registration failed\n");
1691         goto cleanup;
1692     }
1693 
1694     init.num_parents = 1;
1695     init.parent_names = &root_clock_name;
1696     init.ops = &si5341_synth_clk_ops;
1697     for (i = 0; i < data->num_synth; ++i) {
1698         synth_clock_names[i] = devm_kasprintf(&client->dev, GFP_KERNEL,
1699                 "%s.N%u", client->dev.of_node->name, i);
1700         init.name = synth_clock_names[i];
1701         data->synth[i].index = i;
1702         data->synth[i].data = data;
1703         data->synth[i].hw.init = &init;
1704         err = devm_clk_hw_register(&client->dev, &data->synth[i].hw);
1705         if (err) {
1706             dev_err(&client->dev,
1707                 "synth N%u registration failed\n", i);
1708         }
1709     }
1710 
1711     init.num_parents = data->num_synth;
1712     init.parent_names = synth_clock_names;
1713     init.ops = &si5341_output_clk_ops;
1714     for (i = 0; i < data->num_outputs; ++i) {
1715         init.name = kasprintf(GFP_KERNEL, "%s.%d",
1716             client->dev.of_node->name, i);
1717         init.flags = config[i].synth_master ? CLK_SET_RATE_PARENT : 0;
1718         data->clk[i].index = i;
1719         data->clk[i].data = data;
1720         data->clk[i].hw.init = &init;
1721         if (config[i].out_format_drv_bits & 0x07) {
1722             regmap_write(data->regmap,
1723                 SI5341_OUT_FORMAT(&data->clk[i]),
1724                 config[i].out_format_drv_bits);
1725             regmap_write(data->regmap,
1726                 SI5341_OUT_CM(&data->clk[i]),
1727                 config[i].out_cm_ampl_bits);
1728             regmap_update_bits(data->regmap,
1729                 SI5341_OUT_MUX_SEL(&data->clk[i]),
1730                 SI5341_OUT_MUX_VDD_SEL_MASK,
1731                 config[i].vdd_sel_bits);
1732         }
1733         err = devm_clk_hw_register(&client->dev, &data->clk[i].hw);
1734         kfree(init.name); /* clock framework made a copy of the name */
1735         if (err) {
1736             dev_err(&client->dev,
1737                 "output %u registration failed\n", i);
1738             goto cleanup;
1739         }
1740         if (config[i].always_on)
1741             clk_prepare(data->clk[i].hw.clk);
1742     }
1743 
1744     err = devm_of_clk_add_hw_provider(&client->dev, of_clk_si5341_get,
1745             data);
1746     if (err) {
1747         dev_err(&client->dev, "unable to add clk provider\n");
1748         goto cleanup;
1749     }
1750 
1751     if (initialization_required) {
1752         /* Synchronize */
1753         regcache_cache_only(data->regmap, false);
1754         err = regcache_sync(data->regmap);
1755         if (err < 0)
1756             goto cleanup;
1757 
1758         err = si5341_finalize_defaults(data);
1759         if (err < 0)
1760             goto cleanup;
1761     }
1762 
1763     /* wait for device to report input clock present and PLL lock */
1764     err = regmap_read_poll_timeout(data->regmap, SI5341_STATUS, status,
1765         !(status & (SI5341_STATUS_LOSREF | SI5341_STATUS_LOL)),
1766            10000, 250000);
1767     if (err) {
1768         dev_err(&client->dev, "Error waiting for input clock or PLL lock\n");
1769         goto cleanup;
1770     }
1771 
1772     /* clear sticky alarm bits from initialization */
1773     err = regmap_write(data->regmap, SI5341_STATUS_STICKY, 0);
1774     if (err) {
1775         dev_err(&client->dev, "unable to clear sticky status\n");
1776         goto cleanup;
1777     }
1778 
1779     err = sysfs_create_files(&client->dev.kobj, si5341_attributes);
1780     if (err) {
1781         dev_err(&client->dev, "unable to create sysfs files\n");
1782         goto cleanup;
1783     }
1784 
1785     /* Free the names, clk framework makes copies */
1786     for (i = 0; i < data->num_synth; ++i)
1787          devm_kfree(&client->dev, (void *)synth_clock_names[i]);
1788 
1789     return 0;
1790 
1791 cleanup:
1792     for (i = 0; i < SI5341_MAX_NUM_OUTPUTS; ++i) {
1793         if (data->clk[i].vddo_reg)
1794             regulator_disable(data->clk[i].vddo_reg);
1795     }
1796     return err;
1797 }
1798 
1799 static int si5341_remove(struct i2c_client *client)
1800 {
1801     struct clk_si5341 *data = i2c_get_clientdata(client);
1802     int i;
1803 
1804     sysfs_remove_files(&client->dev.kobj, si5341_attributes);
1805 
1806     for (i = 0; i < SI5341_MAX_NUM_OUTPUTS; ++i) {
1807         if (data->clk[i].vddo_reg)
1808             regulator_disable(data->clk[i].vddo_reg);
1809     }
1810 
1811     return 0;
1812 }
1813 
1814 static const struct i2c_device_id si5341_id[] = {
1815     { "si5340", 0 },
1816     { "si5341", 1 },
1817     { "si5342", 2 },
1818     { "si5344", 4 },
1819     { "si5345", 5 },
1820     { }
1821 };
1822 MODULE_DEVICE_TABLE(i2c, si5341_id);
1823 
1824 static const struct of_device_id clk_si5341_of_match[] = {
1825     { .compatible = "silabs,si5340" },
1826     { .compatible = "silabs,si5341" },
1827     { .compatible = "silabs,si5342" },
1828     { .compatible = "silabs,si5344" },
1829     { .compatible = "silabs,si5345" },
1830     { }
1831 };
1832 MODULE_DEVICE_TABLE(of, clk_si5341_of_match);
1833 
1834 static struct i2c_driver si5341_driver = {
1835     .driver = {
1836         .name = "si5341",
1837         .of_match_table = clk_si5341_of_match,
1838     },
1839     .probe_new  = si5341_probe,
1840     .remove     = si5341_remove,
1841     .id_table   = si5341_id,
1842 };
1843 module_i2c_driver(si5341_driver);
1844 
1845 MODULE_AUTHOR("Mike Looijmans <mike.looijmans@topic.nl>");
1846 MODULE_DESCRIPTION("Si5341 driver");
1847 MODULE_LICENSE("GPL");
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