0001
0002
0003
0004
0005
0006
0007 #include <linux/clk-provider.h>
0008 #include <linux/kernel.h>
0009 #include <linux/module.h>
0010 #include <linux/of.h>
0011 #include <linux/platform_device.h>
0012 #include <linux/pwm.h>
0013
0014 struct clk_pwm {
0015 struct clk_hw hw;
0016 struct pwm_device *pwm;
0017 u32 fixed_rate;
0018 };
0019
0020 static inline struct clk_pwm *to_clk_pwm(struct clk_hw *hw)
0021 {
0022 return container_of(hw, struct clk_pwm, hw);
0023 }
0024
0025 static int clk_pwm_prepare(struct clk_hw *hw)
0026 {
0027 struct clk_pwm *clk_pwm = to_clk_pwm(hw);
0028
0029 return pwm_enable(clk_pwm->pwm);
0030 }
0031
0032 static void clk_pwm_unprepare(struct clk_hw *hw)
0033 {
0034 struct clk_pwm *clk_pwm = to_clk_pwm(hw);
0035
0036 pwm_disable(clk_pwm->pwm);
0037 }
0038
0039 static unsigned long clk_pwm_recalc_rate(struct clk_hw *hw,
0040 unsigned long parent_rate)
0041 {
0042 struct clk_pwm *clk_pwm = to_clk_pwm(hw);
0043
0044 return clk_pwm->fixed_rate;
0045 }
0046
0047 static int clk_pwm_get_duty_cycle(struct clk_hw *hw, struct clk_duty *duty)
0048 {
0049 struct clk_pwm *clk_pwm = to_clk_pwm(hw);
0050 struct pwm_state state;
0051
0052 pwm_get_state(clk_pwm->pwm, &state);
0053
0054 duty->num = state.duty_cycle;
0055 duty->den = state.period;
0056
0057 return 0;
0058 }
0059
0060 static const struct clk_ops clk_pwm_ops = {
0061 .prepare = clk_pwm_prepare,
0062 .unprepare = clk_pwm_unprepare,
0063 .recalc_rate = clk_pwm_recalc_rate,
0064 .get_duty_cycle = clk_pwm_get_duty_cycle,
0065 };
0066
0067 static int clk_pwm_probe(struct platform_device *pdev)
0068 {
0069 struct device_node *node = pdev->dev.of_node;
0070 struct clk_init_data init;
0071 struct clk_pwm *clk_pwm;
0072 struct pwm_device *pwm;
0073 struct pwm_args pargs;
0074 const char *clk_name;
0075 int ret;
0076
0077 clk_pwm = devm_kzalloc(&pdev->dev, sizeof(*clk_pwm), GFP_KERNEL);
0078 if (!clk_pwm)
0079 return -ENOMEM;
0080
0081 pwm = devm_pwm_get(&pdev->dev, NULL);
0082 if (IS_ERR(pwm))
0083 return PTR_ERR(pwm);
0084
0085 pwm_get_args(pwm, &pargs);
0086 if (!pargs.period) {
0087 dev_err(&pdev->dev, "invalid PWM period\n");
0088 return -EINVAL;
0089 }
0090
0091 if (of_property_read_u32(node, "clock-frequency", &clk_pwm->fixed_rate))
0092 clk_pwm->fixed_rate = div64_u64(NSEC_PER_SEC, pargs.period);
0093
0094 if (!clk_pwm->fixed_rate) {
0095 dev_err(&pdev->dev, "fixed_rate cannot be zero\n");
0096 return -EINVAL;
0097 }
0098
0099 if (pargs.period != NSEC_PER_SEC / clk_pwm->fixed_rate &&
0100 pargs.period != DIV_ROUND_UP(NSEC_PER_SEC, clk_pwm->fixed_rate)) {
0101 dev_err(&pdev->dev,
0102 "clock-frequency does not match PWM period\n");
0103 return -EINVAL;
0104 }
0105
0106
0107
0108
0109
0110 pwm_apply_args(pwm);
0111 ret = pwm_config(pwm, (pargs.period + 1) >> 1, pargs.period);
0112 if (ret < 0)
0113 return ret;
0114
0115 clk_name = node->name;
0116 of_property_read_string(node, "clock-output-names", &clk_name);
0117
0118 init.name = clk_name;
0119 init.ops = &clk_pwm_ops;
0120 init.flags = 0;
0121 init.num_parents = 0;
0122
0123 clk_pwm->pwm = pwm;
0124 clk_pwm->hw.init = &init;
0125 ret = devm_clk_hw_register(&pdev->dev, &clk_pwm->hw);
0126 if (ret)
0127 return ret;
0128
0129 return of_clk_add_hw_provider(node, of_clk_hw_simple_get, &clk_pwm->hw);
0130 }
0131
0132 static int clk_pwm_remove(struct platform_device *pdev)
0133 {
0134 of_clk_del_provider(pdev->dev.of_node);
0135
0136 return 0;
0137 }
0138
0139 static const struct of_device_id clk_pwm_dt_ids[] = {
0140 { .compatible = "pwm-clock" },
0141 { }
0142 };
0143 MODULE_DEVICE_TABLE(of, clk_pwm_dt_ids);
0144
0145 static struct platform_driver clk_pwm_driver = {
0146 .probe = clk_pwm_probe,
0147 .remove = clk_pwm_remove,
0148 .driver = {
0149 .name = "pwm-clock",
0150 .of_match_table = clk_pwm_dt_ids,
0151 },
0152 };
0153
0154 module_platform_driver(clk_pwm_driver);
0155
0156 MODULE_AUTHOR("Philipp Zabel <p.zabel@pengutronix.de>");
0157 MODULE_DESCRIPTION("PWM clock driver");
0158 MODULE_LICENSE("GPL");