drivers/clk/clk-plldig.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright 2019 NXP
0004  *
0005  * Clock driver for LS1028A Display output interfaces(LCD, DPHY).
0006  */
0007
0008 #include <linux/clk-provider.h>
0009 #include <linux/device.h>
0010 #include <linux/module.h>
0011 #include <linux/err.h>
0012 #include <linux/io.h>
0013 #include <linux/iopoll.h>
0014 #include <linux/of.h>
0015 #include <linux/of_address.h>
0016 #include <linux/of_device.h>
0017 #include <linux/platform_device.h>
0018 #include <linux/slab.h>
0019 #include <linux/bitfield.h>
0020
0021 /* PLLDIG register offsets and bit masks */
0022 #define PLLDIG_REG_PLLSR            0x24
0023 #define PLLDIG_LOCK_MASK            BIT(2)
0024 #define PLLDIG_REG_PLLDV            0x28
0025 #define PLLDIG_MFD_MASK             GENMASK(7, 0)
0026 #define PLLDIG_RFDPHI1_MASK         GENMASK(30, 25)
0027 #define PLLDIG_REG_PLLFM            0x2c
0028 #define PLLDIG_SSCGBYP_ENABLE       BIT(30)
0029 #define PLLDIG_REG_PLLFD            0x30
0030 #define PLLDIG_FDEN                 BIT(30)
0031 #define PLLDIG_FRAC_MASK            GENMASK(15, 0)
0032 #define PLLDIG_REG_PLLCAL1          0x38
0033 #define PLLDIG_REG_PLLCAL2          0x3c
0034
0035 /* Range of the VCO frequencies, in Hz */
0036 #define PLLDIG_MIN_VCO_FREQ         650000000
0037 #define PLLDIG_MAX_VCO_FREQ         1300000000
0038
0039 /* Range of the output frequencies, in Hz */
0040 #define PHI1_MIN_FREQ               27000000UL
0041 #define PHI1_MAX_FREQ               600000000UL
0042
0043 /* Maximum value of the reduced frequency divider */
0044 #define MAX_RFDPHI1          63UL
0045
0046 /* Best value of multiplication factor divider */
0047 #define PLLDIG_DEFAULT_MFD   44
0048
0049 /*
0050  * Denominator part of the fractional part of the
0051  * loop multiplication factor.
0052  */
0053 #define MFDEN          20480
0054
0055 static const struct clk_parent_data parent_data[] = {
0056     { .index = 0 },
0057 };
0058
0059 struct clk_plldig {
0060     struct clk_hw hw;
0061     void __iomem *regs;
0062     unsigned int vco_freq;
0063 };
0064
0065 #define to_clk_plldig(_hw)  container_of(_hw, struct clk_plldig, hw)
0066
0067 static int plldig_enable(struct clk_hw *hw)
0068 {
0069     struct clk_plldig *data = to_clk_plldig(hw);
0070     u32 val;
0071
0072     val = readl(data->regs + PLLDIG_REG_PLLFM);
0073     /*
0074      * Use Bypass mode with PLL off by default, the frequency overshoot
0075      * detector output was disable. SSCG Bypass mode should be enable.
0076      */
0077     val |= PLLDIG_SSCGBYP_ENABLE;
0078     writel(val, data->regs + PLLDIG_REG_PLLFM);
0079
0080     return 0;
0081 }
0082
0083 static void plldig_disable(struct clk_hw *hw)
0084 {
0085     struct clk_plldig *data = to_clk_plldig(hw);
0086     u32 val;
0087
0088     val = readl(data->regs + PLLDIG_REG_PLLFM);
0089
0090     val &= ~PLLDIG_SSCGBYP_ENABLE;
0091     val |= FIELD_PREP(PLLDIG_SSCGBYP_ENABLE, 0x0);
0092
0093     writel(val, data->regs + PLLDIG_REG_PLLFM);
0094 }
0095
0096 static int plldig_is_enabled(struct clk_hw *hw)
0097 {
0098     struct clk_plldig *data = to_clk_plldig(hw);
0099
0100     return readl(data->regs + PLLDIG_REG_PLLFM) &
0101                   PLLDIG_SSCGBYP_ENABLE;
0102 }
0103
0104 static unsigned long plldig_recalc_rate(struct clk_hw *hw,
0105                     unsigned long parent_rate)
0106 {
0107     struct clk_plldig *data = to_clk_plldig(hw);
0108     u32 val, rfdphi1;
0109
0110     val = readl(data->regs + PLLDIG_REG_PLLDV);
0111
0112     /* Check if PLL is bypassed */
0113     if (val & PLLDIG_SSCGBYP_ENABLE)
0114         return parent_rate;
0115
0116     rfdphi1 = FIELD_GET(PLLDIG_RFDPHI1_MASK, val);
0117
0118     /*
0119      * If RFDPHI1 has a value of 1 the VCO frequency is also divided by
0120      * one.
0121      */
0122     if (!rfdphi1)
0123         rfdphi1 = 1;
0124
0125     return DIV_ROUND_UP(data->vco_freq, rfdphi1);
0126 }
0127
0128 static unsigned long plldig_calc_target_div(unsigned long vco_freq,
0129                         unsigned long target_rate)
0130 {
0131     unsigned long div;
0132
0133     div = DIV_ROUND_CLOSEST(vco_freq, target_rate);
0134     div = clamp(div, 1UL, MAX_RFDPHI1);
0135
0136     return div;
0137 }
0138
0139 static int plldig_determine_rate(struct clk_hw *hw,
0140                  struct clk_rate_request *req)
0141 {
0142     struct clk_plldig *data = to_clk_plldig(hw);
0143     unsigned int div;
0144
0145     req->rate = clamp(req->rate, PHI1_MIN_FREQ, PHI1_MAX_FREQ);
0146     div = plldig_calc_target_div(data->vco_freq, req->rate);
0147     req->rate = DIV_ROUND_UP(data->vco_freq, div);
0148
0149     return 0;
0150 }
0151
0152 static int plldig_set_rate(struct clk_hw *hw, unsigned long rate,
0153         unsigned long parent_rate)
0154 {
0155     struct clk_plldig *data = to_clk_plldig(hw);
0156     unsigned int val, cond;
0157     unsigned int rfdphi1;
0158
0159     rate = clamp(rate, PHI1_MIN_FREQ, PHI1_MAX_FREQ);
0160     rfdphi1 = plldig_calc_target_div(data->vco_freq, rate);
0161
0162     /* update the divider value */
0163     val = readl(data->regs + PLLDIG_REG_PLLDV);
0164     val &= ~PLLDIG_RFDPHI1_MASK;
0165     val |= FIELD_PREP(PLLDIG_RFDPHI1_MASK, rfdphi1);
0166     writel(val, data->regs + PLLDIG_REG_PLLDV);
0167
0168     /* waiting for old lock state to clear */
0169     udelay(200);
0170
0171     /* Wait until PLL is locked or timeout */
0172     return readl_poll_timeout_atomic(data->regs + PLLDIG_REG_PLLSR, cond,
0173                      cond & PLLDIG_LOCK_MASK, 0,
0174                      USEC_PER_MSEC);
0175 }
0176
0177 static const struct clk_ops plldig_clk_ops = {
0178     .enable = plldig_enable,
0179     .disable = plldig_disable,
0180     .is_enabled = plldig_is_enabled,
0181     .recalc_rate = plldig_recalc_rate,
0182     .determine_rate = plldig_determine_rate,
0183     .set_rate = plldig_set_rate,
0184 };
0185
0186 static int plldig_init(struct clk_hw *hw)
0187 {
0188     struct clk_plldig *data = to_clk_plldig(hw);
0189     struct clk_hw *parent = clk_hw_get_parent(hw);
0190     unsigned long parent_rate;
0191     unsigned long val;
0192     unsigned long long lltmp;
0193     unsigned int mfd, fracdiv = 0;
0194
0195     if (!parent)
0196         return -EINVAL;
0197
0198     parent_rate = clk_hw_get_rate(parent);
0199
0200     if (data->vco_freq) {
0201         mfd = data->vco_freq / parent_rate;
0202         lltmp = data->vco_freq % parent_rate;
0203         lltmp *= MFDEN;
0204         do_div(lltmp, parent_rate);
0205         fracdiv = lltmp;
0206     } else {
0207         mfd = PLLDIG_DEFAULT_MFD;
0208         data->vco_freq = parent_rate * mfd;
0209     }
0210
0211     val = FIELD_PREP(PLLDIG_MFD_MASK, mfd);
0212     writel(val, data->regs + PLLDIG_REG_PLLDV);
0213
0214     /* Enable fractional divider */
0215     if (fracdiv) {
0216         val = FIELD_PREP(PLLDIG_FRAC_MASK, fracdiv);
0217         val |= PLLDIG_FDEN;
0218         writel(val, data->regs + PLLDIG_REG_PLLFD);
0219     }
0220
0221     return 0;
0222 }
0223
0224 static int plldig_clk_probe(struct platform_device *pdev)
0225 {
0226     struct clk_plldig *data;
0227     struct device *dev = &pdev->dev;
0228     int ret;
0229
0230     data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
0231     if (!data)
0232         return -ENOMEM;
0233
0234     data->regs = devm_platform_ioremap_resource(pdev, 0);
0235     if (IS_ERR(data->regs))
0236         return PTR_ERR(data->regs);
0237
0238     data->hw.init = CLK_HW_INIT_PARENTS_DATA("dpclk",
0239                          parent_data,
0240                          &plldig_clk_ops,
0241                          0);
0242
0243     ret = devm_clk_hw_register(dev, &data->hw);
0244     if (ret) {
0245         dev_err(dev, "failed to register %s clock\n",
0246                         dev->of_node->name);
0247         return ret;
0248     }
0249
0250     ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
0251                       &data->hw);
0252     if (ret) {
0253         dev_err(dev, "unable to add clk provider\n");
0254         return ret;
0255     }
0256
0257     /*
0258      * The frequency of the VCO cannot be changed during runtime.
0259      * Therefore, let the user specify a desired frequency.
0260      */
0261     if (!of_property_read_u32(dev->of_node, "fsl,vco-hz",
0262                   &data->vco_freq)) {
0263         if (data->vco_freq < PLLDIG_MIN_VCO_FREQ ||
0264             data->vco_freq > PLLDIG_MAX_VCO_FREQ)
0265             return -EINVAL;
0266     }
0267
0268     return plldig_init(&data->hw);
0269 }
0270
0271 static const struct of_device_id plldig_clk_id[] = {
0272     { .compatible = "fsl,ls1028a-plldig" },
0273     { }
0274 };
0275 MODULE_DEVICE_TABLE(of, plldig_clk_id);
0276
0277 static struct platform_driver plldig_clk_driver = {
0278     .driver = {
0279         .name = "plldig-clock",
0280         .of_match_table = plldig_clk_id,
0281     },
0282     .probe = plldig_clk_probe,
0283 };
0284 module_platform_driver(plldig_clk_driver);
0285
0286 MODULE_LICENSE("GPL v2");
0287 MODULE_AUTHOR("Wen He <wen.he_1@nxp.com>");
0288 MODULE_DESCRIPTION("LS1028A Display output interface pixel clock driver");