drivers/clk/clk-oxnas.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (C) 2010 Broadcom
0004  * Copyright (C) 2012 Stephen Warren
0005  * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
0006  */
0007
0008 #include <linux/clk-provider.h>
0009 #include <linux/kernel.h>
0010 #include <linux/init.h>
0011 #include <linux/of.h>
0012 #include <linux/of_device.h>
0013 #include <linux/platform_device.h>
0014 #include <linux/stringify.h>
0015 #include <linux/regmap.h>
0016 #include <linux/mfd/syscon.h>
0017
0018 #include <dt-bindings/clock/oxsemi,ox810se.h>
0019 #include <dt-bindings/clock/oxsemi,ox820.h>
0020
0021 /* Standard regmap gate clocks */
0022 struct clk_oxnas_gate {
0023     struct clk_hw hw;
0024     unsigned int bit;
0025     struct regmap *regmap;
0026 };
0027
0028 struct oxnas_stdclk_data {
0029     struct clk_hw_onecell_data *onecell_data;
0030     struct clk_oxnas_gate **gates;
0031     unsigned int ngates;
0032     struct clk_oxnas_pll **plls;
0033     unsigned int nplls;
0034 };
0035
0036 /* Regmap offsets */
0037 #define CLK_STAT_REGOFFSET  0x24
0038 #define CLK_SET_REGOFFSET   0x2c
0039 #define CLK_CLR_REGOFFSET   0x30
0040
0041 static inline struct clk_oxnas_gate *to_clk_oxnas_gate(struct clk_hw *hw)
0042 {
0043     return container_of(hw, struct clk_oxnas_gate, hw);
0044 }
0045
0046 static int oxnas_clk_gate_is_enabled(struct clk_hw *hw)
0047 {
0048     struct clk_oxnas_gate *std = to_clk_oxnas_gate(hw);
0049     int ret;
0050     unsigned int val;
0051
0052     ret = regmap_read(std->regmap, CLK_STAT_REGOFFSET, &val);
0053     if (ret < 0)
0054         return ret;
0055
0056     return val & BIT(std->bit);
0057 }
0058
0059 static int oxnas_clk_gate_enable(struct clk_hw *hw)
0060 {
0061     struct clk_oxnas_gate *std = to_clk_oxnas_gate(hw);
0062
0063     regmap_write(std->regmap, CLK_SET_REGOFFSET, BIT(std->bit));
0064
0065     return 0;
0066 }
0067
0068 static void oxnas_clk_gate_disable(struct clk_hw *hw)
0069 {
0070     struct clk_oxnas_gate *std = to_clk_oxnas_gate(hw);
0071
0072     regmap_write(std->regmap, CLK_CLR_REGOFFSET, BIT(std->bit));
0073 }
0074
0075 static const struct clk_ops oxnas_clk_gate_ops = {
0076     .enable = oxnas_clk_gate_enable,
0077     .disable = oxnas_clk_gate_disable,
0078     .is_enabled = oxnas_clk_gate_is_enabled,
0079 };
0080
0081 static const char *const osc_parents[] = {
0082     "oscillator",
0083 };
0084
0085 static const char *const eth_parents[] = {
0086     "gmacclk",
0087 };
0088
0089 #define OXNAS_GATE(_name, _bit, _parents)               \
0090 struct clk_oxnas_gate _name = {                     \
0091     .bit = (_bit),                          \
0092     .hw.init = &(struct clk_init_data) {                \
0093         .name = #_name,                     \
0094         .ops = &oxnas_clk_gate_ops,             \
0095         .parent_names = _parents,               \
0096         .num_parents = ARRAY_SIZE(_parents),            \
0097         .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), \
0098     },                              \
0099 }
0100
0101 static OXNAS_GATE(ox810se_leon, 0, osc_parents);
0102 static OXNAS_GATE(ox810se_dma_sgdma, 1, osc_parents);
0103 static OXNAS_GATE(ox810se_cipher, 2, osc_parents);
0104 static OXNAS_GATE(ox810se_sata, 4, osc_parents);
0105 static OXNAS_GATE(ox810se_audio, 5, osc_parents);
0106 static OXNAS_GATE(ox810se_usbmph, 6, osc_parents);
0107 static OXNAS_GATE(ox810se_etha, 7, eth_parents);
0108 static OXNAS_GATE(ox810se_pciea, 8, osc_parents);
0109 static OXNAS_GATE(ox810se_nand, 9, osc_parents);
0110
0111 static struct clk_oxnas_gate *ox810se_gates[] = {
0112     &ox810se_leon,
0113     &ox810se_dma_sgdma,
0114     &ox810se_cipher,
0115     &ox810se_sata,
0116     &ox810se_audio,
0117     &ox810se_usbmph,
0118     &ox810se_etha,
0119     &ox810se_pciea,
0120     &ox810se_nand,
0121 };
0122
0123 static OXNAS_GATE(ox820_leon, 0, osc_parents);
0124 static OXNAS_GATE(ox820_dma_sgdma, 1, osc_parents);
0125 static OXNAS_GATE(ox820_cipher, 2, osc_parents);
0126 static OXNAS_GATE(ox820_sd, 3, osc_parents);
0127 static OXNAS_GATE(ox820_sata, 4, osc_parents);
0128 static OXNAS_GATE(ox820_audio, 5, osc_parents);
0129 static OXNAS_GATE(ox820_usbmph, 6, osc_parents);
0130 static OXNAS_GATE(ox820_etha, 7, eth_parents);
0131 static OXNAS_GATE(ox820_pciea, 8, osc_parents);
0132 static OXNAS_GATE(ox820_nand, 9, osc_parents);
0133 static OXNAS_GATE(ox820_ethb, 10, eth_parents);
0134 static OXNAS_GATE(ox820_pcieb, 11, osc_parents);
0135 static OXNAS_GATE(ox820_ref600, 12, osc_parents);
0136 static OXNAS_GATE(ox820_usbdev, 13, osc_parents);
0137
0138 static struct clk_oxnas_gate *ox820_gates[] = {
0139     &ox820_leon,
0140     &ox820_dma_sgdma,
0141     &ox820_cipher,
0142     &ox820_sd,
0143     &ox820_sata,
0144     &ox820_audio,
0145     &ox820_usbmph,
0146     &ox820_etha,
0147     &ox820_pciea,
0148     &ox820_nand,
0149     &ox820_etha,
0150     &ox820_pciea,
0151     &ox820_ref600,
0152     &ox820_usbdev,
0153 };
0154
0155 static struct clk_hw_onecell_data ox810se_hw_onecell_data = {
0156     .hws = {
0157         [CLK_810_LEON]  = &ox810se_leon.hw,
0158         [CLK_810_DMA_SGDMA] = &ox810se_dma_sgdma.hw,
0159         [CLK_810_CIPHER]    = &ox810se_cipher.hw,
0160         [CLK_810_SATA]  = &ox810se_sata.hw,
0161         [CLK_810_AUDIO] = &ox810se_audio.hw,
0162         [CLK_810_USBMPH]    = &ox810se_usbmph.hw,
0163         [CLK_810_ETHA]  = &ox810se_etha.hw,
0164         [CLK_810_PCIEA] = &ox810se_pciea.hw,
0165         [CLK_810_NAND]  = &ox810se_nand.hw,
0166     },
0167     .num = ARRAY_SIZE(ox810se_gates),
0168 };
0169
0170 static struct clk_hw_onecell_data ox820_hw_onecell_data = {
0171     .hws = {
0172         [CLK_820_LEON]  = &ox820_leon.hw,
0173         [CLK_820_DMA_SGDMA] = &ox820_dma_sgdma.hw,
0174         [CLK_820_CIPHER]    = &ox820_cipher.hw,
0175         [CLK_820_SD]    = &ox820_sd.hw,
0176         [CLK_820_SATA]  = &ox820_sata.hw,
0177         [CLK_820_AUDIO] = &ox820_audio.hw,
0178         [CLK_820_USBMPH]    = &ox820_usbmph.hw,
0179         [CLK_820_ETHA]  = &ox820_etha.hw,
0180         [CLK_820_PCIEA] = &ox820_pciea.hw,
0181         [CLK_820_NAND]  = &ox820_nand.hw,
0182         [CLK_820_ETHB]  = &ox820_ethb.hw,
0183         [CLK_820_PCIEB] = &ox820_pcieb.hw,
0184         [CLK_820_REF600]    = &ox820_ref600.hw,
0185         [CLK_820_USBDEV]    = &ox820_usbdev.hw,
0186     },
0187     .num = ARRAY_SIZE(ox820_gates),
0188 };
0189
0190 static struct oxnas_stdclk_data ox810se_stdclk_data = {
0191     .onecell_data = &ox810se_hw_onecell_data,
0192     .gates = ox810se_gates,
0193     .ngates = ARRAY_SIZE(ox810se_gates),
0194 };
0195
0196 static struct oxnas_stdclk_data ox820_stdclk_data = {
0197     .onecell_data = &ox820_hw_onecell_data,
0198     .gates = ox820_gates,
0199     .ngates = ARRAY_SIZE(ox820_gates),
0200 };
0201
0202 static const struct of_device_id oxnas_stdclk_dt_ids[] = {
0203     { .compatible = "oxsemi,ox810se-stdclk", &ox810se_stdclk_data },
0204     { .compatible = "oxsemi,ox820-stdclk", &ox820_stdclk_data },
0205     { }
0206 };
0207
0208 static int oxnas_stdclk_probe(struct platform_device *pdev)
0209 {
0210     struct device_node *np = pdev->dev.of_node;
0211     const struct oxnas_stdclk_data *data;
0212     struct regmap *regmap;
0213     int ret;
0214     int i;
0215
0216     data = of_device_get_match_data(&pdev->dev);
0217
0218     regmap = syscon_node_to_regmap(of_get_parent(np));
0219     if (IS_ERR(regmap)) {
0220         dev_err(&pdev->dev, "failed to have parent regmap\n");
0221         return PTR_ERR(regmap);
0222     }
0223
0224     for (i = 0 ; i < data->ngates ; ++i)
0225         data->gates[i]->regmap = regmap;
0226
0227     for (i = 0; i < data->onecell_data->num; i++) {
0228         if (!data->onecell_data->hws[i])
0229             continue;
0230
0231         ret = devm_clk_hw_register(&pdev->dev,
0232                        data->onecell_data->hws[i]);
0233         if (ret)
0234             return ret;
0235     }
0236
0237     return of_clk_add_hw_provider(np, of_clk_hw_onecell_get,
0238                       data->onecell_data);
0239 }
0240
0241 static struct platform_driver oxnas_stdclk_driver = {
0242     .probe = oxnas_stdclk_probe,
0243     .driver = {
0244         .name = "oxnas-stdclk",
0245         .suppress_bind_attrs = true,
0246         .of_match_table = oxnas_stdclk_dt_ids,
0247     },
0248 };
0249 builtin_platform_driver(oxnas_stdclk_driver);