drivers/clk/clk-moxart.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * MOXA ART SoCs clock driver.
0004  *
0005  * Copyright (C) 2013 Jonas Jensen
0006  *
0007  * Jonas Jensen <jonas.jensen@gmail.com>
0008  */
0009
0010 #include <linux/clk.h>
0011 #include <linux/clk-provider.h>
0012 #include <linux/io.h>
0013 #include <linux/of_address.h>
0014 #include <linux/clkdev.h>
0015
0016 static void __init moxart_of_pll_clk_init(struct device_node *node)
0017 {
0018     void __iomem *base;
0019     struct clk_hw *hw;
0020     struct clk *ref_clk;
0021     unsigned int mul;
0022     const char *name = node->name;
0023     const char *parent_name;
0024
0025     of_property_read_string(node, "clock-output-names", &name);
0026     parent_name = of_clk_get_parent_name(node, 0);
0027
0028     base = of_iomap(node, 0);
0029     if (!base) {
0030         pr_err("%pOF: of_iomap failed\n", node);
0031         return;
0032     }
0033
0034     mul = readl(base + 0x30) >> 3 & 0x3f;
0035     iounmap(base);
0036
0037     ref_clk = of_clk_get(node, 0);
0038     if (IS_ERR(ref_clk)) {
0039         pr_err("%pOF: of_clk_get failed\n", node);
0040         return;
0041     }
0042
0043     hw = clk_hw_register_fixed_factor(NULL, name, parent_name, 0, mul, 1);
0044     if (IS_ERR(hw)) {
0045         pr_err("%pOF: failed to register clock\n", node);
0046         return;
0047     }
0048
0049     clk_hw_register_clkdev(hw, NULL, name);
0050     of_clk_add_hw_provider(node, of_clk_hw_simple_get, hw);
0051 }
0052 CLK_OF_DECLARE(moxart_pll_clock, "moxa,moxart-pll-clock",
0053            moxart_of_pll_clk_init);
0054
0055 static void __init moxart_of_apb_clk_init(struct device_node *node)
0056 {
0057     void __iomem *base;
0058     struct clk_hw *hw;
0059     struct clk *pll_clk;
0060     unsigned int div, val;
0061     unsigned int div_idx[] = { 2, 3, 4, 6, 8};
0062     const char *name = node->name;
0063     const char *parent_name;
0064
0065     of_property_read_string(node, "clock-output-names", &name);
0066     parent_name = of_clk_get_parent_name(node, 0);
0067
0068     base = of_iomap(node, 0);
0069     if (!base) {
0070         pr_err("%pOF: of_iomap failed\n", node);
0071         return;
0072     }
0073
0074     val = readl(base + 0xc) >> 4 & 0x7;
0075     iounmap(base);
0076
0077     if (val > 4)
0078         val = 0;
0079     div = div_idx[val] * 2;
0080
0081     pll_clk = of_clk_get(node, 0);
0082     if (IS_ERR(pll_clk)) {
0083         pr_err("%pOF: of_clk_get failed\n", node);
0084         return;
0085     }
0086
0087     hw = clk_hw_register_fixed_factor(NULL, name, parent_name, 0, 1, div);
0088     if (IS_ERR(hw)) {
0089         pr_err("%pOF: failed to register clock\n", node);
0090         return;
0091     }
0092
0093     clk_hw_register_clkdev(hw, NULL, name);
0094     of_clk_add_hw_provider(node, of_clk_hw_simple_get, hw);
0095 }
0096 CLK_OF_DECLARE(moxart_apb_clock, "moxa,moxart-apb-clock",
0097            moxart_of_apb_clk_init);