drivers/clk/clk-max9485.c

0001 // SPDX-License-Identifier: GPL-2.0
0002
0003 #include <linux/module.h>
0004 #include <linux/kernel.h>
0005 #include <linux/clk.h>
0006 #include <linux/clk-provider.h>
0007 #include <linux/err.h>
0008 #include <linux/errno.h>
0009 #include <linux/gpio/consumer.h>
0010 #include <linux/i2c.h>
0011 #include <linux/regulator/consumer.h>
0012
0013 #include <dt-bindings/clock/maxim,max9485.h>
0014
0015 #define MAX9485_NUM_CLKS 4
0016
0017 /* This chip has only one register of 8 bit width. */
0018
0019 #define MAX9485_FS_12KHZ    (0 << 0)
0020 #define MAX9485_FS_32KHZ    (1 << 0)
0021 #define MAX9485_FS_44_1KHZ  (2 << 0)
0022 #define MAX9485_FS_48KHZ    (3 << 0)
0023
0024 #define MAX9485_SCALE_256   (0 << 2)
0025 #define MAX9485_SCALE_384   (1 << 2)
0026 #define MAX9485_SCALE_768   (2 << 2)
0027
0028 #define MAX9485_DOUBLE      BIT(4)
0029 #define MAX9485_CLKOUT1_ENABLE  BIT(5)
0030 #define MAX9485_CLKOUT2_ENABLE  BIT(6)
0031 #define MAX9485_MCLK_ENABLE BIT(7)
0032 #define MAX9485_FREQ_MASK   0x1f
0033
0034 struct max9485_rate {
0035     unsigned long out;
0036     u8 reg_value;
0037 };
0038
0039 /*
0040  * Ordered by frequency. For frequency the hardware can generate with
0041  * multiple settings, the one with lowest jitter is listed first.
0042  */
0043 static const struct max9485_rate max9485_rates[] = {
0044     {  3072000, MAX9485_FS_12KHZ   | MAX9485_SCALE_256 },
0045     {  4608000, MAX9485_FS_12KHZ   | MAX9485_SCALE_384 },
0046     {  8192000, MAX9485_FS_32KHZ   | MAX9485_SCALE_256 },
0047     {  9126000, MAX9485_FS_12KHZ   | MAX9485_SCALE_768 },
0048     { 11289600, MAX9485_FS_44_1KHZ | MAX9485_SCALE_256 },
0049     { 12288000, MAX9485_FS_48KHZ   | MAX9485_SCALE_256 },
0050     { 12288000, MAX9485_FS_32KHZ   | MAX9485_SCALE_384 },
0051     { 16384000, MAX9485_FS_32KHZ   | MAX9485_SCALE_256 | MAX9485_DOUBLE },
0052     { 16934400, MAX9485_FS_44_1KHZ | MAX9485_SCALE_384 },
0053     { 18384000, MAX9485_FS_48KHZ   | MAX9485_SCALE_384 },
0054     { 22579200, MAX9485_FS_44_1KHZ | MAX9485_SCALE_256 | MAX9485_DOUBLE },
0055     { 24576000, MAX9485_FS_48KHZ   | MAX9485_SCALE_256 | MAX9485_DOUBLE },
0056     { 24576000, MAX9485_FS_32KHZ   | MAX9485_SCALE_384 | MAX9485_DOUBLE },
0057     { 24576000, MAX9485_FS_32KHZ   | MAX9485_SCALE_768 },
0058     { 33868800, MAX9485_FS_44_1KHZ | MAX9485_SCALE_384 | MAX9485_DOUBLE },
0059     { 33868800, MAX9485_FS_44_1KHZ | MAX9485_SCALE_768 },
0060     { 36864000, MAX9485_FS_48KHZ   | MAX9485_SCALE_384 | MAX9485_DOUBLE },
0061     { 36864000, MAX9485_FS_48KHZ   | MAX9485_SCALE_768 },
0062     { 49152000, MAX9485_FS_32KHZ   | MAX9485_SCALE_768 | MAX9485_DOUBLE },
0063     { 67737600, MAX9485_FS_44_1KHZ | MAX9485_SCALE_768 | MAX9485_DOUBLE },
0064     { 73728000, MAX9485_FS_48KHZ   | MAX9485_SCALE_768 | MAX9485_DOUBLE },
0065     { } /* sentinel */
0066 };
0067
0068 struct max9485_driver_data;
0069
0070 struct max9485_clk_hw {
0071     struct clk_hw hw;
0072     struct clk_init_data init;
0073     u8 enable_bit;
0074     struct max9485_driver_data *drvdata;
0075 };
0076
0077 struct max9485_driver_data {
0078     struct clk *xclk;
0079     struct i2c_client *client;
0080     u8 reg_value;
0081     struct regulator *supply;
0082     struct gpio_desc *reset_gpio;
0083     struct max9485_clk_hw hw[MAX9485_NUM_CLKS];
0084 };
0085
0086 static inline struct max9485_clk_hw *to_max9485_clk(struct clk_hw *hw)
0087 {
0088     return container_of(hw, struct max9485_clk_hw, hw);
0089 }
0090
0091 static int max9485_update_bits(struct max9485_driver_data *drvdata,
0092                    u8 mask, u8 value)
0093 {
0094     int ret;
0095
0096     drvdata->reg_value &= ~mask;
0097     drvdata->reg_value |= value;
0098
0099     dev_dbg(&drvdata->client->dev,
0100         "updating mask 0x%02x value 0x%02x -> 0x%02x\n",
0101         mask, value, drvdata->reg_value);
0102
0103     ret = i2c_master_send(drvdata->client,
0104                   &drvdata->reg_value,
0105                   sizeof(drvdata->reg_value));
0106
0107     return ret < 0 ? ret : 0;
0108 }
0109
0110 static int max9485_clk_prepare(struct clk_hw *hw)
0111 {
0112     struct max9485_clk_hw *clk_hw = to_max9485_clk(hw);
0113
0114     return max9485_update_bits(clk_hw->drvdata,
0115                    clk_hw->enable_bit,
0116                    clk_hw->enable_bit);
0117 }
0118
0119 static void max9485_clk_unprepare(struct clk_hw *hw)
0120 {
0121     struct max9485_clk_hw *clk_hw = to_max9485_clk(hw);
0122
0123     max9485_update_bits(clk_hw->drvdata, clk_hw->enable_bit, 0);
0124 }
0125
0126 /*
0127  * CLKOUT - configurable clock output
0128  */
0129 static int max9485_clkout_set_rate(struct clk_hw *hw, unsigned long rate,
0130                    unsigned long parent_rate)
0131 {
0132     struct max9485_clk_hw *clk_hw = to_max9485_clk(hw);
0133     const struct max9485_rate *entry;
0134
0135     for (entry = max9485_rates; entry->out != 0; entry++)
0136         if (entry->out == rate)
0137             break;
0138
0139     if (entry->out == 0)
0140         return -EINVAL;
0141
0142     return max9485_update_bits(clk_hw->drvdata,
0143                    MAX9485_FREQ_MASK,
0144                    entry->reg_value);
0145 }
0146
0147 static unsigned long max9485_clkout_recalc_rate(struct clk_hw *hw,
0148                         unsigned long parent_rate)
0149 {
0150     struct max9485_clk_hw *clk_hw = to_max9485_clk(hw);
0151     struct max9485_driver_data *drvdata = clk_hw->drvdata;
0152     u8 val = drvdata->reg_value & MAX9485_FREQ_MASK;
0153     const struct max9485_rate *entry;
0154
0155     for (entry = max9485_rates; entry->out != 0; entry++)
0156         if (val == entry->reg_value)
0157             return entry->out;
0158
0159     return 0;
0160 }
0161
0162 static long max9485_clkout_round_rate(struct clk_hw *hw, unsigned long rate,
0163                       unsigned long *parent_rate)
0164 {
0165     const struct max9485_rate *curr, *prev = NULL;
0166
0167     for (curr = max9485_rates; curr->out != 0; curr++) {
0168         /* Exact matches */
0169         if (curr->out == rate)
0170             return rate;
0171
0172         /*
0173          * Find the first entry that has a frequency higher than the
0174          * requested one.
0175          */
0176         if (curr->out > rate) {
0177             unsigned int mid;
0178
0179             /*
0180              * If this is the first entry, clamp the value to the
0181              * lowest possible frequency.
0182              */
0183             if (!prev)
0184                 return curr->out;
0185
0186             /*
0187              * Otherwise, determine whether the previous entry or
0188              * current one is closer.
0189              */
0190             mid = prev->out + ((curr->out - prev->out) / 2);
0191
0192             return (mid > rate) ? prev->out : curr->out;
0193         }
0194
0195         prev = curr;
0196     }
0197
0198     /* If the last entry was still too high, clamp the value */
0199     return prev->out;
0200 }
0201
0202 struct max9485_clk {
0203     const char *name;
0204     int parent_index;
0205     const struct clk_ops ops;
0206     u8 enable_bit;
0207 };
0208
0209 static const struct max9485_clk max9485_clks[MAX9485_NUM_CLKS] = {
0210     [MAX9485_MCLKOUT] = {
0211         .name = "mclkout",
0212         .parent_index = -1,
0213         .enable_bit = MAX9485_MCLK_ENABLE,
0214         .ops = {
0215             .prepare    = max9485_clk_prepare,
0216             .unprepare  = max9485_clk_unprepare,
0217         },
0218     },
0219     [MAX9485_CLKOUT] = {
0220         .name = "clkout",
0221         .parent_index = -1,
0222         .ops = {
0223             .set_rate   = max9485_clkout_set_rate,
0224             .round_rate = max9485_clkout_round_rate,
0225             .recalc_rate    = max9485_clkout_recalc_rate,
0226         },
0227     },
0228     [MAX9485_CLKOUT1] = {
0229         .name = "clkout1",
0230         .parent_index = MAX9485_CLKOUT,
0231         .enable_bit = MAX9485_CLKOUT1_ENABLE,
0232         .ops = {
0233             .prepare    = max9485_clk_prepare,
0234             .unprepare  = max9485_clk_unprepare,
0235         },
0236     },
0237     [MAX9485_CLKOUT2] = {
0238         .name = "clkout2",
0239         .parent_index = MAX9485_CLKOUT,
0240         .enable_bit = MAX9485_CLKOUT2_ENABLE,
0241         .ops = {
0242             .prepare    = max9485_clk_prepare,
0243             .unprepare  = max9485_clk_unprepare,
0244         },
0245     },
0246 };
0247
0248 static struct clk_hw *
0249 max9485_of_clk_get(struct of_phandle_args *clkspec, void *data)
0250 {
0251     struct max9485_driver_data *drvdata = data;
0252     unsigned int idx = clkspec->args[0];
0253
0254     return &drvdata->hw[idx].hw;
0255 }
0256
0257 static int max9485_i2c_probe(struct i2c_client *client)
0258 {
0259     struct max9485_driver_data *drvdata;
0260     struct device *dev = &client->dev;
0261     const char *xclk_name;
0262     int i, ret;
0263
0264     drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
0265     if (!drvdata)
0266         return -ENOMEM;
0267
0268     drvdata->xclk = devm_clk_get(dev, "xclk");
0269     if (IS_ERR(drvdata->xclk))
0270         return PTR_ERR(drvdata->xclk);
0271
0272     xclk_name = __clk_get_name(drvdata->xclk);
0273
0274     drvdata->supply = devm_regulator_get(dev, "vdd");
0275     if (IS_ERR(drvdata->supply))
0276         return PTR_ERR(drvdata->supply);
0277
0278     ret = regulator_enable(drvdata->supply);
0279     if (ret < 0)
0280         return ret;
0281
0282     drvdata->reset_gpio =
0283         devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
0284     if (IS_ERR(drvdata->reset_gpio))
0285         return PTR_ERR(drvdata->reset_gpio);
0286
0287     i2c_set_clientdata(client, drvdata);
0288     drvdata->client = client;
0289
0290     ret = i2c_master_recv(drvdata->client, &drvdata->reg_value,
0291                   sizeof(drvdata->reg_value));
0292     if (ret < 0) {
0293         dev_warn(dev, "Unable to read device register: %d\n", ret);
0294         return ret;
0295     }
0296
0297     for (i = 0; i < MAX9485_NUM_CLKS; i++) {
0298         int parent_index = max9485_clks[i].parent_index;
0299         const char *name;
0300
0301         if (of_property_read_string_index(dev->of_node,
0302                           "clock-output-names",
0303                           i, &name) == 0) {
0304             drvdata->hw[i].init.name = name;
0305         } else {
0306             drvdata->hw[i].init.name = max9485_clks[i].name;
0307         }
0308
0309         drvdata->hw[i].init.ops = &max9485_clks[i].ops;
0310         drvdata->hw[i].init.num_parents = 1;
0311         drvdata->hw[i].init.flags = 0;
0312
0313         if (parent_index > 0) {
0314             drvdata->hw[i].init.parent_names =
0315                 &drvdata->hw[parent_index].init.name;
0316             drvdata->hw[i].init.flags |= CLK_SET_RATE_PARENT;
0317         } else {
0318             drvdata->hw[i].init.parent_names = &xclk_name;
0319         }
0320
0321         drvdata->hw[i].enable_bit = max9485_clks[i].enable_bit;
0322         drvdata->hw[i].hw.init = &drvdata->hw[i].init;
0323         drvdata->hw[i].drvdata = drvdata;
0324
0325         ret = devm_clk_hw_register(dev, &drvdata->hw[i].hw);
0326         if (ret < 0)
0327             return ret;
0328     }
0329
0330     return devm_of_clk_add_hw_provider(dev, max9485_of_clk_get, drvdata);
0331 }
0332
0333 static int __maybe_unused max9485_suspend(struct device *dev)
0334 {
0335     struct i2c_client *client = to_i2c_client(dev);
0336     struct max9485_driver_data *drvdata = i2c_get_clientdata(client);
0337
0338     gpiod_set_value_cansleep(drvdata->reset_gpio, 0);
0339
0340     return 0;
0341 }
0342
0343 static int __maybe_unused max9485_resume(struct device *dev)
0344 {
0345     struct i2c_client *client = to_i2c_client(dev);
0346     struct max9485_driver_data *drvdata = i2c_get_clientdata(client);
0347     int ret;
0348
0349     gpiod_set_value_cansleep(drvdata->reset_gpio, 1);
0350
0351     ret = i2c_master_send(client, &drvdata->reg_value,
0352                   sizeof(drvdata->reg_value));
0353
0354     return ret < 0 ? ret : 0;
0355 }
0356
0357 static const struct dev_pm_ops max9485_pm_ops = {
0358     SET_SYSTEM_SLEEP_PM_OPS(max9485_suspend, max9485_resume)
0359 };
0360
0361 static const struct of_device_id max9485_dt_ids[] = {
0362     { .compatible = "maxim,max9485", },
0363     { }
0364 };
0365 MODULE_DEVICE_TABLE(of, max9485_dt_ids);
0366
0367 static const struct i2c_device_id max9485_i2c_ids[] = {
0368     { .name = "max9485", },
0369     { }
0370 };
0371 MODULE_DEVICE_TABLE(i2c, max9485_i2c_ids);
0372
0373 static struct i2c_driver max9485_driver = {
0374     .driver = {
0375         .name       = "max9485",
0376         .pm     = &max9485_pm_ops,
0377         .of_match_table = max9485_dt_ids,
0378     },
0379     .probe_new = max9485_i2c_probe,
0380     .id_table = max9485_i2c_ids,
0381 };
0382 module_i2c_driver(max9485_driver);
0383
0384 MODULE_AUTHOR("Daniel Mack <daniel@zonque.org>");
0385 MODULE_DESCRIPTION("MAX9485 Programmable Audio Clock Generator");
0386 MODULE_LICENSE("GPL v2");