drivers/clk/clk-max77686.c

0001 // SPDX-License-Identifier: GPL-2.0+
0002 //
0003 // clk-max77686.c - Clock driver for Maxim 77686/MAX77802
0004 //
0005 // Copyright (C) 2012 Samsung Electornics
0006 // Jonghwa Lee <jonghwa3.lee@samsung.com>
0007
0008 #include <linux/kernel.h>
0009 #include <linux/slab.h>
0010 #include <linux/err.h>
0011 #include <linux/module.h>
0012 #include <linux/platform_device.h>
0013 #include <linux/mfd/max77620.h>
0014 #include <linux/mfd/max77686.h>
0015 #include <linux/mfd/max77686-private.h>
0016 #include <linux/clk-provider.h>
0017 #include <linux/mutex.h>
0018 #include <linux/clkdev.h>
0019 #include <linux/of.h>
0020 #include <linux/regmap.h>
0021
0022 #include <dt-bindings/clock/maxim,max77686.h>
0023 #include <dt-bindings/clock/maxim,max77802.h>
0024 #include <dt-bindings/clock/maxim,max77620.h>
0025
0026 #define MAX77802_CLOCK_LOW_JITTER_SHIFT 0x3
0027
0028 enum max77686_chip_name {
0029     CHIP_MAX77686,
0030     CHIP_MAX77802,
0031     CHIP_MAX77620,
0032 };
0033
0034 struct max77686_hw_clk_info {
0035     const char *name;
0036     u32 clk_reg;
0037     u32 clk_enable_mask;
0038     u32 flags;
0039 };
0040
0041 struct max77686_clk_init_data {
0042     struct regmap *regmap;
0043     struct clk_hw hw;
0044     struct clk_init_data clk_idata;
0045     const struct max77686_hw_clk_info *clk_info;
0046 };
0047
0048 struct max77686_clk_driver_data {
0049     enum max77686_chip_name chip;
0050     struct max77686_clk_init_data *max_clk_data;
0051     size_t num_clks;
0052 };
0053
0054 static const struct
0055 max77686_hw_clk_info max77686_hw_clks_info[MAX77686_CLKS_NUM] = {
0056     [MAX77686_CLK_AP] = {
0057         .name = "32khz_ap",
0058         .clk_reg = MAX77686_REG_32KHZ,
0059         .clk_enable_mask = BIT(MAX77686_CLK_AP),
0060     },
0061     [MAX77686_CLK_CP] = {
0062         .name = "32khz_cp",
0063         .clk_reg = MAX77686_REG_32KHZ,
0064         .clk_enable_mask = BIT(MAX77686_CLK_CP),
0065     },
0066     [MAX77686_CLK_PMIC] = {
0067         .name = "32khz_pmic",
0068         .clk_reg = MAX77686_REG_32KHZ,
0069         .clk_enable_mask = BIT(MAX77686_CLK_PMIC),
0070     },
0071 };
0072
0073 static const struct
0074 max77686_hw_clk_info max77802_hw_clks_info[MAX77802_CLKS_NUM] = {
0075     [MAX77802_CLK_32K_AP] = {
0076         .name = "32khz_ap",
0077         .clk_reg = MAX77802_REG_32KHZ,
0078         .clk_enable_mask = BIT(MAX77802_CLK_32K_AP),
0079     },
0080     [MAX77802_CLK_32K_CP] = {
0081         .name = "32khz_cp",
0082         .clk_reg = MAX77802_REG_32KHZ,
0083         .clk_enable_mask = BIT(MAX77802_CLK_32K_CP),
0084     },
0085 };
0086
0087 static const struct
0088 max77686_hw_clk_info max77620_hw_clks_info[MAX77620_CLKS_NUM] = {
0089     [MAX77620_CLK_32K_OUT0] = {
0090         .name = "32khz_out0",
0091         .clk_reg = MAX77620_REG_CNFG1_32K,
0092         .clk_enable_mask = MAX77620_CNFG1_32K_OUT0_EN,
0093     },
0094 };
0095
0096 static struct max77686_clk_init_data *to_max77686_clk_init_data(
0097                 struct clk_hw *hw)
0098 {
0099     return container_of(hw, struct max77686_clk_init_data, hw);
0100 }
0101
0102 static int max77686_clk_prepare(struct clk_hw *hw)
0103 {
0104     struct max77686_clk_init_data *max77686 = to_max77686_clk_init_data(hw);
0105
0106     return regmap_update_bits(max77686->regmap, max77686->clk_info->clk_reg,
0107                   max77686->clk_info->clk_enable_mask,
0108                   max77686->clk_info->clk_enable_mask);
0109 }
0110
0111 static void max77686_clk_unprepare(struct clk_hw *hw)
0112 {
0113     struct max77686_clk_init_data *max77686 = to_max77686_clk_init_data(hw);
0114
0115     regmap_update_bits(max77686->regmap, max77686->clk_info->clk_reg,
0116                max77686->clk_info->clk_enable_mask,
0117                ~max77686->clk_info->clk_enable_mask);
0118 }
0119
0120 static int max77686_clk_is_prepared(struct clk_hw *hw)
0121 {
0122     struct max77686_clk_init_data *max77686 = to_max77686_clk_init_data(hw);
0123     int ret;
0124     u32 val;
0125
0126     ret = regmap_read(max77686->regmap, max77686->clk_info->clk_reg, &val);
0127
0128     if (ret < 0)
0129         return -EINVAL;
0130
0131     return val & max77686->clk_info->clk_enable_mask;
0132 }
0133
0134 static unsigned long max77686_recalc_rate(struct clk_hw *hw,
0135                       unsigned long parent_rate)
0136 {
0137     return 32768;
0138 }
0139
0140 static const struct clk_ops max77686_clk_ops = {
0141     .prepare    = max77686_clk_prepare,
0142     .unprepare  = max77686_clk_unprepare,
0143     .is_prepared    = max77686_clk_is_prepared,
0144     .recalc_rate    = max77686_recalc_rate,
0145 };
0146
0147 static struct clk_hw *
0148 of_clk_max77686_get(struct of_phandle_args *clkspec, void *data)
0149 {
0150     struct max77686_clk_driver_data *drv_data = data;
0151     unsigned int idx = clkspec->args[0];
0152
0153     if (idx >= drv_data->num_clks) {
0154         pr_err("%s: invalid index %u\n", __func__, idx);
0155         return ERR_PTR(-EINVAL);
0156     }
0157
0158     return &drv_data->max_clk_data[idx].hw;
0159 }
0160
0161 static int max77686_clk_probe(struct platform_device *pdev)
0162 {
0163     struct device *dev = &pdev->dev;
0164     struct device *parent = dev->parent;
0165     const struct platform_device_id *id = platform_get_device_id(pdev);
0166     struct max77686_clk_driver_data *drv_data;
0167     const struct max77686_hw_clk_info *hw_clks;
0168     struct regmap *regmap;
0169     int i, ret, num_clks;
0170
0171     drv_data = devm_kzalloc(dev, sizeof(*drv_data), GFP_KERNEL);
0172     if (!drv_data)
0173         return -ENOMEM;
0174
0175     regmap = dev_get_regmap(parent, NULL);
0176     if (!regmap) {
0177         dev_err(dev, "Failed to get rtc regmap\n");
0178         return -ENODEV;
0179     }
0180
0181     drv_data->chip = id->driver_data;
0182
0183     switch (drv_data->chip) {
0184     case CHIP_MAX77686:
0185         num_clks = MAX77686_CLKS_NUM;
0186         hw_clks = max77686_hw_clks_info;
0187         break;
0188
0189     case CHIP_MAX77802:
0190         num_clks = MAX77802_CLKS_NUM;
0191         hw_clks = max77802_hw_clks_info;
0192         break;
0193
0194     case CHIP_MAX77620:
0195         num_clks = MAX77620_CLKS_NUM;
0196         hw_clks = max77620_hw_clks_info;
0197         break;
0198
0199     default:
0200         dev_err(dev, "Unknown Chip ID\n");
0201         return -EINVAL;
0202     }
0203
0204     drv_data->num_clks = num_clks;
0205     drv_data->max_clk_data = devm_kcalloc(dev, num_clks,
0206                           sizeof(*drv_data->max_clk_data),
0207                           GFP_KERNEL);
0208     if (!drv_data->max_clk_data)
0209         return -ENOMEM;
0210
0211     for (i = 0; i < num_clks; i++) {
0212         struct max77686_clk_init_data *max_clk_data;
0213         const char *clk_name;
0214
0215         max_clk_data = &drv_data->max_clk_data[i];
0216
0217         max_clk_data->regmap = regmap;
0218         max_clk_data->clk_info = &hw_clks[i];
0219         max_clk_data->clk_idata.flags = hw_clks[i].flags;
0220         max_clk_data->clk_idata.ops = &max77686_clk_ops;
0221
0222         if (parent->of_node &&
0223             !of_property_read_string_index(parent->of_node,
0224                            "clock-output-names",
0225                            i, &clk_name))
0226             max_clk_data->clk_idata.name = clk_name;
0227         else
0228             max_clk_data->clk_idata.name = hw_clks[i].name;
0229
0230         max_clk_data->hw.init = &max_clk_data->clk_idata;
0231
0232         ret = devm_clk_hw_register(dev, &max_clk_data->hw);
0233         if (ret) {
0234             dev_err(dev, "Failed to clock register: %d\n", ret);
0235             return ret;
0236         }
0237
0238         ret = devm_clk_hw_register_clkdev(dev, &max_clk_data->hw,
0239                           max_clk_data->clk_idata.name,
0240                           NULL);
0241         if (ret < 0) {
0242             dev_err(dev, "Failed to clkdev register: %d\n", ret);
0243             return ret;
0244         }
0245     }
0246
0247     if (parent->of_node) {
0248         ret = devm_of_clk_add_hw_provider(dev, of_clk_max77686_get,
0249                           drv_data);
0250
0251         if (ret < 0) {
0252             dev_err(dev, "Failed to register OF clock provider: %d\n",
0253                 ret);
0254             return ret;
0255         }
0256     }
0257
0258     /* MAX77802: Enable low-jitter mode on the 32khz clocks. */
0259     if (drv_data->chip == CHIP_MAX77802) {
0260         ret = regmap_update_bits(regmap, MAX77802_REG_32KHZ,
0261                      1 << MAX77802_CLOCK_LOW_JITTER_SHIFT,
0262                      1 << MAX77802_CLOCK_LOW_JITTER_SHIFT);
0263         if (ret < 0) {
0264             dev_err(dev, "Failed to config low-jitter: %d\n", ret);
0265             return ret;
0266         }
0267     }
0268
0269     return 0;
0270 }
0271
0272 static const struct platform_device_id max77686_clk_id[] = {
0273     { "max77686-clk", .driver_data = CHIP_MAX77686, },
0274     { "max77802-clk", .driver_data = CHIP_MAX77802, },
0275     { "max77620-clock", .driver_data = CHIP_MAX77620, },
0276     {},
0277 };
0278 MODULE_DEVICE_TABLE(platform, max77686_clk_id);
0279
0280 static struct platform_driver max77686_clk_driver = {
0281     .driver = {
0282         .name  = "max77686-clk",
0283     },
0284     .probe = max77686_clk_probe,
0285     .id_table = max77686_clk_id,
0286 };
0287
0288 module_platform_driver(max77686_clk_driver);
0289
0290 MODULE_DESCRIPTION("MAXIM 77686 Clock Driver");
0291 MODULE_AUTHOR("Jonghwa Lee <jonghwa3.lee@samsung.com>");
0292 MODULE_LICENSE("GPL");