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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * LMK04832 Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner
0004  * Pin compatible with the LMK0482x family
0005  *
0006  * Datasheet: https://www.ti.com/lit/ds/symlink/lmk04832.pdf
0007  *
0008  * Copyright (c) 2020, Xiphos Systems Corp.
0009  *
0010  */
0011 
0012 #include <linux/bitfield.h>
0013 #include <linux/clk.h>
0014 #include <linux/clk-provider.h>
0015 #include <linux/debugfs.h>
0016 #include <linux/device.h>
0017 #include <linux/gcd.h>
0018 #include <linux/gpio/consumer.h>
0019 #include <linux/module.h>
0020 #include <linux/uaccess.h>
0021 #include <linux/regmap.h>
0022 #include <linux/spi/spi.h>
0023 
0024 /* 0x000 - 0x00d System Functions */
0025 #define LMK04832_REG_RST3W      0x000
0026 #define LMK04832_BIT_RESET          BIT(7)
0027 #define LMK04832_BIT_SPI_3WIRE_DIS      BIT(4)
0028 #define LMK04832_REG_POWERDOWN      0x002
0029 #define LMK04832_REG_ID_DEV_TYPE    0x003
0030 #define LMK04832_REG_ID_PROD_MSB    0x004
0031 #define LMK04832_REG_ID_PROD_LSB    0x005
0032 #define LMK04832_REG_ID_MASKREV     0x006
0033 #define LMK04832_REG_ID_VNDR_MSB    0x00c
0034 #define LMK04832_REG_ID_VNDR_LSB    0x00d
0035 
0036 /* 0x100 - 0x137 Device Clock and SYSREF Clock Output Control */
0037 #define LMK04832_REG_CLKOUT_CTRL0(ch)   (0x100 + (ch >> 1) * 8)
0038 #define LMK04832_BIT_DCLK_DIV_LSB       GENMASK(7, 0)
0039 #define LMK04832_REG_CLKOUT_CTRL1(ch)   (0x101 + (ch >> 1) * 8)
0040 #define LMK04832_BIT_DCLKX_Y_DDLY_LSB       GENMASK(7, 0)
0041 #define LMK04832_REG_CLKOUT_CTRL2(ch)   (0x102 + (ch >> 1) * 8)
0042 #define LMK04832_BIT_CLKOUTX_Y_PD       BIT(7)
0043 #define LMK04832_BIT_DCLKX_Y_DDLY_PD        BIT(4)
0044 #define LMK04832_BIT_DCLKX_Y_DDLY_MSB       GENMASK(3, 2)
0045 #define LMK04832_BIT_DCLK_DIV_MSB       GENMASK(1, 0)
0046 #define LMK04832_REG_CLKOUT_SRC_MUX(ch) (0x103 + (ch % 2) + (ch >> 1) * 8)
0047 #define LMK04832_BIT_CLKOUT_SRC_MUX     BIT(5)
0048 #define LMK04832_REG_CLKOUT_CTRL3(ch)   (0x103 + (ch >> 1) * 8)
0049 #define LMK04832_BIT_DCLKX_Y_PD         BIT(4)
0050 #define LMK04832_BIT_DCLKX_Y_DCC        BIT(2)
0051 #define LMK04832_BIT_DCLKX_Y_HS         BIT(0)
0052 #define LMK04832_REG_CLKOUT_CTRL4(ch)   (0x104 + (ch >> 1) * 8)
0053 #define LMK04832_BIT_SCLK_PD            BIT(4)
0054 #define LMK04832_BIT_SCLKX_Y_DIS_MODE       GENMASK(3, 2)
0055 #define LMK04832_REG_SCLKX_Y_ADLY(ch)   (0x105 + (ch >> 1) * 8)
0056 #define LMK04832_REG_SCLKX_Y_DDLY(ch)   (0x106 + (ch >> 1) * 8)
0057 #define LMK04832_BIT_SCLKX_Y_DDLY       GENMASK(3, 0)
0058 #define LMK04832_REG_CLKOUT_FMT(ch) (0x107 + (ch >> 1) * 8)
0059 #define LMK04832_BIT_CLKOUT_FMT(ch)     (ch % 2 ? 0xf0 : 0x0f)
0060 #define LMK04832_VAL_CLKOUT_FMT_POWERDOWN       0x00
0061 #define LMK04832_VAL_CLKOUT_FMT_LVDS            0x01
0062 #define LMK04832_VAL_CLKOUT_FMT_HSDS6           0x02
0063 #define LMK04832_VAL_CLKOUT_FMT_HSDS8           0x03
0064 #define LMK04832_VAL_CLKOUT_FMT_LVPECL1600      0x04
0065 #define LMK04832_VAL_CLKOUT_FMT_LVPECL2000      0x05
0066 #define LMK04832_VAL_CLKOUT_FMT_LCPECL          0x06
0067 #define LMK04832_VAL_CLKOUT_FMT_CML16           0x07
0068 #define LMK04832_VAL_CLKOUT_FMT_CML24           0x08
0069 #define LMK04832_VAL_CLKOUT_FMT_CML32           0x09
0070 #define LMK04832_VAL_CLKOUT_FMT_CMOS_OFF_INV        0x0a
0071 #define LMK04832_VAL_CLKOUT_FMT_CMOS_NOR_OFF        0x0b
0072 #define LMK04832_VAL_CLKOUT_FMT_CMOS_INV_INV        0x0c
0073 #define LMK04832_VAL_CLKOUT_FMT_CMOS_INV_NOR        0x0d
0074 #define LMK04832_VAL_CLKOUT_FMT_CMOS_NOR_INV        0x0e
0075 #define LMK04832_VAL_CLKOUT_FMT_CMOS_NOR_NOR        0x0f
0076 
0077 /* 0x138 - 0x145 SYSREF, SYNC, and Device Config */
0078 #define LMK04832_REG_VCO_OSCOUT     0x138
0079 #define LMK04832_BIT_VCO_MUX            GENMASK(6, 5)
0080 #define LMK04832_VAL_VCO_MUX_VCO0           0x00
0081 #define LMK04832_VAL_VCO_MUX_VCO1           0x01
0082 #define LMK04832_VAL_VCO_MUX_EXT            0x02
0083 #define LMK04832_REG_SYSREF_OUT     0x139
0084 #define LMK04832_BIT_SYSREF_REQ_EN      BIT(6)
0085 #define LMK04832_BIT_SYSREF_MUX         GENMASK(1, 0)
0086 #define LMK04832_VAL_SYSREF_MUX_NORMAL_SYNC     0x00
0087 #define LMK04832_VAL_SYSREF_MUX_RECLK           0x01
0088 #define LMK04832_VAL_SYSREF_MUX_PULSER          0x02
0089 #define LMK04832_VAL_SYSREF_MUX_CONTINUOUS      0x03
0090 #define LMK04832_REG_SYSREF_DIV_MSB 0x13a
0091 #define LMK04832_BIT_SYSREF_DIV_MSB     GENMASK(4, 0)
0092 #define LMK04832_REG_SYSREF_DIV_LSB 0x13b
0093 #define LMK04832_REG_SYSREF_DDLY_MSB    0x13c
0094 #define LMK04832_BIT_SYSREF_DDLY_MSB        GENMASK(4, 0)
0095 #define LMK04832_REG_SYSREF_DDLY_LSB    0x13d
0096 #define LMK04832_REG_SYSREF_PULSE_CNT   0x13e
0097 #define LMK04832_REG_FB_CTRL        0x13f
0098 #define LMK04832_BIT_PLL2_RCLK_MUX      BIT(7)
0099 #define LMK04832_VAL_PLL2_RCLK_MUX_OSCIN        0x00
0100 #define LMK04832_VAL_PLL2_RCLK_MUX_CLKIN        0x01
0101 #define LMK04832_BIT_PLL2_NCLK_MUX      BIT(5)
0102 #define LMK04832_VAL_PLL2_NCLK_MUX_PLL2_P       0x00
0103 #define LMK04832_VAL_PLL2_NCLK_MUX_FB_MUX       0x01
0104 #define LMK04832_BIT_FB_MUX_EN          BIT(0)
0105 #define LMK04832_REG_MAIN_PD        0x140
0106 #define LMK04832_BIT_PLL1_PD            BIT(7)
0107 #define LMK04832_BIT_VCO_LDO_PD         BIT(6)
0108 #define LMK04832_BIT_VCO_PD         BIT(5)
0109 #define LMK04832_BIT_OSCIN_PD           BIT(4)
0110 #define LMK04832_BIT_SYSREF_GBL_PD      BIT(3)
0111 #define LMK04832_BIT_SYSREF_PD          BIT(2)
0112 #define LMK04832_BIT_SYSREF_DDLY_PD     BIT(1)
0113 #define LMK04832_BIT_SYSREF_PLSR_PD     BIT(0)
0114 #define LMK04832_REG_SYNC       0x143
0115 #define LMK04832_BIT_SYNC_CLR           BIT(7)
0116 #define LMK04832_BIT_SYNC_1SHOT_EN      BIT(6)
0117 #define LMK04832_BIT_SYNC_POL           BIT(5)
0118 #define LMK04832_BIT_SYNC_EN            BIT(4)
0119 #define LMK04832_BIT_SYNC_MODE          GENMASK(1, 0)
0120 #define LMK04832_VAL_SYNC_MODE_OFF          0x00
0121 #define LMK04832_VAL_SYNC_MODE_ON           0x01
0122 #define LMK04832_VAL_SYNC_MODE_PULSER_PIN       0x02
0123 #define LMK04832_VAL_SYNC_MODE_PULSER_SPI       0x03
0124 #define LMK04832_REG_SYNC_DIS       0x144
0125 
0126 /* 0x146 - 0x14a CLKin Control */
0127 #define LMK04832_REG_CLKIN_SEL0     0x148
0128 #define LMK04832_REG_CLKIN_SEL1     0x149
0129 #define LMK04832_REG_CLKIN_RST      0x14a
0130 #define LMK04832_BIT_SDIO_RDBK_TYPE     BIT(6)
0131 #define LMK04832_BIT_CLKIN_SEL_MUX      GENMASK(5, 3)
0132 #define LMK04832_VAL_CLKIN_SEL_MUX_SPI_RDBK     0x06
0133 #define LMK04832_BIT_CLKIN_SEL_TYPE     GENMASK(2, 0)
0134 #define LMK04832_VAL_CLKIN_SEL_TYPE_OUT         0x03
0135 
0136 /* 0x14b - 0x152 Holdover */
0137 
0138 /* 0x153 - 0x15f PLL1 Configuration */
0139 
0140 /* 0x160 - 0x16e PLL2 Configuration */
0141 #define LMK04832_REG_PLL2_R_MSB     0x160
0142 #define LMK04832_BIT_PLL2_R_MSB         GENMASK(3, 0)
0143 #define LMK04832_REG_PLL2_R_LSB     0x161
0144 #define LMK04832_REG_PLL2_MISC      0x162
0145 #define LMK04832_BIT_PLL2_MISC_P        GENMASK(7, 5)
0146 #define LMK04832_BIT_PLL2_MISC_REF_2X_EN    BIT(0)
0147 #define LMK04832_REG_PLL2_N_CAL_0   0x163
0148 #define LMK04832_BIT_PLL2_N_CAL_0       GENMASK(1, 0)
0149 #define LMK04832_REG_PLL2_N_CAL_1   0x164
0150 #define LMK04832_REG_PLL2_N_CAL_2   0x165
0151 #define LMK04832_REG_PLL2_N_0       0x166
0152 #define LMK04832_BIT_PLL2_N_0           GENMASK(1, 0)
0153 #define LMK04832_REG_PLL2_N_1       0x167
0154 #define LMK04832_REG_PLL2_N_2       0x168
0155 #define LMK04832_REG_PLL2_DLD_CNT_MSB   0x16a
0156 #define LMK04832_REG_PLL2_DLD_CNT_LSB   0x16b
0157 #define LMK04832_REG_PLL2_LD        0x16e
0158 #define LMK04832_BIT_PLL2_LD_MUX        GENMASK(7, 3)
0159 #define LMK04832_VAL_PLL2_LD_MUX_PLL2_DLD       0x02
0160 #define LMK04832_BIT_PLL2_LD_TYPE       GENMASK(2, 0)
0161 #define LMK04832_VAL_PLL2_LD_TYPE_OUT_PP        0x03
0162 
0163 /* 0x16F - 0x555 Misc Registers */
0164 #define LMK04832_REG_PLL2_PD        0x173
0165 #define LMK04832_BIT_PLL2_PRE_PD        BIT(6)
0166 #define LMK04832_BIT_PLL2_PD            BIT(5)
0167 #define LMK04832_REG_PLL1R_RST      0x177
0168 #define LMK04832_REG_CLR_PLL_LOST   0x182
0169 #define LMK04832_REG_RB_PLL_LD      0x183
0170 #define LMK04832_REG_RB_CLK_DAC_VAL_MSB 0x184
0171 #define LMK04832_REG_RB_DAC_VAL_LSB 0x185
0172 #define LMK04832_REG_RB_HOLDOVER    0x188
0173 #define LMK04832_REG_SPI_LOCK       0x555
0174 
0175 enum lmk04832_device_types {
0176     LMK04832,
0177 };
0178 
0179 /**
0180  * lmk04832_device_info - Holds static device information that is specific to
0181  *                        the chip revision
0182  *
0183  * pid:          Product Identifier
0184  * maskrev:      IC version identifier
0185  * num_channels: Number of available output channels (clkout count)
0186  * vco0_range:   {min, max} of the VCO0 operating range (in MHz)
0187  * vco1_range:   {min, max} of the VCO1 operating range (in MHz)
0188  */
0189 struct lmk04832_device_info {
0190     u16 pid;
0191     u8 maskrev;
0192     size_t num_channels;
0193     unsigned int vco0_range[2];
0194     unsigned int vco1_range[2];
0195 };
0196 
0197 static const struct lmk04832_device_info lmk04832_device_info[] = {
0198     [LMK04832] = {
0199         .pid = 0x63d1, /* WARNING PROD_ID is inverted in the datasheet */
0200         .maskrev = 0x70,
0201         .num_channels = 14,
0202         .vco0_range = { 2440, 2580 },
0203         .vco1_range = { 2945, 3255 },
0204     },
0205 };
0206 
0207 enum lmk04832_rdbk_type {
0208     RDBK_CLKIN_SEL0,
0209     RDBK_CLKIN_SEL1,
0210     RDBK_RESET,
0211 };
0212 
0213 struct lmk_dclk {
0214     struct lmk04832 *lmk;
0215     struct clk_hw hw;
0216     u8 id;
0217 };
0218 
0219 struct lmk_clkout {
0220     struct lmk04832 *lmk;
0221     struct clk_hw hw;
0222     bool sysref;
0223     u32 format;
0224     u8 id;
0225 };
0226 
0227 /**
0228  * struct lmk04832 - The LMK04832 device structure
0229  *
0230  * @dev: reference to a struct device, linked to the spi_device
0231  * @regmap: struct regmap instance use to access the chip
0232  * @sync_mode: operational mode for SYNC signal
0233  * @sysref_mux: select SYSREF source
0234  * @sysref_pulse_cnt: number of SYSREF pulses generated while not in continuous
0235  *                    mode.
0236  * @sysref_ddly: SYSREF digital delay value
0237  * @oscin: PLL2 input clock
0238  * @vco: reference to the internal VCO clock
0239  * @sclk: reference to the internal sysref clock (SCLK)
0240  * @vco_rate: user provided VCO rate
0241  * @reset_gpio: reference to the reset GPIO
0242  * @dclk: list of internal device clock references.
0243  *        Each pair of clkout clocks share a single device clock (DCLKX_Y)
0244  * @clkout: list of output clock references
0245  * @clk_data: holds clkout related data like clk_hw* and number of clocks
0246  */
0247 struct lmk04832 {
0248     struct device *dev;
0249     struct regmap *regmap;
0250 
0251     unsigned int sync_mode;
0252     unsigned int sysref_mux;
0253     unsigned int sysref_pulse_cnt;
0254     unsigned int sysref_ddly;
0255 
0256     struct clk *oscin;
0257     struct clk_hw vco;
0258     struct clk_hw sclk;
0259     unsigned int vco_rate;
0260 
0261     struct gpio_desc *reset_gpio;
0262 
0263     struct lmk_dclk *dclk;
0264     struct lmk_clkout *clkout;
0265     struct clk_hw_onecell_data *clk_data;
0266 };
0267 
0268 static bool lmk04832_regmap_rd_regs(struct device *dev, unsigned int reg)
0269 {
0270     switch (reg) {
0271     case LMK04832_REG_RST3W ... LMK04832_REG_ID_MASKREV:
0272     case LMK04832_REG_ID_VNDR_MSB:
0273     case LMK04832_REG_ID_VNDR_LSB:
0274     case LMK04832_REG_CLKOUT_CTRL0(0) ... LMK04832_REG_PLL2_DLD_CNT_LSB:
0275     case LMK04832_REG_PLL2_LD:
0276     case LMK04832_REG_PLL2_PD:
0277     case LMK04832_REG_PLL1R_RST:
0278     case LMK04832_REG_CLR_PLL_LOST ... LMK04832_REG_RB_DAC_VAL_LSB:
0279     case LMK04832_REG_RB_HOLDOVER:
0280     case LMK04832_REG_SPI_LOCK:
0281         return true;
0282     default:
0283         return false;
0284     };
0285 };
0286 
0287 static bool lmk04832_regmap_wr_regs(struct device *dev, unsigned int reg)
0288 {
0289     switch (reg) {
0290     case LMK04832_REG_RST3W:
0291     case LMK04832_REG_POWERDOWN:
0292         return true;
0293     case LMK04832_REG_ID_DEV_TYPE ... LMK04832_REG_ID_MASKREV:
0294     case LMK04832_REG_ID_VNDR_MSB:
0295     case LMK04832_REG_ID_VNDR_LSB:
0296         return false;
0297     case LMK04832_REG_CLKOUT_CTRL0(0) ... LMK04832_REG_PLL2_DLD_CNT_LSB:
0298     case LMK04832_REG_PLL2_LD:
0299     case LMK04832_REG_PLL2_PD:
0300     case LMK04832_REG_PLL1R_RST:
0301     case LMK04832_REG_CLR_PLL_LOST ... LMK04832_REG_RB_DAC_VAL_LSB:
0302     case LMK04832_REG_RB_HOLDOVER:
0303     case LMK04832_REG_SPI_LOCK:
0304         return true;
0305     default:
0306         return false;
0307     };
0308 };
0309 
0310 static const struct regmap_config regmap_config = {
0311     .name = "lmk04832",
0312     .reg_bits = 16,
0313     .val_bits = 8,
0314     .use_single_read = 1,
0315     .use_single_write = 1,
0316     .read_flag_mask = 0x80,
0317     .write_flag_mask = 0x00,
0318     .readable_reg = lmk04832_regmap_rd_regs,
0319     .writeable_reg = lmk04832_regmap_wr_regs,
0320     .cache_type = REGCACHE_NONE,
0321     .max_register = LMK04832_REG_SPI_LOCK,
0322 };
0323 
0324 static int lmk04832_vco_is_enabled(struct clk_hw *hw)
0325 {
0326     struct lmk04832 *lmk = container_of(hw, struct lmk04832, vco);
0327     unsigned int tmp;
0328     int ret;
0329 
0330     ret = regmap_read(lmk->regmap, LMK04832_REG_MAIN_PD, &tmp);
0331     if (ret)
0332         return ret;
0333 
0334     return !(FIELD_GET(LMK04832_BIT_OSCIN_PD, tmp) |
0335          FIELD_GET(LMK04832_BIT_VCO_PD, tmp) |
0336          FIELD_GET(LMK04832_BIT_VCO_LDO_PD, tmp));
0337 }
0338 
0339 static int lmk04832_vco_prepare(struct clk_hw *hw)
0340 {
0341     struct lmk04832 *lmk = container_of(hw, struct lmk04832, vco);
0342     int ret;
0343 
0344     ret = regmap_update_bits(lmk->regmap, LMK04832_REG_PLL2_PD,
0345                  LMK04832_BIT_PLL2_PRE_PD |
0346                  LMK04832_BIT_PLL2_PD,
0347                  0x00);
0348     if (ret)
0349         return ret;
0350 
0351     return regmap_update_bits(lmk->regmap, LMK04832_REG_MAIN_PD,
0352                   LMK04832_BIT_VCO_LDO_PD |
0353                   LMK04832_BIT_VCO_PD |
0354                   LMK04832_BIT_OSCIN_PD, 0x00);
0355 }
0356 
0357 static void lmk04832_vco_unprepare(struct clk_hw *hw)
0358 {
0359     struct lmk04832 *lmk = container_of(hw, struct lmk04832, vco);
0360 
0361     regmap_update_bits(lmk->regmap, LMK04832_REG_PLL2_PD,
0362                LMK04832_BIT_PLL2_PRE_PD | LMK04832_BIT_PLL2_PD,
0363                0xff);
0364 
0365     /* Don't set LMK04832_BIT_OSCIN_PD since other clocks depend on it */
0366     regmap_update_bits(lmk->regmap, LMK04832_REG_MAIN_PD,
0367                LMK04832_BIT_VCO_LDO_PD | LMK04832_BIT_VCO_PD, 0xff);
0368 }
0369 
0370 static unsigned long lmk04832_vco_recalc_rate(struct clk_hw *hw,
0371                           unsigned long prate)
0372 {
0373     struct lmk04832 *lmk = container_of(hw, struct lmk04832, vco);
0374     unsigned int pll2_p[] = {8, 2, 2, 3, 4, 5, 6, 7};
0375     unsigned int pll2_n, p, pll2_r;
0376     unsigned int pll2_misc;
0377     unsigned long vco_rate;
0378     u8 tmp[3];
0379     int ret;
0380 
0381     ret = regmap_read(lmk->regmap, LMK04832_REG_PLL2_MISC, &pll2_misc);
0382     if (ret)
0383         return ret;
0384 
0385     p = FIELD_GET(LMK04832_BIT_PLL2_MISC_P, pll2_misc);
0386 
0387     ret = regmap_bulk_read(lmk->regmap, LMK04832_REG_PLL2_N_0, &tmp, 3);
0388     if (ret)
0389         return ret;
0390 
0391     pll2_n = FIELD_PREP(0x030000, tmp[0]) |
0392          FIELD_PREP(0x00ff00, tmp[1]) |
0393          FIELD_PREP(0x0000ff, tmp[2]);
0394 
0395     ret = regmap_bulk_read(lmk->regmap, LMK04832_REG_PLL2_R_MSB, &tmp, 2);
0396     if (ret)
0397         return ret;
0398 
0399     pll2_r = FIELD_PREP(0x0f00, tmp[0]) |
0400          FIELD_PREP(0x00ff, tmp[1]);
0401 
0402     vco_rate = (prate << FIELD_GET(LMK04832_BIT_PLL2_MISC_REF_2X_EN,
0403                        pll2_misc)) * pll2_n * pll2_p[p] / pll2_r;
0404 
0405     return vco_rate;
0406 };
0407 
0408 /**
0409  * lmk04832_check_vco_ranges - Check requested VCO frequency against VCO ranges
0410  *
0411  * @lmk:   Reference to the lmk device
0412  * @rate:  Desired output rate for the VCO
0413  *
0414  * The LMK04832 has 2 internal VCO, each with independent operating ranges.
0415  * Use the device_info structure to determine which VCO to use based on rate.
0416  *
0417  * Returns VCO_MUX value or negative errno.
0418  */
0419 static int lmk04832_check_vco_ranges(struct lmk04832 *lmk, unsigned long rate)
0420 {
0421     struct spi_device *spi = to_spi_device(lmk->dev);
0422     const struct lmk04832_device_info *info;
0423     unsigned long mhz = rate / 1000000;
0424 
0425     info = &lmk04832_device_info[spi_get_device_id(spi)->driver_data];
0426 
0427     if (mhz >= info->vco0_range[0] && mhz <= info->vco0_range[1])
0428         return LMK04832_VAL_VCO_MUX_VCO0;
0429 
0430     if (mhz >= info->vco1_range[0] && mhz <= info->vco1_range[1])
0431         return LMK04832_VAL_VCO_MUX_VCO1;
0432 
0433     dev_err(lmk->dev, "%lu Hz is out of VCO ranges\n", rate);
0434     return -ERANGE;
0435 }
0436 
0437 /**
0438  * lmk04832_calc_pll2_params - Get PLL2 parameters used to set the VCO frequency
0439  *
0440  * @prate: parent rate to the PLL2, usually OSCin
0441  * @rate:  Desired output rate for the VCO
0442  * @n:     reference to PLL2_N
0443  * @p:     reference to PLL2_P
0444  * @r:     reference to PLL2_R
0445  *
0446  * This functions assumes LMK04832_BIT_PLL2_MISC_REF_2X_EN is set since it is
0447  * recommended in the datasheet because a higher phase detector frequencies
0448  * makes the design of wider loop bandwidth filters possible.
0449  *
0450  * the VCO rate can be calculated using the following expression:
0451  *
0452  *  VCO = OSCin * 2 * PLL2_N * PLL2_P / PLL2_R
0453  *
0454  * Returns vco rate or negative errno.
0455  */
0456 static long lmk04832_calc_pll2_params(unsigned long prate, unsigned long rate,
0457                       unsigned int *n, unsigned int *p,
0458                       unsigned int *r)
0459 {
0460     unsigned int pll2_n, pll2_p, pll2_r;
0461     unsigned long num, div;
0462 
0463     /* Set PLL2_P to a fixed value to simplify optimizations */
0464     pll2_p = 2;
0465 
0466     div = gcd(rate, prate);
0467 
0468     num = DIV_ROUND_CLOSEST(rate, div);
0469     pll2_r = DIV_ROUND_CLOSEST(prate, div);
0470 
0471     if (num > 4) {
0472         pll2_n = num >> 2;
0473     } else {
0474         pll2_r = pll2_r << 2;
0475         pll2_n = num;
0476     }
0477 
0478     if (pll2_n < 1 || pll2_n > 0x03ffff)
0479         return -EINVAL;
0480     if (pll2_r < 1 || pll2_r > 0xfff)
0481         return -EINVAL;
0482 
0483     *n = pll2_n;
0484     *p = pll2_p;
0485     *r = pll2_r;
0486 
0487     return DIV_ROUND_CLOSEST(prate * 2 * pll2_p * pll2_n, pll2_r);
0488 }
0489 
0490 static long lmk04832_vco_round_rate(struct clk_hw *hw, unsigned long rate,
0491                     unsigned long *prate)
0492 {
0493     struct lmk04832 *lmk = container_of(hw, struct lmk04832, vco);
0494     unsigned int n, p, r;
0495     long vco_rate;
0496     int ret;
0497 
0498     ret = lmk04832_check_vco_ranges(lmk, rate);
0499     if (ret < 0)
0500         return ret;
0501 
0502     vco_rate = lmk04832_calc_pll2_params(*prate, rate, &n, &p, &r);
0503     if (vco_rate < 0) {
0504         dev_err(lmk->dev, "PLL2 parameters out of range\n");
0505         return vco_rate;
0506     }
0507 
0508     if (rate != vco_rate)
0509         return -EINVAL;
0510 
0511     return vco_rate;
0512 };
0513 
0514 static int lmk04832_vco_set_rate(struct clk_hw *hw, unsigned long rate,
0515                  unsigned long prate)
0516 {
0517     struct lmk04832 *lmk = container_of(hw, struct lmk04832, vco);
0518     unsigned int n, p, r;
0519     long vco_rate;
0520     int vco_mux;
0521     int ret;
0522 
0523     vco_mux = lmk04832_check_vco_ranges(lmk, rate);
0524     if (vco_mux < 0)
0525         return vco_mux;
0526 
0527     ret = regmap_update_bits(lmk->regmap, LMK04832_REG_VCO_OSCOUT,
0528                  LMK04832_BIT_VCO_MUX,
0529                  FIELD_PREP(LMK04832_BIT_VCO_MUX, vco_mux));
0530     if (ret)
0531         return ret;
0532 
0533     vco_rate = lmk04832_calc_pll2_params(prate, rate, &n, &p, &r);
0534     if (vco_rate < 0) {
0535         dev_err(lmk->dev, "failed to determine PLL2 parameters\n");
0536         return vco_rate;
0537     }
0538 
0539     ret = regmap_update_bits(lmk->regmap, LMK04832_REG_PLL2_R_MSB,
0540                  LMK04832_BIT_PLL2_R_MSB,
0541                  FIELD_GET(0x000700, r));
0542     if (ret)
0543         return ret;
0544 
0545     ret = regmap_write(lmk->regmap, LMK04832_REG_PLL2_R_LSB,
0546                FIELD_GET(0x0000ff, r));
0547     if (ret)
0548         return ret;
0549 
0550     ret = regmap_update_bits(lmk->regmap, LMK04832_REG_PLL2_MISC,
0551                  LMK04832_BIT_PLL2_MISC_P,
0552                  FIELD_PREP(LMK04832_BIT_PLL2_MISC_P, p));
0553     if (ret)
0554         return ret;
0555 
0556     /*
0557      * PLL2_N registers must be programmed after other PLL2 dividers are
0558      * programmed to ensure proper VCO frequency calibration
0559      */
0560     ret = regmap_write(lmk->regmap, LMK04832_REG_PLL2_N_0,
0561                FIELD_GET(0x030000, n));
0562     if (ret)
0563         return ret;
0564     ret = regmap_write(lmk->regmap, LMK04832_REG_PLL2_N_1,
0565                FIELD_GET(0x00ff00, n));
0566     if (ret)
0567         return ret;
0568 
0569     return regmap_write(lmk->regmap, LMK04832_REG_PLL2_N_2,
0570                 FIELD_GET(0x0000ff, n));
0571 };
0572 
0573 static const struct clk_ops lmk04832_vco_ops = {
0574     .is_enabled = lmk04832_vco_is_enabled,
0575     .prepare = lmk04832_vco_prepare,
0576     .unprepare = lmk04832_vco_unprepare,
0577     .recalc_rate = lmk04832_vco_recalc_rate,
0578     .round_rate = lmk04832_vco_round_rate,
0579     .set_rate = lmk04832_vco_set_rate,
0580 };
0581 
0582 /*
0583  * lmk04832_register_vco - Initialize the internal VCO and clock distribution
0584  *                         path in PLL2 single loop mode.
0585  */
0586 static int lmk04832_register_vco(struct lmk04832 *lmk)
0587 {
0588     const char *parent_names[1];
0589     struct clk_init_data init;
0590     int ret;
0591 
0592     init.name = "lmk-vco";
0593     parent_names[0] = __clk_get_name(lmk->oscin);
0594     init.parent_names = parent_names;
0595 
0596     init.ops = &lmk04832_vco_ops;
0597     init.num_parents = 1;
0598 
0599     ret = regmap_update_bits(lmk->regmap, LMK04832_REG_VCO_OSCOUT,
0600                  LMK04832_BIT_VCO_MUX,
0601                  FIELD_PREP(LMK04832_BIT_VCO_MUX,
0602                         LMK04832_VAL_VCO_MUX_VCO1));
0603     if (ret)
0604         return ret;
0605 
0606     ret = regmap_update_bits(lmk->regmap, LMK04832_REG_FB_CTRL,
0607                  LMK04832_BIT_PLL2_RCLK_MUX |
0608                  LMK04832_BIT_PLL2_NCLK_MUX,
0609                  FIELD_PREP(LMK04832_BIT_PLL2_RCLK_MUX,
0610                         LMK04832_VAL_PLL2_RCLK_MUX_OSCIN)|
0611                  FIELD_PREP(LMK04832_BIT_PLL2_NCLK_MUX,
0612                         LMK04832_VAL_PLL2_NCLK_MUX_PLL2_P));
0613     if (ret)
0614         return ret;
0615 
0616     ret = regmap_update_bits(lmk->regmap, LMK04832_REG_PLL2_MISC,
0617                  LMK04832_BIT_PLL2_MISC_REF_2X_EN,
0618                  LMK04832_BIT_PLL2_MISC_REF_2X_EN);
0619     if (ret)
0620         return ret;
0621 
0622     ret = regmap_write(lmk->regmap, LMK04832_REG_PLL2_LD,
0623                FIELD_PREP(LMK04832_BIT_PLL2_LD_MUX,
0624                       LMK04832_VAL_PLL2_LD_MUX_PLL2_DLD) |
0625                FIELD_PREP(LMK04832_BIT_PLL2_LD_TYPE,
0626                       LMK04832_VAL_PLL2_LD_TYPE_OUT_PP));
0627     if (ret)
0628         return ret;
0629 
0630     lmk->vco.init = &init;
0631     return devm_clk_hw_register(lmk->dev, &lmk->vco);
0632 }
0633 
0634 static int lmk04832_clkout_set_ddly(struct lmk04832 *lmk, int id)
0635 {
0636     int dclk_div_adj[] = {0, 0, -2, -2, 0, 3, -1, 0};
0637     unsigned int sclkx_y_ddly = 10;
0638     unsigned int dclkx_y_ddly;
0639     unsigned int dclkx_y_div;
0640     unsigned int sysref_ddly;
0641     unsigned int dclkx_y_hs;
0642     unsigned int lsb, msb;
0643     int ret;
0644 
0645     ret = regmap_update_bits(lmk->regmap,
0646                  LMK04832_REG_CLKOUT_CTRL2(id),
0647                  LMK04832_BIT_DCLKX_Y_DDLY_PD,
0648                  FIELD_PREP(LMK04832_BIT_DCLKX_Y_DDLY_PD, 0));
0649     if (ret)
0650         return ret;
0651 
0652     ret = regmap_read(lmk->regmap, LMK04832_REG_SYSREF_DDLY_LSB, &lsb);
0653     if (ret)
0654         return ret;
0655 
0656     ret = regmap_read(lmk->regmap, LMK04832_REG_SYSREF_DDLY_MSB, &msb);
0657     if (ret)
0658         return ret;
0659 
0660     sysref_ddly = FIELD_GET(LMK04832_BIT_SYSREF_DDLY_MSB, msb) << 8 | lsb;
0661 
0662     ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL0(id), &lsb);
0663     if (ret)
0664         return ret;
0665 
0666     ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL2(id), &msb);
0667     if (ret)
0668         return ret;
0669 
0670     dclkx_y_div = FIELD_GET(LMK04832_BIT_DCLK_DIV_MSB, msb) << 8 | lsb;
0671 
0672     ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL3(id), &lsb);
0673     if (ret)
0674         return ret;
0675 
0676     dclkx_y_hs = FIELD_GET(LMK04832_BIT_DCLKX_Y_HS, lsb);
0677 
0678     dclkx_y_ddly = sysref_ddly + 1 -
0679         dclk_div_adj[dclkx_y_div < 6 ?  dclkx_y_div : 7] -
0680         dclkx_y_hs + sclkx_y_ddly;
0681 
0682     if (dclkx_y_ddly < 7 || dclkx_y_ddly > 0x3fff) {
0683         dev_err(lmk->dev, "DCLKX_Y_DDLY out of range (%d)\n",
0684             dclkx_y_ddly);
0685         return -EINVAL;
0686     }
0687 
0688     ret = regmap_write(lmk->regmap,
0689                LMK04832_REG_SCLKX_Y_DDLY(id),
0690                FIELD_GET(LMK04832_BIT_SCLKX_Y_DDLY, sclkx_y_ddly));
0691     if (ret)
0692         return ret;
0693 
0694     ret = regmap_write(lmk->regmap, LMK04832_REG_CLKOUT_CTRL1(id),
0695                 FIELD_GET(0x00ff, dclkx_y_ddly));
0696     if (ret)
0697         return ret;
0698 
0699     dev_dbg(lmk->dev, "clkout%02u: sysref_ddly=%u, dclkx_y_ddly=%u, "
0700         "dclk_div_adj=%+d, dclkx_y_hs=%u, sclkx_y_ddly=%u\n",
0701         id, sysref_ddly, dclkx_y_ddly,
0702         dclk_div_adj[dclkx_y_div < 6 ? dclkx_y_div : 7],
0703         dclkx_y_hs, sclkx_y_ddly);
0704 
0705     return regmap_update_bits(lmk->regmap, LMK04832_REG_CLKOUT_CTRL2(id),
0706                   LMK04832_BIT_DCLKX_Y_DDLY_MSB,
0707                   FIELD_GET(0x0300, dclkx_y_ddly));
0708 }
0709 
0710 /** lmk04832_sclk_sync - Establish deterministic phase relationship between sclk
0711  *                       and dclk
0712  *
0713  * @lmk: Reference to the lmk device
0714  *
0715  * The synchronization sequence:
0716  * - in the datasheet https://www.ti.com/lit/ds/symlink/lmk04832.pdf, p.31
0717  *   (8.3.3.1 How to enable SYSREF)
0718  * - Ti forum: https://e2e.ti.com/support/clock-and-timing/f/48/t/970972
0719  *
0720  * Returns 0 or negative errno.
0721  */
0722 static int lmk04832_sclk_sync_sequence(struct lmk04832 *lmk)
0723 {
0724     int ret;
0725     int i;
0726 
0727     /* 1. (optional) mute all sysref_outputs during synchronization */
0728     /* 2. Enable and write device clock digital delay to applicable clocks */
0729     ret = regmap_update_bits(lmk->regmap, LMK04832_REG_MAIN_PD,
0730                  LMK04832_BIT_SYSREF_DDLY_PD,
0731                  FIELD_PREP(LMK04832_BIT_SYSREF_DDLY_PD, 0));
0732     if (ret)
0733         return ret;
0734 
0735     for (i = 0; i < lmk->clk_data->num; i += 2) {
0736         ret = lmk04832_clkout_set_ddly(lmk, i);
0737         if (ret)
0738             return ret;
0739     }
0740 
0741     /*
0742      * 3. Configure SYNC_MODE to SYNC_PIN and SYSREF_MUX to Normal SYNC,
0743      *    and clear SYSREF_REQ_EN (see 6.)
0744      */
0745     ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYSREF_OUT,
0746                  LMK04832_BIT_SYSREF_REQ_EN |
0747                  LMK04832_BIT_SYSREF_MUX,
0748                  FIELD_PREP(LMK04832_BIT_SYSREF_REQ_EN, 0) |
0749                  FIELD_PREP(LMK04832_BIT_SYSREF_MUX,
0750                         LMK04832_VAL_SYSREF_MUX_NORMAL_SYNC));
0751     if (ret)
0752         return ret;
0753 
0754     ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYNC,
0755                  LMK04832_BIT_SYNC_MODE,
0756                  FIELD_PREP(LMK04832_BIT_SYNC_MODE,
0757                         LMK04832_VAL_SYNC_MODE_ON));
0758     if (ret)
0759         return ret;
0760 
0761     /* 4. Clear SYNXC_DISx or applicable clocks and clear SYNC_DISSYSREF */
0762     ret = regmap_write(lmk->regmap, LMK04832_REG_SYNC_DIS, 0x00);
0763     if (ret)
0764         return ret;
0765 
0766     /*
0767      * 5. If SCLKX_Y_DDLY != 0, Set SYSREF_CLR=1 for at least 15 clock
0768      *    distribution path cycles (VCO cycles), then back to 0. In
0769      *    PLL2-only use case, this will be complete in less than one SPI
0770      *    transaction. If SYSREF local digital delay is not used, this step
0771      *    can be skipped.
0772      */
0773     ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYNC,
0774                  LMK04832_BIT_SYNC_CLR,
0775                  FIELD_PREP(LMK04832_BIT_SYNC_CLR, 0x01));
0776     if (ret)
0777         return ret;
0778 
0779     ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYNC,
0780                  LMK04832_BIT_SYNC_CLR,
0781                  FIELD_PREP(LMK04832_BIT_SYNC_CLR, 0x00));
0782     if (ret)
0783         return ret;
0784 
0785     /*
0786      * 6. Toggle SYNC_POL state between inverted and not inverted.
0787      *    If you use an external signal on the SYNC pin instead of toggling
0788      *    SYNC_POL, make sure that SYSREF_REQ_EN=0 so that the SYSREF_MUX
0789      *    does not shift into continuous SYSREF mode.
0790      */
0791     ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYNC,
0792                LMK04832_BIT_SYNC_POL,
0793                FIELD_PREP(LMK04832_BIT_SYNC_POL, 0x01));
0794     if (ret)
0795         return ret;
0796 
0797     ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYNC,
0798                LMK04832_BIT_SYNC_POL,
0799                FIELD_PREP(LMK04832_BIT_SYNC_POL, 0x00));
0800     if (ret)
0801         return ret;
0802 
0803     /* 7. Set all SYNC_DISx=1, including SYNC_DISSYSREF */
0804     ret = regmap_write(lmk->regmap, LMK04832_REG_SYNC_DIS, 0xff);
0805     if (ret)
0806         return ret;
0807 
0808     /* 8. Restore state of SYNC_MODE and SYSREF_MUX to desired values */
0809     ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYSREF_OUT,
0810                  LMK04832_BIT_SYSREF_MUX,
0811                  FIELD_PREP(LMK04832_BIT_SYSREF_MUX,
0812                         lmk->sysref_mux));
0813     if (ret)
0814         return ret;
0815 
0816     ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYNC,
0817                  LMK04832_BIT_SYNC_MODE,
0818                  FIELD_PREP(LMK04832_BIT_SYNC_MODE,
0819                         lmk->sync_mode));
0820     if (ret)
0821         return ret;
0822 
0823     /*
0824      * 9. (optional) if SCLKx_y_DIS_MODE was used to mute SYSREF outputs
0825      *    during the SYNC event, restore SCLKx_y_DIS_MODE=0 for active state,
0826      *    or set SYSREF_GBL_PD=0 if SCLKx_y_DIS_MODE is set to a conditional
0827      *    option.
0828      */
0829 
0830     /*
0831      * 10. (optional) To reduce power consumption, after the synchronization
0832      *     event is complete, DCLKx_y_DDLY_PD=1 and SYSREF_DDLY_PD=1 disable the
0833      *     digital delay counters (which are only used immediately after the
0834      *     SYNC pulse to delay the output by some number of VCO counts).
0835      */
0836 
0837     return ret;
0838 }
0839 
0840 static int lmk04832_sclk_is_enabled(struct clk_hw *hw)
0841 {
0842     struct lmk04832 *lmk = container_of(hw, struct lmk04832, sclk);
0843     unsigned int tmp;
0844     int ret;
0845 
0846     ret = regmap_read(lmk->regmap, LMK04832_REG_MAIN_PD, &tmp);
0847     if (ret)
0848         return ret;
0849 
0850     return FIELD_GET(LMK04832_BIT_SYSREF_PD, tmp);
0851 }
0852 
0853 static int lmk04832_sclk_prepare(struct clk_hw *hw)
0854 {
0855     struct lmk04832 *lmk = container_of(hw, struct lmk04832, sclk);
0856 
0857     return regmap_update_bits(lmk->regmap, LMK04832_REG_MAIN_PD,
0858                   LMK04832_BIT_SYSREF_PD, 0x00);
0859 }
0860 
0861 static void lmk04832_sclk_unprepare(struct clk_hw *hw)
0862 {
0863     struct lmk04832 *lmk = container_of(hw, struct lmk04832, sclk);
0864 
0865     regmap_update_bits(lmk->regmap, LMK04832_REG_MAIN_PD,
0866                LMK04832_BIT_SYSREF_PD, LMK04832_BIT_SYSREF_PD);
0867 }
0868 
0869 static unsigned long lmk04832_sclk_recalc_rate(struct clk_hw *hw,
0870                            unsigned long prate)
0871 {
0872     struct lmk04832 *lmk = container_of(hw, struct lmk04832, sclk);
0873     unsigned int sysref_div;
0874     u8 tmp[2];
0875     int ret;
0876 
0877     ret = regmap_bulk_read(lmk->regmap, LMK04832_REG_SYSREF_DIV_MSB, &tmp, 2);
0878     if (ret)
0879         return ret;
0880 
0881     sysref_div = FIELD_GET(LMK04832_BIT_SYSREF_DIV_MSB, tmp[0]) << 8 |
0882         tmp[1];
0883 
0884     return DIV_ROUND_CLOSEST(prate, sysref_div);
0885 }
0886 
0887 static long lmk04832_sclk_round_rate(struct clk_hw *hw, unsigned long rate,
0888                      unsigned long *prate)
0889 {
0890     struct lmk04832 *lmk = container_of(hw, struct lmk04832, sclk);
0891     unsigned long sclk_rate;
0892     unsigned int sysref_div;
0893 
0894     sysref_div = DIV_ROUND_CLOSEST(*prate, rate);
0895     sclk_rate = DIV_ROUND_CLOSEST(*prate, sysref_div);
0896 
0897     if (sysref_div < 0x07 || sysref_div > 0x1fff) {
0898         dev_err(lmk->dev, "SYSREF divider out of range\n");
0899         return -EINVAL;
0900     }
0901 
0902     if (rate != sclk_rate)
0903         return -EINVAL;
0904 
0905     return sclk_rate;
0906 }
0907 
0908 static int lmk04832_sclk_set_rate(struct clk_hw *hw, unsigned long rate,
0909                   unsigned long prate)
0910 {
0911     struct lmk04832 *lmk = container_of(hw, struct lmk04832, sclk);
0912     unsigned int sysref_div;
0913     int ret;
0914 
0915     sysref_div = DIV_ROUND_CLOSEST(prate, rate);
0916 
0917     if (sysref_div < 0x07 || sysref_div > 0x1fff) {
0918         dev_err(lmk->dev, "SYSREF divider out of range\n");
0919         return -EINVAL;
0920     }
0921 
0922     ret = regmap_write(lmk->regmap, LMK04832_REG_SYSREF_DIV_MSB,
0923                FIELD_GET(0x1f00, sysref_div));
0924     if (ret)
0925         return ret;
0926 
0927     ret = regmap_write(lmk->regmap, LMK04832_REG_SYSREF_DIV_LSB,
0928                 FIELD_GET(0x00ff, sysref_div));
0929     if (ret)
0930         return ret;
0931 
0932     ret = lmk04832_sclk_sync_sequence(lmk);
0933     if (ret)
0934         dev_err(lmk->dev, "SYNC sequence failed\n");
0935 
0936     return ret;
0937 }
0938 
0939 static const struct clk_ops lmk04832_sclk_ops = {
0940     .is_enabled = lmk04832_sclk_is_enabled,
0941     .prepare = lmk04832_sclk_prepare,
0942     .unprepare = lmk04832_sclk_unprepare,
0943     .recalc_rate = lmk04832_sclk_recalc_rate,
0944     .round_rate = lmk04832_sclk_round_rate,
0945     .set_rate = lmk04832_sclk_set_rate,
0946 };
0947 
0948 static int lmk04832_register_sclk(struct lmk04832 *lmk)
0949 {
0950     const char *parent_names[1];
0951     struct clk_init_data init;
0952     int ret;
0953 
0954     init.name = "lmk-sclk";
0955     parent_names[0] = clk_hw_get_name(&lmk->vco);
0956     init.parent_names = parent_names;
0957 
0958     init.ops = &lmk04832_sclk_ops;
0959     init.flags = CLK_SET_RATE_PARENT;
0960     init.num_parents = 1;
0961 
0962     ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYSREF_OUT,
0963                  LMK04832_BIT_SYSREF_MUX,
0964                  FIELD_PREP(LMK04832_BIT_SYSREF_MUX,
0965                         lmk->sysref_mux));
0966     if (ret)
0967         return ret;
0968 
0969     ret = regmap_write(lmk->regmap, LMK04832_REG_SYSREF_DDLY_LSB,
0970                FIELD_GET(0x00ff, lmk->sysref_ddly));
0971     if (ret)
0972         return ret;
0973 
0974     ret = regmap_write(lmk->regmap, LMK04832_REG_SYSREF_DDLY_MSB,
0975                FIELD_GET(0x1f00, lmk->sysref_ddly));
0976     if (ret)
0977         return ret;
0978 
0979     ret = regmap_write(lmk->regmap, LMK04832_REG_SYSREF_PULSE_CNT,
0980                ilog2(lmk->sysref_pulse_cnt));
0981     if (ret)
0982         return ret;
0983 
0984     ret = regmap_update_bits(lmk->regmap, LMK04832_REG_MAIN_PD,
0985                  LMK04832_BIT_SYSREF_DDLY_PD |
0986                  LMK04832_BIT_SYSREF_PLSR_PD,
0987                  FIELD_PREP(LMK04832_BIT_SYSREF_DDLY_PD, 0) |
0988                  FIELD_PREP(LMK04832_BIT_SYSREF_PLSR_PD, 0));
0989     if (ret)
0990         return ret;
0991 
0992     ret = regmap_write(lmk->regmap, LMK04832_REG_SYNC,
0993                FIELD_PREP(LMK04832_BIT_SYNC_POL, 0) |
0994                FIELD_PREP(LMK04832_BIT_SYNC_EN, 1) |
0995                FIELD_PREP(LMK04832_BIT_SYNC_MODE, lmk->sync_mode));
0996     if (ret)
0997         return ret;
0998 
0999     ret = regmap_write(lmk->regmap, LMK04832_REG_SYNC_DIS, 0xff);
1000     if (ret)
1001         return ret;
1002 
1003     lmk->sclk.init = &init;
1004     return devm_clk_hw_register(lmk->dev, &lmk->sclk);
1005 }
1006 
1007 static int lmk04832_dclk_is_enabled(struct clk_hw *hw)
1008 {
1009     struct lmk_dclk *dclk = container_of(hw, struct lmk_dclk, hw);
1010     struct lmk04832 *lmk = dclk->lmk;
1011     unsigned int tmp;
1012     int ret;
1013 
1014     ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL3(dclk->id),
1015               &tmp);
1016     if (ret)
1017         return ret;
1018 
1019     return !FIELD_GET(LMK04832_BIT_DCLKX_Y_PD, tmp);
1020 }
1021 
1022 static int lmk04832_dclk_prepare(struct clk_hw *hw)
1023 {
1024     struct lmk_dclk *dclk = container_of(hw, struct lmk_dclk, hw);
1025     struct lmk04832 *lmk = dclk->lmk;
1026 
1027     return regmap_update_bits(lmk->regmap,
1028                   LMK04832_REG_CLKOUT_CTRL3(dclk->id),
1029                   LMK04832_BIT_DCLKX_Y_PD, 0x00);
1030 }
1031 
1032 static void lmk04832_dclk_unprepare(struct clk_hw *hw)
1033 {
1034     struct lmk_dclk *dclk = container_of(hw, struct lmk_dclk, hw);
1035     struct lmk04832 *lmk = dclk->lmk;
1036 
1037     regmap_update_bits(lmk->regmap,
1038                LMK04832_REG_CLKOUT_CTRL3(dclk->id),
1039                LMK04832_BIT_DCLKX_Y_PD, 0xff);
1040 }
1041 
1042 static unsigned long lmk04832_dclk_recalc_rate(struct clk_hw *hw,
1043                            unsigned long prate)
1044 {
1045     struct lmk_dclk *dclk = container_of(hw, struct lmk_dclk, hw);
1046     struct lmk04832 *lmk = dclk->lmk;
1047     unsigned int dclk_div;
1048     unsigned int lsb, msb;
1049     unsigned long rate;
1050     int ret;
1051 
1052     ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL0(dclk->id),
1053               &lsb);
1054     if (ret)
1055         return ret;
1056 
1057     ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL2(dclk->id),
1058               &msb);
1059     if (ret)
1060         return ret;
1061 
1062     dclk_div = FIELD_GET(LMK04832_BIT_DCLK_DIV_MSB, msb) << 8 | lsb;
1063     rate = DIV_ROUND_CLOSEST(prate, dclk_div);
1064 
1065     return rate;
1066 };
1067 
1068 static long lmk04832_dclk_round_rate(struct clk_hw *hw, unsigned long rate,
1069                      unsigned long *prate)
1070 {
1071     struct lmk_dclk *dclk = container_of(hw, struct lmk_dclk, hw);
1072     struct lmk04832 *lmk = dclk->lmk;
1073     unsigned long dclk_rate;
1074     unsigned int dclk_div;
1075 
1076     dclk_div = DIV_ROUND_CLOSEST(*prate, rate);
1077     dclk_rate = DIV_ROUND_CLOSEST(*prate, dclk_div);
1078 
1079     if (dclk_div < 1 || dclk_div > 0x3ff) {
1080         dev_err(lmk->dev, "%s_div out of range\n", clk_hw_get_name(hw));
1081         return -EINVAL;
1082     }
1083 
1084     if (rate != dclk_rate)
1085         return -EINVAL;
1086 
1087     return dclk_rate;
1088 };
1089 
1090 static int lmk04832_dclk_set_rate(struct clk_hw *hw, unsigned long rate,
1091                   unsigned long prate)
1092 {
1093     struct lmk_dclk *dclk = container_of(hw, struct lmk_dclk, hw);
1094     struct lmk04832 *lmk = dclk->lmk;
1095     unsigned int dclk_div;
1096     int ret;
1097 
1098     dclk_div = DIV_ROUND_CLOSEST(prate, rate);
1099 
1100     if (dclk_div > 0x3ff) {
1101         dev_err(lmk->dev, "%s_div out of range\n", clk_hw_get_name(hw));
1102         return -EINVAL;
1103     }
1104 
1105     /* Enable Duty Cycle Correction */
1106     if (dclk_div == 1) {
1107         ret = regmap_update_bits(lmk->regmap,
1108                      LMK04832_REG_CLKOUT_CTRL3(dclk->id),
1109                      LMK04832_BIT_DCLKX_Y_DCC,
1110                      FIELD_PREP(LMK04832_BIT_DCLKX_Y_DCC, 1));
1111         if (ret)
1112             return ret;
1113     }
1114 
1115     /*
1116      * While using Divide-by-2 or Divide-by-3 for DCLK_X_Y_DIV, SYNC
1117      * procedure requires to first program Divide-by-4 and then back to
1118      * Divide-by-2 or Divide-by-3 before doing SYNC.
1119      */
1120     if (dclk_div == 2 || dclk_div == 3) {
1121         ret = regmap_update_bits(lmk->regmap,
1122                      LMK04832_REG_CLKOUT_CTRL2(dclk->id),
1123                      LMK04832_BIT_DCLK_DIV_MSB, 0x00);
1124         if (ret)
1125             return ret;
1126 
1127         ret = regmap_write(lmk->regmap,
1128                    LMK04832_REG_CLKOUT_CTRL0(dclk->id), 0x04);
1129         if (ret)
1130             return ret;
1131     }
1132 
1133     ret = regmap_write(lmk->regmap, LMK04832_REG_CLKOUT_CTRL0(dclk->id),
1134                FIELD_GET(0x0ff, dclk_div));
1135     if (ret)
1136         return ret;
1137 
1138     ret = regmap_update_bits(lmk->regmap,
1139                   LMK04832_REG_CLKOUT_CTRL2(dclk->id),
1140                   LMK04832_BIT_DCLK_DIV_MSB,
1141                   FIELD_GET(0x300, dclk_div));
1142     if (ret)
1143         return ret;
1144 
1145     ret = lmk04832_sclk_sync_sequence(lmk);
1146     if (ret)
1147         dev_err(lmk->dev, "SYNC sequence failed\n");
1148 
1149     return ret;
1150 };
1151 
1152 static const struct clk_ops lmk04832_dclk_ops = {
1153     .is_enabled = lmk04832_dclk_is_enabled,
1154     .prepare = lmk04832_dclk_prepare,
1155     .unprepare = lmk04832_dclk_unprepare,
1156     .recalc_rate = lmk04832_dclk_recalc_rate,
1157     .round_rate = lmk04832_dclk_round_rate,
1158     .set_rate = lmk04832_dclk_set_rate,
1159 };
1160 
1161 static int lmk04832_clkout_is_enabled(struct clk_hw *hw)
1162 {
1163     struct lmk_clkout *clkout = container_of(hw, struct lmk_clkout, hw);
1164     struct lmk04832 *lmk = clkout->lmk;
1165     unsigned int clkoutx_y_pd;
1166     unsigned int sclkx_y_pd;
1167     unsigned int tmp;
1168     u32 enabled;
1169     int ret;
1170     u8 fmt;
1171 
1172     ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL2(clkout->id),
1173               &clkoutx_y_pd);
1174     if (ret)
1175         return ret;
1176 
1177     enabled = !FIELD_GET(LMK04832_BIT_CLKOUTX_Y_PD, clkoutx_y_pd);
1178 
1179     ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_SRC_MUX(clkout->id),
1180               &tmp);
1181     if (ret)
1182         return ret;
1183 
1184     if (FIELD_GET(LMK04832_BIT_CLKOUT_SRC_MUX, tmp)) {
1185         ret = regmap_read(lmk->regmap,
1186                   LMK04832_REG_CLKOUT_CTRL4(clkout->id),
1187                   &sclkx_y_pd);
1188         if (ret)
1189             return ret;
1190 
1191         enabled = enabled && !FIELD_GET(LMK04832_BIT_SCLK_PD, sclkx_y_pd);
1192     }
1193 
1194     ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_FMT(clkout->id),
1195               &tmp);
1196     if (ret)
1197         return ret;
1198 
1199     if (clkout->id % 2)
1200         fmt = FIELD_GET(0xf0, tmp);
1201     else
1202         fmt = FIELD_GET(0x0f, tmp);
1203 
1204     return enabled && !fmt;
1205 }
1206 
1207 static int lmk04832_clkout_prepare(struct clk_hw *hw)
1208 {
1209     struct lmk_clkout *clkout = container_of(hw, struct lmk_clkout, hw);
1210     struct lmk04832 *lmk = clkout->lmk;
1211     unsigned int tmp;
1212     int ret;
1213 
1214     if (clkout->format == LMK04832_VAL_CLKOUT_FMT_POWERDOWN)
1215         dev_err(lmk->dev, "prepared %s but format is powerdown\n",
1216             clk_hw_get_name(hw));
1217 
1218     ret = regmap_update_bits(lmk->regmap,
1219                  LMK04832_REG_CLKOUT_CTRL2(clkout->id),
1220                  LMK04832_BIT_CLKOUTX_Y_PD, 0x00);
1221     if (ret)
1222         return ret;
1223 
1224     ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_SRC_MUX(clkout->id),
1225               &tmp);
1226     if (ret)
1227         return ret;
1228 
1229     if (FIELD_GET(LMK04832_BIT_CLKOUT_SRC_MUX, tmp)) {
1230         ret = regmap_update_bits(lmk->regmap,
1231                      LMK04832_REG_CLKOUT_CTRL4(clkout->id),
1232                      LMK04832_BIT_SCLK_PD, 0x00);
1233         if (ret)
1234             return ret;
1235     }
1236 
1237     return regmap_update_bits(lmk->regmap,
1238                   LMK04832_REG_CLKOUT_FMT(clkout->id),
1239                   LMK04832_BIT_CLKOUT_FMT(clkout->id),
1240                   clkout->format << 4 * (clkout->id % 2));
1241 }
1242 
1243 static void lmk04832_clkout_unprepare(struct clk_hw *hw)
1244 {
1245     struct lmk_clkout *clkout = container_of(hw, struct lmk_clkout, hw);
1246     struct lmk04832 *lmk = clkout->lmk;
1247 
1248     regmap_update_bits(lmk->regmap, LMK04832_REG_CLKOUT_FMT(clkout->id),
1249                LMK04832_BIT_CLKOUT_FMT(clkout->id),
1250                0x00);
1251 }
1252 
1253 static int lmk04832_clkout_set_parent(struct clk_hw *hw, uint8_t index)
1254 {
1255     struct lmk_clkout *clkout = container_of(hw, struct lmk_clkout, hw);
1256     struct lmk04832 *lmk = clkout->lmk;
1257 
1258     return regmap_update_bits(lmk->regmap,
1259                   LMK04832_REG_CLKOUT_SRC_MUX(clkout->id),
1260                   LMK04832_BIT_CLKOUT_SRC_MUX,
1261                   FIELD_PREP(LMK04832_BIT_CLKOUT_SRC_MUX,
1262                          index));
1263 }
1264 
1265 static uint8_t lmk04832_clkout_get_parent(struct clk_hw *hw)
1266 {
1267     struct lmk_clkout *clkout = container_of(hw, struct lmk_clkout, hw);
1268     struct lmk04832 *lmk = clkout->lmk;
1269     unsigned int tmp;
1270     int ret;
1271 
1272     ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_SRC_MUX(clkout->id),
1273               &tmp);
1274     if (ret)
1275         return ret;
1276 
1277     return FIELD_GET(LMK04832_BIT_CLKOUT_SRC_MUX, tmp);
1278 }
1279 
1280 static const struct clk_ops lmk04832_clkout_ops = {
1281     .is_enabled = lmk04832_clkout_is_enabled,
1282     .prepare = lmk04832_clkout_prepare,
1283     .unprepare = lmk04832_clkout_unprepare,
1284     .set_parent = lmk04832_clkout_set_parent,
1285     .get_parent = lmk04832_clkout_get_parent,
1286 };
1287 
1288 static int lmk04832_register_clkout(struct lmk04832 *lmk, const int num)
1289 {
1290     char name[] = "lmk-clkoutXX";
1291     char dclk_name[] = "lmk-dclkXX_YY";
1292     const char *parent_names[2];
1293     struct clk_init_data init;
1294     int dclk_num = num / 2;
1295     int ret;
1296 
1297     if (num % 2 == 0) {
1298         sprintf(dclk_name, "lmk-dclk%02d_%02d", num, num + 1);
1299         init.name = dclk_name;
1300         parent_names[0] = clk_hw_get_name(&lmk->vco);
1301         init.ops = &lmk04832_dclk_ops;
1302         init.flags = CLK_SET_RATE_PARENT;
1303         init.num_parents = 1;
1304 
1305         lmk->dclk[dclk_num].id = num;
1306         lmk->dclk[dclk_num].lmk = lmk;
1307         lmk->dclk[dclk_num].hw.init = &init;
1308 
1309         ret = devm_clk_hw_register(lmk->dev, &lmk->dclk[dclk_num].hw);
1310         if (ret)
1311             return ret;
1312     } else {
1313         sprintf(dclk_name, "lmk-dclk%02d_%02d", num - 1, num);
1314     }
1315 
1316     if (of_property_read_string_index(lmk->dev->of_node,
1317                       "clock-output-names",
1318                       num, &init.name)) {
1319         sprintf(name, "lmk-clkout%02d", num);
1320         init.name = name;
1321     }
1322 
1323     parent_names[0] = dclk_name;
1324     parent_names[1] = clk_hw_get_name(&lmk->sclk);
1325     init.parent_names = parent_names;
1326     init.ops = &lmk04832_clkout_ops;
1327     init.flags = CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT;
1328     init.num_parents = ARRAY_SIZE(parent_names);
1329 
1330     lmk->clkout[num].id = num;
1331     lmk->clkout[num].lmk = lmk;
1332     lmk->clkout[num].hw.init = &init;
1333     lmk->clk_data->hws[num] = &lmk->clkout[num].hw;
1334 
1335     /* Set initial parent */
1336     regmap_update_bits(lmk->regmap,
1337                LMK04832_REG_CLKOUT_SRC_MUX(num),
1338                LMK04832_BIT_CLKOUT_SRC_MUX,
1339                FIELD_PREP(LMK04832_BIT_CLKOUT_SRC_MUX,
1340                       lmk->clkout[num].sysref));
1341 
1342     return devm_clk_hw_register(lmk->dev, &lmk->clkout[num].hw);
1343 }
1344 
1345 static int lmk04832_set_spi_rdbk(const struct lmk04832 *lmk, const int rdbk_pin)
1346 {
1347     int reg;
1348     int ret;
1349 
1350     dev_info(lmk->dev, "setting up 4-wire mode\n");
1351     ret = regmap_write(lmk->regmap, LMK04832_REG_RST3W,
1352                LMK04832_BIT_SPI_3WIRE_DIS);
1353     if (ret)
1354         return ret;
1355 
1356     switch (rdbk_pin) {
1357     case RDBK_CLKIN_SEL0:
1358         reg = LMK04832_REG_CLKIN_SEL0;
1359         break;
1360     case RDBK_CLKIN_SEL1:
1361         reg = LMK04832_REG_CLKIN_SEL1;
1362         break;
1363     case RDBK_RESET:
1364         reg = LMK04832_REG_CLKIN_RST;
1365         break;
1366     default:
1367         return -EINVAL;
1368     }
1369 
1370     return regmap_write(lmk->regmap, reg,
1371                 FIELD_PREP(LMK04832_BIT_CLKIN_SEL_MUX,
1372                        LMK04832_VAL_CLKIN_SEL_MUX_SPI_RDBK) |
1373                 FIELD_PREP(LMK04832_BIT_CLKIN_SEL_TYPE,
1374                        LMK04832_VAL_CLKIN_SEL_TYPE_OUT));
1375 }
1376 
1377 static int lmk04832_probe(struct spi_device *spi)
1378 {
1379     const struct lmk04832_device_info *info;
1380     int rdbk_pin = RDBK_CLKIN_SEL1;
1381     struct device_node *child;
1382     struct lmk04832 *lmk;
1383     u8 tmp[3];
1384     int ret;
1385     int i;
1386 
1387     info = &lmk04832_device_info[spi_get_device_id(spi)->driver_data];
1388 
1389     lmk = devm_kzalloc(&spi->dev, sizeof(struct lmk04832), GFP_KERNEL);
1390     if (!lmk)
1391         return -ENOMEM;
1392 
1393     lmk->dev = &spi->dev;
1394 
1395     lmk->oscin = devm_clk_get(lmk->dev, "oscin");
1396     if (IS_ERR(lmk->oscin)) {
1397         dev_err(lmk->dev, "failed to get oscin clock\n");
1398         return PTR_ERR(lmk->oscin);
1399     }
1400 
1401     ret = clk_prepare_enable(lmk->oscin);
1402     if (ret)
1403         return ret;
1404 
1405     lmk->reset_gpio = devm_gpiod_get_optional(&spi->dev, "reset",
1406                           GPIOD_OUT_LOW);
1407 
1408     lmk->dclk = devm_kcalloc(lmk->dev, info->num_channels >> 1,
1409                  sizeof(struct lmk_dclk), GFP_KERNEL);
1410     if (!lmk->dclk) {
1411         ret = -ENOMEM;
1412         goto err_disable_oscin;
1413     }
1414 
1415     lmk->clkout = devm_kcalloc(lmk->dev, info->num_channels,
1416                    sizeof(*lmk->clkout), GFP_KERNEL);
1417     if (!lmk->clkout) {
1418         ret = -ENOMEM;
1419         goto err_disable_oscin;
1420     }
1421 
1422     lmk->clk_data = devm_kzalloc(lmk->dev, struct_size(lmk->clk_data, hws,
1423                                info->num_channels),
1424                      GFP_KERNEL);
1425     if (!lmk->clk_data) {
1426         ret = -ENOMEM;
1427         goto err_disable_oscin;
1428     }
1429 
1430     device_property_read_u32(lmk->dev, "ti,vco-hz", &lmk->vco_rate);
1431 
1432     lmk->sysref_ddly = 8;
1433     device_property_read_u32(lmk->dev, "ti,sysref-ddly", &lmk->sysref_ddly);
1434 
1435     lmk->sysref_mux = LMK04832_VAL_SYSREF_MUX_CONTINUOUS;
1436     device_property_read_u32(lmk->dev, "ti,sysref-mux",
1437                  &lmk->sysref_mux);
1438 
1439     lmk->sync_mode = LMK04832_VAL_SYNC_MODE_OFF;
1440     device_property_read_u32(lmk->dev, "ti,sync-mode",
1441                  &lmk->sync_mode);
1442 
1443     lmk->sysref_pulse_cnt = 4;
1444     device_property_read_u32(lmk->dev, "ti,sysref-pulse-count",
1445                  &lmk->sysref_pulse_cnt);
1446 
1447     for_each_child_of_node(lmk->dev->of_node, child) {
1448         int reg;
1449 
1450         ret = of_property_read_u32(child, "reg", &reg);
1451         if (ret) {
1452             dev_err(lmk->dev, "missing reg property in child: %s\n",
1453                 child->full_name);
1454             of_node_put(child);
1455             goto err_disable_oscin;
1456         }
1457 
1458         of_property_read_u32(child, "ti,clkout-fmt",
1459                      &lmk->clkout[reg].format);
1460 
1461         if (lmk->clkout[reg].format >= 0x0a && reg % 2 == 0
1462             && reg != 8 && reg != 10)
1463             dev_err(lmk->dev, "invalid format for clkout%02d\n",
1464                 reg);
1465 
1466         lmk->clkout[reg].sysref =
1467             of_property_read_bool(child, "ti,clkout-sysref");
1468     }
1469 
1470     lmk->regmap = devm_regmap_init_spi(spi, &regmap_config);
1471     if (IS_ERR(lmk->regmap)) {
1472         dev_err(lmk->dev, "%s: regmap allocation failed: %ld\n",
1473 
1474             __func__, PTR_ERR(lmk->regmap));
1475         ret = PTR_ERR(lmk->regmap);
1476         goto err_disable_oscin;
1477     }
1478 
1479     regmap_write(lmk->regmap, LMK04832_REG_RST3W, LMK04832_BIT_RESET);
1480 
1481     if (!(spi->mode & SPI_3WIRE)) {
1482         device_property_read_u32(lmk->dev, "ti,spi-4wire-rdbk",
1483                      &rdbk_pin);
1484         ret = lmk04832_set_spi_rdbk(lmk, rdbk_pin);
1485         if (ret)
1486             goto err_disable_oscin;
1487     }
1488 
1489     regmap_bulk_read(lmk->regmap, LMK04832_REG_ID_PROD_MSB, &tmp, 3);
1490     if ((tmp[0] << 8 | tmp[1]) != info->pid || tmp[2] != info->maskrev) {
1491         dev_err(lmk->dev, "unsupported device type: pid 0x%04x, maskrev 0x%02x\n",
1492             tmp[0] << 8 | tmp[1], tmp[2]);
1493         ret = -EINVAL;
1494         goto err_disable_oscin;
1495     }
1496 
1497     ret = lmk04832_register_vco(lmk);
1498     if (ret) {
1499         dev_err(lmk->dev, "failed to init device clock path\n");
1500         goto err_disable_oscin;
1501     }
1502 
1503     if (lmk->vco_rate) {
1504         dev_info(lmk->dev, "setting VCO rate to %u Hz\n", lmk->vco_rate);
1505         ret = clk_set_rate(lmk->vco.clk, lmk->vco_rate);
1506         if (ret) {
1507             dev_err(lmk->dev, "failed to set VCO rate\n");
1508             goto err_disable_vco;
1509         }
1510     }
1511 
1512     ret = lmk04832_register_sclk(lmk);
1513     if (ret) {
1514         dev_err(lmk->dev, "failed to init SYNC/SYSREF clock path\n");
1515         goto err_disable_vco;
1516     }
1517 
1518     for (i = 0; i < info->num_channels; i++) {
1519         ret = lmk04832_register_clkout(lmk, i);
1520         if (ret) {
1521             dev_err(lmk->dev, "failed to register clk %d\n", i);
1522             goto err_disable_vco;
1523         }
1524     }
1525 
1526     lmk->clk_data->num = info->num_channels;
1527     ret = of_clk_add_hw_provider(lmk->dev->of_node, of_clk_hw_onecell_get,
1528                      lmk->clk_data);
1529     if (ret) {
1530         dev_err(lmk->dev, "failed to add provider (%d)\n", ret);
1531         goto err_disable_vco;
1532     }
1533 
1534     spi_set_drvdata(spi, lmk);
1535 
1536     return 0;
1537 
1538 err_disable_vco:
1539     clk_disable_unprepare(lmk->vco.clk);
1540 
1541 err_disable_oscin:
1542     clk_disable_unprepare(lmk->oscin);
1543 
1544     return ret;
1545 }
1546 
1547 static void lmk04832_remove(struct spi_device *spi)
1548 {
1549     struct lmk04832 *lmk = spi_get_drvdata(spi);
1550 
1551     clk_disable_unprepare(lmk->oscin);
1552     of_clk_del_provider(spi->dev.of_node);
1553 }
1554 static const struct spi_device_id lmk04832_id[] = {
1555     { "lmk04832", LMK04832 },
1556     {}
1557 };
1558 MODULE_DEVICE_TABLE(spi, lmk04832_id);
1559 
1560 static const struct of_device_id lmk04832_of_id[] = {
1561     { .compatible = "ti,lmk04832" },
1562     {}
1563 };
1564 MODULE_DEVICE_TABLE(of, lmk04832_of_id);
1565 
1566 static struct spi_driver lmk04832_driver = {
1567     .driver = {
1568         .name   = "lmk04832",
1569         .of_match_table = lmk04832_of_id,
1570     },
1571     .probe      = lmk04832_probe,
1572     .remove     = lmk04832_remove,
1573     .id_table   = lmk04832_id,
1574 };
1575 module_spi_driver(lmk04832_driver);
1576 
1577 MODULE_AUTHOR("Liam Beguin <lvb@xiphos.com>");
1578 MODULE_DESCRIPTION("Texas Instruments LMK04832");
1579 MODULE_LICENSE("GPL v2");
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