drivers/clk/clk-hsdk-pll.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Synopsys HSDK SDP Generic PLL clock driver
0004  *
0005  * Copyright (C) 2017 Synopsys
0006  */
0007
0008 #include <linux/clk-provider.h>
0009 #include <linux/delay.h>
0010 #include <linux/device.h>
0011 #include <linux/err.h>
0012 #include <linux/io.h>
0013 #include <linux/of.h>
0014 #include <linux/of_address.h>
0015 #include <linux/of_device.h>
0016 #include <linux/platform_device.h>
0017 #include <linux/slab.h>
0018
0019 #define CGU_PLL_CTRL    0x000 /* ARC PLL control register */
0020 #define CGU_PLL_STATUS  0x004 /* ARC PLL status register */
0021 #define CGU_PLL_FMEAS   0x008 /* ARC PLL frequency measurement register */
0022 #define CGU_PLL_MON 0x00C /* ARC PLL monitor register */
0023
0024 #define CGU_PLL_CTRL_ODIV_SHIFT     2
0025 #define CGU_PLL_CTRL_IDIV_SHIFT     4
0026 #define CGU_PLL_CTRL_FBDIV_SHIFT    9
0027 #define CGU_PLL_CTRL_BAND_SHIFT     20
0028
0029 #define CGU_PLL_CTRL_ODIV_MASK      GENMASK(3, CGU_PLL_CTRL_ODIV_SHIFT)
0030 #define CGU_PLL_CTRL_IDIV_MASK      GENMASK(8, CGU_PLL_CTRL_IDIV_SHIFT)
0031 #define CGU_PLL_CTRL_FBDIV_MASK     GENMASK(15, CGU_PLL_CTRL_FBDIV_SHIFT)
0032
0033 #define CGU_PLL_CTRL_PD         BIT(0)
0034 #define CGU_PLL_CTRL_BYPASS     BIT(1)
0035
0036 #define CGU_PLL_STATUS_LOCK     BIT(0)
0037 #define CGU_PLL_STATUS_ERR      BIT(1)
0038
0039 #define HSDK_PLL_MAX_LOCK_TIME      100 /* 100 us */
0040
0041 #define CGU_PLL_SOURCE_MAX      1
0042
0043 #define CORE_IF_CLK_THRESHOLD_HZ    500000000
0044 #define CREG_CORE_IF_CLK_DIV_1      0x0
0045 #define CREG_CORE_IF_CLK_DIV_2      0x1
0046
0047 struct hsdk_pll_cfg {
0048     u32 rate;
0049     u32 idiv;
0050     u32 fbdiv;
0051     u32 odiv;
0052     u32 band;
0053     u32 bypass;
0054 };
0055
0056 static const struct hsdk_pll_cfg asdt_pll_cfg[] = {
0057     { 100000000,  0, 11, 3, 0, 0 },
0058     { 133000000,  0, 15, 3, 0, 0 },
0059     { 200000000,  1, 47, 3, 0, 0 },
0060     { 233000000,  1, 27, 2, 0, 0 },
0061     { 300000000,  1, 35, 2, 0, 0 },
0062     { 333000000,  1, 39, 2, 0, 0 },
0063     { 400000000,  1, 47, 2, 0, 0 },
0064     { 500000000,  0, 14, 1, 0, 0 },
0065     { 600000000,  0, 17, 1, 0, 0 },
0066     { 700000000,  0, 20, 1, 0, 0 },
0067     { 800000000,  0, 23, 1, 0, 0 },
0068     { 900000000,  1, 26, 0, 0, 0 },
0069     { 1000000000, 1, 29, 0, 0, 0 },
0070     { 1100000000, 1, 32, 0, 0, 0 },
0071     { 1200000000, 1, 35, 0, 0, 0 },
0072     { 1300000000, 1, 38, 0, 0, 0 },
0073     { 1400000000, 1, 41, 0, 0, 0 },
0074     { 1500000000, 1, 44, 0, 0, 0 },
0075     { 1600000000, 1, 47, 0, 0, 0 },
0076     {}
0077 };
0078
0079 static const struct hsdk_pll_cfg hdmi_pll_cfg[] = {
0080     { 27000000,   0, 0,  0, 0, 1 },
0081     { 148500000,  0, 21, 3, 0, 0 },
0082     { 297000000,  0, 21, 2, 0, 0 },
0083     { 540000000,  0, 19, 1, 0, 0 },
0084     { 594000000,  0, 21, 1, 0, 0 },
0085     {}
0086 };
0087
0088 struct hsdk_pll_clk {
0089     struct clk_hw hw;
0090     void __iomem *regs;
0091     void __iomem *spec_regs;
0092     const struct hsdk_pll_devdata *pll_devdata;
0093     struct device *dev;
0094 };
0095
0096 struct hsdk_pll_devdata {
0097     const struct hsdk_pll_cfg *pll_cfg;
0098     int (*update_rate)(struct hsdk_pll_clk *clk, unsigned long rate,
0099                const struct hsdk_pll_cfg *cfg);
0100 };
0101
0102 static int hsdk_pll_core_update_rate(struct hsdk_pll_clk *, unsigned long,
0103                      const struct hsdk_pll_cfg *);
0104 static int hsdk_pll_comm_update_rate(struct hsdk_pll_clk *, unsigned long,
0105                      const struct hsdk_pll_cfg *);
0106
0107 static const struct hsdk_pll_devdata core_pll_devdata = {
0108     .pll_cfg = asdt_pll_cfg,
0109     .update_rate = hsdk_pll_core_update_rate,
0110 };
0111
0112 static const struct hsdk_pll_devdata sdt_pll_devdata = {
0113     .pll_cfg = asdt_pll_cfg,
0114     .update_rate = hsdk_pll_comm_update_rate,
0115 };
0116
0117 static const struct hsdk_pll_devdata hdmi_pll_devdata = {
0118     .pll_cfg = hdmi_pll_cfg,
0119     .update_rate = hsdk_pll_comm_update_rate,
0120 };
0121
0122 static inline void hsdk_pll_write(struct hsdk_pll_clk *clk, u32 reg, u32 val)
0123 {
0124     iowrite32(val, clk->regs + reg);
0125 }
0126
0127 static inline u32 hsdk_pll_read(struct hsdk_pll_clk *clk, u32 reg)
0128 {
0129     return ioread32(clk->regs + reg);
0130 }
0131
0132 static inline void hsdk_pll_set_cfg(struct hsdk_pll_clk *clk,
0133                     const struct hsdk_pll_cfg *cfg)
0134 {
0135     u32 val = 0;
0136
0137     if (cfg->bypass) {
0138         val = hsdk_pll_read(clk, CGU_PLL_CTRL);
0139         val |= CGU_PLL_CTRL_BYPASS;
0140     } else {
0141         /* Powerdown and Bypass bits should be cleared */
0142         val |= cfg->idiv << CGU_PLL_CTRL_IDIV_SHIFT;
0143         val |= cfg->fbdiv << CGU_PLL_CTRL_FBDIV_SHIFT;
0144         val |= cfg->odiv << CGU_PLL_CTRL_ODIV_SHIFT;
0145         val |= cfg->band << CGU_PLL_CTRL_BAND_SHIFT;
0146     }
0147
0148     dev_dbg(clk->dev, "write configuration: %#x\n", val);
0149
0150     hsdk_pll_write(clk, CGU_PLL_CTRL, val);
0151 }
0152
0153 static inline bool hsdk_pll_is_locked(struct hsdk_pll_clk *clk)
0154 {
0155     return !!(hsdk_pll_read(clk, CGU_PLL_STATUS) & CGU_PLL_STATUS_LOCK);
0156 }
0157
0158 static inline bool hsdk_pll_is_err(struct hsdk_pll_clk *clk)
0159 {
0160     return !!(hsdk_pll_read(clk, CGU_PLL_STATUS) & CGU_PLL_STATUS_ERR);
0161 }
0162
0163 static inline struct hsdk_pll_clk *to_hsdk_pll_clk(struct clk_hw *hw)
0164 {
0165     return container_of(hw, struct hsdk_pll_clk, hw);
0166 }
0167
0168 static unsigned long hsdk_pll_recalc_rate(struct clk_hw *hw,
0169                       unsigned long parent_rate)
0170 {
0171     u32 val;
0172     u64 rate;
0173     u32 idiv, fbdiv, odiv;
0174     struct hsdk_pll_clk *clk = to_hsdk_pll_clk(hw);
0175
0176     val = hsdk_pll_read(clk, CGU_PLL_CTRL);
0177
0178     dev_dbg(clk->dev, "current configuration: %#x\n", val);
0179
0180     /* Check if PLL is bypassed */
0181     if (val & CGU_PLL_CTRL_BYPASS)
0182         return parent_rate;
0183
0184     /* Check if PLL is disabled */
0185     if (val & CGU_PLL_CTRL_PD)
0186         return 0;
0187
0188     /* input divider = reg.idiv + 1 */
0189     idiv = 1 + ((val & CGU_PLL_CTRL_IDIV_MASK) >> CGU_PLL_CTRL_IDIV_SHIFT);
0190     /* fb divider = 2*(reg.fbdiv + 1) */
0191     fbdiv = 2 * (1 + ((val & CGU_PLL_CTRL_FBDIV_MASK) >> CGU_PLL_CTRL_FBDIV_SHIFT));
0192     /* output divider = 2^(reg.odiv) */
0193     odiv = 1 << ((val & CGU_PLL_CTRL_ODIV_MASK) >> CGU_PLL_CTRL_ODIV_SHIFT);
0194
0195     rate = (u64)parent_rate * fbdiv;
0196     do_div(rate, idiv * odiv);
0197
0198     return rate;
0199 }
0200
0201 static long hsdk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
0202                 unsigned long *prate)
0203 {
0204     int i;
0205     unsigned long best_rate;
0206     struct hsdk_pll_clk *clk = to_hsdk_pll_clk(hw);
0207     const struct hsdk_pll_cfg *pll_cfg = clk->pll_devdata->pll_cfg;
0208
0209     if (pll_cfg[0].rate == 0)
0210         return -EINVAL;
0211
0212     best_rate = pll_cfg[0].rate;
0213
0214     for (i = 1; pll_cfg[i].rate != 0; i++) {
0215         if (abs(rate - pll_cfg[i].rate) < abs(rate - best_rate))
0216             best_rate = pll_cfg[i].rate;
0217     }
0218
0219     dev_dbg(clk->dev, "chosen best rate: %lu\n", best_rate);
0220
0221     return best_rate;
0222 }
0223
0224 static int hsdk_pll_comm_update_rate(struct hsdk_pll_clk *clk,
0225                      unsigned long rate,
0226                      const struct hsdk_pll_cfg *cfg)
0227 {
0228     hsdk_pll_set_cfg(clk, cfg);
0229
0230     /*
0231      * Wait until CGU relocks and check error status.
0232      * If after timeout CGU is unlocked yet return error.
0233      */
0234     udelay(HSDK_PLL_MAX_LOCK_TIME);
0235     if (!hsdk_pll_is_locked(clk))
0236         return -ETIMEDOUT;
0237
0238     if (hsdk_pll_is_err(clk))
0239         return -EINVAL;
0240
0241     return 0;
0242 }
0243
0244 static int hsdk_pll_core_update_rate(struct hsdk_pll_clk *clk,
0245                      unsigned long rate,
0246                      const struct hsdk_pll_cfg *cfg)
0247 {
0248     /*
0249      * When core clock exceeds 500MHz, the divider for the interface
0250      * clock must be programmed to div-by-2.
0251      */
0252     if (rate > CORE_IF_CLK_THRESHOLD_HZ)
0253         iowrite32(CREG_CORE_IF_CLK_DIV_2, clk->spec_regs);
0254
0255     hsdk_pll_set_cfg(clk, cfg);
0256
0257     /*
0258      * Wait until CGU relocks and check error status.
0259      * If after timeout CGU is unlocked yet return error.
0260      */
0261     udelay(HSDK_PLL_MAX_LOCK_TIME);
0262     if (!hsdk_pll_is_locked(clk))
0263         return -ETIMEDOUT;
0264
0265     if (hsdk_pll_is_err(clk))
0266         return -EINVAL;
0267
0268     /*
0269      * Program divider to div-by-1 if we succesfuly set core clock below
0270      * 500MHz threshold.
0271      */
0272     if (rate <= CORE_IF_CLK_THRESHOLD_HZ)
0273         iowrite32(CREG_CORE_IF_CLK_DIV_1, clk->spec_regs);
0274
0275     return 0;
0276 }
0277
0278 static int hsdk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
0279                  unsigned long parent_rate)
0280 {
0281     int i;
0282     struct hsdk_pll_clk *clk = to_hsdk_pll_clk(hw);
0283     const struct hsdk_pll_cfg *pll_cfg = clk->pll_devdata->pll_cfg;
0284
0285     for (i = 0; pll_cfg[i].rate != 0; i++) {
0286         if (pll_cfg[i].rate == rate) {
0287             return clk->pll_devdata->update_rate(clk, rate,
0288                                  &pll_cfg[i]);
0289         }
0290     }
0291
0292     dev_err(clk->dev, "invalid rate=%ld, parent_rate=%ld\n", rate,
0293             parent_rate);
0294
0295     return -EINVAL;
0296 }
0297
0298 static const struct clk_ops hsdk_pll_ops = {
0299     .recalc_rate = hsdk_pll_recalc_rate,
0300     .round_rate = hsdk_pll_round_rate,
0301     .set_rate = hsdk_pll_set_rate,
0302 };
0303
0304 static int hsdk_pll_clk_probe(struct platform_device *pdev)
0305 {
0306     int ret;
0307     struct resource *mem;
0308     const char *parent_name;
0309     unsigned int num_parents;
0310     struct hsdk_pll_clk *pll_clk;
0311     struct clk_init_data init = { };
0312     struct device *dev = &pdev->dev;
0313
0314     pll_clk = devm_kzalloc(dev, sizeof(*pll_clk), GFP_KERNEL);
0315     if (!pll_clk)
0316         return -ENOMEM;
0317
0318     mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0319     pll_clk->regs = devm_ioremap_resource(dev, mem);
0320     if (IS_ERR(pll_clk->regs))
0321         return PTR_ERR(pll_clk->regs);
0322
0323     init.name = dev->of_node->name;
0324     init.ops = &hsdk_pll_ops;
0325     parent_name = of_clk_get_parent_name(dev->of_node, 0);
0326     init.parent_names = &parent_name;
0327     num_parents = of_clk_get_parent_count(dev->of_node);
0328     if (num_parents == 0 || num_parents > CGU_PLL_SOURCE_MAX) {
0329         dev_err(dev, "wrong clock parents number: %u\n", num_parents);
0330         return -EINVAL;
0331     }
0332     init.num_parents = num_parents;
0333
0334     pll_clk->hw.init = &init;
0335     pll_clk->dev = dev;
0336     pll_clk->pll_devdata = of_device_get_match_data(dev);
0337
0338     if (!pll_clk->pll_devdata) {
0339         dev_err(dev, "No OF match data provided\n");
0340         return -EINVAL;
0341     }
0342
0343     ret = devm_clk_hw_register(dev, &pll_clk->hw);
0344     if (ret) {
0345         dev_err(dev, "failed to register %s clock\n", init.name);
0346         return ret;
0347     }
0348
0349     return of_clk_add_hw_provider(dev->of_node, of_clk_hw_simple_get,
0350             &pll_clk->hw);
0351 }
0352
0353 static int hsdk_pll_clk_remove(struct platform_device *pdev)
0354 {
0355     of_clk_del_provider(pdev->dev.of_node);
0356     return 0;
0357 }
0358
0359 static void __init of_hsdk_pll_clk_setup(struct device_node *node)
0360 {
0361     int ret;
0362     const char *parent_name;
0363     unsigned int num_parents;
0364     struct hsdk_pll_clk *pll_clk;
0365     struct clk_init_data init = { };
0366
0367     pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
0368     if (!pll_clk)
0369         return;
0370
0371     pll_clk->regs = of_iomap(node, 0);
0372     if (!pll_clk->regs) {
0373         pr_err("failed to map pll registers\n");
0374         goto err_free_pll_clk;
0375     }
0376
0377     pll_clk->spec_regs = of_iomap(node, 1);
0378     if (!pll_clk->spec_regs) {
0379         pr_err("failed to map pll registers\n");
0380         goto err_unmap_comm_regs;
0381     }
0382
0383     init.name = node->name;
0384     init.ops = &hsdk_pll_ops;
0385     parent_name = of_clk_get_parent_name(node, 0);
0386     init.parent_names = &parent_name;
0387     num_parents = of_clk_get_parent_count(node);
0388     if (num_parents > CGU_PLL_SOURCE_MAX) {
0389         pr_err("too much clock parents: %u\n", num_parents);
0390         goto err_unmap_spec_regs;
0391     }
0392     init.num_parents = num_parents;
0393
0394     pll_clk->hw.init = &init;
0395     pll_clk->pll_devdata = &core_pll_devdata;
0396
0397     ret = clk_hw_register(NULL, &pll_clk->hw);
0398     if (ret) {
0399         pr_err("failed to register %pOFn clock\n", node);
0400         goto err_unmap_spec_regs;
0401     }
0402
0403     ret = of_clk_add_hw_provider(node, of_clk_hw_simple_get, &pll_clk->hw);
0404     if (ret) {
0405         pr_err("failed to add hw provider for %pOFn clock\n", node);
0406         goto err_unmap_spec_regs;
0407     }
0408
0409     return;
0410
0411 err_unmap_spec_regs:
0412     iounmap(pll_clk->spec_regs);
0413 err_unmap_comm_regs:
0414     iounmap(pll_clk->regs);
0415 err_free_pll_clk:
0416     kfree(pll_clk);
0417 }
0418
0419 /* Core PLL needed early for ARC cpus timers */
0420 CLK_OF_DECLARE(hsdk_pll_clock, "snps,hsdk-core-pll-clock",
0421 of_hsdk_pll_clk_setup);
0422
0423 static const struct of_device_id hsdk_pll_clk_id[] = {
0424     { .compatible = "snps,hsdk-gp-pll-clock", .data = &sdt_pll_devdata},
0425     { .compatible = "snps,hsdk-hdmi-pll-clock", .data = &hdmi_pll_devdata},
0426     { }
0427 };
0428
0429 static struct platform_driver hsdk_pll_clk_driver = {
0430     .driver = {
0431         .name = "hsdk-gp-pll-clock",
0432         .of_match_table = hsdk_pll_clk_id,
0433     },
0434     .probe = hsdk_pll_clk_probe,
0435     .remove = hsdk_pll_clk_remove,
0436 };
0437 builtin_platform_driver(hsdk_pll_clk_driver);