drivers/clk/clk-highbank.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright 2011-2012 Calxeda, Inc.
0004  */
0005
0006 #include <linux/kernel.h>
0007 #include <linux/slab.h>
0008 #include <linux/err.h>
0009 #include <linux/clk-provider.h>
0010 #include <linux/io.h>
0011 #include <linux/of.h>
0012 #include <linux/of_address.h>
0013
0014 #define HB_PLL_LOCK_500     0x20000000
0015 #define HB_PLL_LOCK     0x10000000
0016 #define HB_PLL_DIVF_SHIFT   20
0017 #define HB_PLL_DIVF_MASK    0x0ff00000
0018 #define HB_PLL_DIVQ_SHIFT   16
0019 #define HB_PLL_DIVQ_MASK    0x00070000
0020 #define HB_PLL_DIVR_SHIFT   8
0021 #define HB_PLL_DIVR_MASK    0x00001f00
0022 #define HB_PLL_RANGE_SHIFT  4
0023 #define HB_PLL_RANGE_MASK   0x00000070
0024 #define HB_PLL_BYPASS       0x00000008
0025 #define HB_PLL_RESET        0x00000004
0026 #define HB_PLL_EXT_BYPASS   0x00000002
0027 #define HB_PLL_EXT_ENA      0x00000001
0028
0029 #define HB_PLL_VCO_MIN_FREQ 2133000000
0030 #define HB_PLL_MAX_FREQ     HB_PLL_VCO_MIN_FREQ
0031 #define HB_PLL_MIN_FREQ     (HB_PLL_VCO_MIN_FREQ / 64)
0032
0033 #define HB_A9_BCLK_DIV_MASK 0x00000006
0034 #define HB_A9_BCLK_DIV_SHIFT    1
0035 #define HB_A9_PCLK_DIV      0x00000001
0036
0037 struct hb_clk {
0038         struct clk_hw   hw;
0039     void __iomem    *reg;
0040     char *parent_name;
0041 };
0042 #define to_hb_clk(p) container_of(p, struct hb_clk, hw)
0043
0044 static int clk_pll_prepare(struct clk_hw *hwclk)
0045     {
0046     struct hb_clk *hbclk = to_hb_clk(hwclk);
0047     u32 reg;
0048
0049     reg = readl(hbclk->reg);
0050     reg &= ~HB_PLL_RESET;
0051     writel(reg, hbclk->reg);
0052
0053     while ((readl(hbclk->reg) & HB_PLL_LOCK) == 0)
0054         ;
0055     while ((readl(hbclk->reg) & HB_PLL_LOCK_500) == 0)
0056         ;
0057
0058     return 0;
0059 }
0060
0061 static void clk_pll_unprepare(struct clk_hw *hwclk)
0062 {
0063     struct hb_clk *hbclk = to_hb_clk(hwclk);
0064     u32 reg;
0065
0066     reg = readl(hbclk->reg);
0067     reg |= HB_PLL_RESET;
0068     writel(reg, hbclk->reg);
0069 }
0070
0071 static int clk_pll_enable(struct clk_hw *hwclk)
0072 {
0073     struct hb_clk *hbclk = to_hb_clk(hwclk);
0074     u32 reg;
0075
0076     reg = readl(hbclk->reg);
0077     reg |= HB_PLL_EXT_ENA;
0078     writel(reg, hbclk->reg);
0079
0080     return 0;
0081 }
0082
0083 static void clk_pll_disable(struct clk_hw *hwclk)
0084 {
0085     struct hb_clk *hbclk = to_hb_clk(hwclk);
0086     u32 reg;
0087
0088     reg = readl(hbclk->reg);
0089     reg &= ~HB_PLL_EXT_ENA;
0090     writel(reg, hbclk->reg);
0091 }
0092
0093 static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk,
0094                      unsigned long parent_rate)
0095 {
0096     struct hb_clk *hbclk = to_hb_clk(hwclk);
0097     unsigned long divf, divq, vco_freq, reg;
0098
0099     reg = readl(hbclk->reg);
0100     if (reg & HB_PLL_EXT_BYPASS)
0101         return parent_rate;
0102
0103     divf = (reg & HB_PLL_DIVF_MASK) >> HB_PLL_DIVF_SHIFT;
0104     divq = (reg & HB_PLL_DIVQ_MASK) >> HB_PLL_DIVQ_SHIFT;
0105     vco_freq = parent_rate * (divf + 1);
0106
0107     return vco_freq / (1 << divq);
0108 }
0109
0110 static void clk_pll_calc(unsigned long rate, unsigned long ref_freq,
0111             u32 *pdivq, u32 *pdivf)
0112 {
0113     u32 divq, divf;
0114     unsigned long vco_freq;
0115
0116     if (rate < HB_PLL_MIN_FREQ)
0117         rate = HB_PLL_MIN_FREQ;
0118     if (rate > HB_PLL_MAX_FREQ)
0119         rate = HB_PLL_MAX_FREQ;
0120
0121     for (divq = 1; divq <= 6; divq++) {
0122         if ((rate * (1 << divq)) >= HB_PLL_VCO_MIN_FREQ)
0123             break;
0124     }
0125
0126     vco_freq = rate * (1 << divq);
0127     divf = (vco_freq + (ref_freq / 2)) / ref_freq;
0128     divf--;
0129
0130     *pdivq = divq;
0131     *pdivf = divf;
0132 }
0133
0134 static long clk_pll_round_rate(struct clk_hw *hwclk, unsigned long rate,
0135                    unsigned long *parent_rate)
0136 {
0137     u32 divq, divf;
0138     unsigned long ref_freq = *parent_rate;
0139
0140     clk_pll_calc(rate, ref_freq, &divq, &divf);
0141
0142     return (ref_freq * (divf + 1)) / (1 << divq);
0143 }
0144
0145 static int clk_pll_set_rate(struct clk_hw *hwclk, unsigned long rate,
0146                 unsigned long parent_rate)
0147 {
0148     struct hb_clk *hbclk = to_hb_clk(hwclk);
0149     u32 divq, divf;
0150     u32 reg;
0151
0152     clk_pll_calc(rate, parent_rate, &divq, &divf);
0153
0154     reg = readl(hbclk->reg);
0155     if (divf != ((reg & HB_PLL_DIVF_MASK) >> HB_PLL_DIVF_SHIFT)) {
0156         /* Need to re-lock PLL, so put it into bypass mode */
0157         reg |= HB_PLL_EXT_BYPASS;
0158         writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg);
0159
0160         writel(reg | HB_PLL_RESET, hbclk->reg);
0161         reg &= ~(HB_PLL_DIVF_MASK | HB_PLL_DIVQ_MASK);
0162         reg |= (divf << HB_PLL_DIVF_SHIFT) | (divq << HB_PLL_DIVQ_SHIFT);
0163         writel(reg | HB_PLL_RESET, hbclk->reg);
0164         writel(reg, hbclk->reg);
0165
0166         while ((readl(hbclk->reg) & HB_PLL_LOCK) == 0)
0167             ;
0168         while ((readl(hbclk->reg) & HB_PLL_LOCK_500) == 0)
0169             ;
0170         reg |= HB_PLL_EXT_ENA;
0171         reg &= ~HB_PLL_EXT_BYPASS;
0172     } else {
0173         writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg);
0174         reg &= ~HB_PLL_DIVQ_MASK;
0175         reg |= divq << HB_PLL_DIVQ_SHIFT;
0176         writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg);
0177     }
0178     writel(reg, hbclk->reg);
0179
0180     return 0;
0181 }
0182
0183 static const struct clk_ops clk_pll_ops = {
0184     .prepare = clk_pll_prepare,
0185     .unprepare = clk_pll_unprepare,
0186     .enable = clk_pll_enable,
0187     .disable = clk_pll_disable,
0188     .recalc_rate = clk_pll_recalc_rate,
0189     .round_rate = clk_pll_round_rate,
0190     .set_rate = clk_pll_set_rate,
0191 };
0192
0193 static unsigned long clk_cpu_periphclk_recalc_rate(struct clk_hw *hwclk,
0194                            unsigned long parent_rate)
0195 {
0196     struct hb_clk *hbclk = to_hb_clk(hwclk);
0197     u32 div = (readl(hbclk->reg) & HB_A9_PCLK_DIV) ? 8 : 4;
0198     return parent_rate / div;
0199 }
0200
0201 static const struct clk_ops a9periphclk_ops = {
0202     .recalc_rate = clk_cpu_periphclk_recalc_rate,
0203 };
0204
0205 static unsigned long clk_cpu_a9bclk_recalc_rate(struct clk_hw *hwclk,
0206                         unsigned long parent_rate)
0207 {
0208     struct hb_clk *hbclk = to_hb_clk(hwclk);
0209     u32 div = (readl(hbclk->reg) & HB_A9_BCLK_DIV_MASK) >> HB_A9_BCLK_DIV_SHIFT;
0210
0211     return parent_rate / (div + 2);
0212 }
0213
0214 static const struct clk_ops a9bclk_ops = {
0215     .recalc_rate = clk_cpu_a9bclk_recalc_rate,
0216 };
0217
0218 static unsigned long clk_periclk_recalc_rate(struct clk_hw *hwclk,
0219                          unsigned long parent_rate)
0220 {
0221     struct hb_clk *hbclk = to_hb_clk(hwclk);
0222     u32 div;
0223
0224     div = readl(hbclk->reg) & 0x1f;
0225     div++;
0226     div *= 2;
0227
0228     return parent_rate / div;
0229 }
0230
0231 static long clk_periclk_round_rate(struct clk_hw *hwclk, unsigned long rate,
0232                    unsigned long *parent_rate)
0233 {
0234     u32 div;
0235
0236     div = *parent_rate / rate;
0237     div++;
0238     div &= ~0x1;
0239
0240     return *parent_rate / div;
0241 }
0242
0243 static int clk_periclk_set_rate(struct clk_hw *hwclk, unsigned long rate,
0244                 unsigned long parent_rate)
0245 {
0246     struct hb_clk *hbclk = to_hb_clk(hwclk);
0247     u32 div;
0248
0249     div = parent_rate / rate;
0250     if (div & 0x1)
0251         return -EINVAL;
0252
0253     writel(div >> 1, hbclk->reg);
0254     return 0;
0255 }
0256
0257 static const struct clk_ops periclk_ops = {
0258     .recalc_rate = clk_periclk_recalc_rate,
0259     .round_rate = clk_periclk_round_rate,
0260     .set_rate = clk_periclk_set_rate,
0261 };
0262
0263 static void __init hb_clk_init(struct device_node *node, const struct clk_ops *ops, unsigned long clkflags)
0264 {
0265     u32 reg;
0266     struct hb_clk *hb_clk;
0267     const char *clk_name = node->name;
0268     const char *parent_name;
0269     struct clk_init_data init;
0270     struct device_node *srnp;
0271     int rc;
0272
0273     rc = of_property_read_u32(node, "reg", &reg);
0274     if (WARN_ON(rc))
0275         return;
0276
0277     hb_clk = kzalloc(sizeof(*hb_clk), GFP_KERNEL);
0278     if (WARN_ON(!hb_clk))
0279         return;
0280
0281     /* Map system registers */
0282     srnp = of_find_compatible_node(NULL, NULL, "calxeda,hb-sregs");
0283     hb_clk->reg = of_iomap(srnp, 0);
0284     of_node_put(srnp);
0285     BUG_ON(!hb_clk->reg);
0286     hb_clk->reg += reg;
0287
0288     of_property_read_string(node, "clock-output-names", &clk_name);
0289
0290     init.name = clk_name;
0291     init.ops = ops;
0292     init.flags = clkflags;
0293     parent_name = of_clk_get_parent_name(node, 0);
0294     init.parent_names = &parent_name;
0295     init.num_parents = 1;
0296
0297     hb_clk->hw.init = &init;
0298
0299     rc = clk_hw_register(NULL, &hb_clk->hw);
0300     if (WARN_ON(rc)) {
0301         kfree(hb_clk);
0302         return;
0303     }
0304     of_clk_add_hw_provider(node, of_clk_hw_simple_get, &hb_clk->hw);
0305 }
0306
0307 static void __init hb_pll_init(struct device_node *node)
0308 {
0309     hb_clk_init(node, &clk_pll_ops, 0);
0310 }
0311 CLK_OF_DECLARE(hb_pll, "calxeda,hb-pll-clock", hb_pll_init);
0312
0313 static void __init hb_a9periph_init(struct device_node *node)
0314 {
0315     hb_clk_init(node, &a9periphclk_ops, 0);
0316 }
0317 CLK_OF_DECLARE(hb_a9periph, "calxeda,hb-a9periph-clock", hb_a9periph_init);
0318
0319 static void __init hb_a9bus_init(struct device_node *node)
0320 {
0321     hb_clk_init(node, &a9bclk_ops, CLK_IS_CRITICAL);
0322 }
0323 CLK_OF_DECLARE(hb_a9bus, "calxeda,hb-a9bus-clock", hb_a9bus_init);
0324
0325 static void __init hb_emmc_init(struct device_node *node)
0326 {
0327     hb_clk_init(node, &periclk_ops, 0);
0328 }
0329 CLK_OF_DECLARE(hb_emmc, "calxeda,hb-emmc-clock", hb_emmc_init);