drivers/clk/clk-gemini.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Cortina Gemini SoC Clock Controller driver
0004  * Copyright (c) 2017 Linus Walleij <linus.walleij@linaro.org>
0005  */
0006
0007 #define pr_fmt(fmt) "clk-gemini: " fmt
0008
0009 #include <linux/init.h>
0010 #include <linux/module.h>
0011 #include <linux/platform_device.h>
0012 #include <linux/slab.h>
0013 #include <linux/err.h>
0014 #include <linux/io.h>
0015 #include <linux/clk-provider.h>
0016 #include <linux/of.h>
0017 #include <linux/of_address.h>
0018 #include <linux/mfd/syscon.h>
0019 #include <linux/regmap.h>
0020 #include <linux/spinlock.h>
0021 #include <linux/reset-controller.h>
0022 #include <dt-bindings/reset/cortina,gemini-reset.h>
0023 #include <dt-bindings/clock/cortina,gemini-clock.h>
0024
0025 /* Globally visible clocks */
0026 static DEFINE_SPINLOCK(gemini_clk_lock);
0027
0028 #define GEMINI_GLOBAL_STATUS        0x04
0029 #define PLL_OSC_SEL         BIT(30)
0030 #define AHBSPEED_SHIFT          (15)
0031 #define AHBSPEED_MASK           0x07
0032 #define CPU_AHB_RATIO_SHIFT     (18)
0033 #define CPU_AHB_RATIO_MASK      0x03
0034
0035 #define GEMINI_GLOBAL_PLL_CONTROL   0x08
0036
0037 #define GEMINI_GLOBAL_SOFT_RESET    0x0c
0038
0039 #define GEMINI_GLOBAL_MISC_CONTROL  0x30
0040 #define PCI_CLK_66MHZ           BIT(18)
0041
0042 #define GEMINI_GLOBAL_CLOCK_CONTROL 0x34
0043 #define PCI_CLKRUN_EN           BIT(16)
0044 #define TVC_HALFDIV_SHIFT       (24)
0045 #define TVC_HALFDIV_MASK        0x1f
0046 #define SECURITY_CLK_SEL        BIT(29)
0047
0048 #define GEMINI_GLOBAL_PCI_DLL_CONTROL   0x44
0049 #define PCI_DLL_BYPASS          BIT(31)
0050 #define PCI_DLL_TAP_SEL_MASK        0x1f
0051
0052 /**
0053  * struct gemini_gate_data - Gemini gated clocks
0054  * @bit_idx: the bit used to gate this clock in the clock register
0055  * @name: the clock name
0056  * @parent_name: the name of the parent clock
0057  * @flags: standard clock framework flags
0058  */
0059 struct gemini_gate_data {
0060     u8 bit_idx;
0061     const char *name;
0062     const char *parent_name;
0063     unsigned long flags;
0064 };
0065
0066 /**
0067  * struct clk_gemini_pci - Gemini PCI clock
0068  * @hw: corresponding clock hardware entry
0069  * @map: regmap to access the registers
0070  * @rate: current rate
0071  */
0072 struct clk_gemini_pci {
0073     struct clk_hw hw;
0074     struct regmap *map;
0075     unsigned long rate;
0076 };
0077
0078 /**
0079  * struct gemini_reset - gemini reset controller
0080  * @map: regmap to access the containing system controller
0081  * @rcdev: reset controller device
0082  */
0083 struct gemini_reset {
0084     struct regmap *map;
0085     struct reset_controller_dev rcdev;
0086 };
0087
0088 /* Keeps track of all clocks */
0089 static struct clk_hw_onecell_data *gemini_clk_data;
0090
0091 static const struct gemini_gate_data gemini_gates[] = {
0092     { 1, "security-gate", "secdiv", 0 },
0093     { 2, "gmac0-gate", "ahb", 0 },
0094     { 3, "gmac1-gate", "ahb", 0 },
0095     { 4, "sata0-gate", "ahb", 0 },
0096     { 5, "sata1-gate", "ahb", 0 },
0097     { 6, "usb0-gate", "ahb", 0 },
0098     { 7, "usb1-gate", "ahb", 0 },
0099     { 8, "ide-gate", "ahb", 0 },
0100     { 9, "pci-gate", "ahb", 0 },
0101     /*
0102      * The DDR controller may never have a driver, but certainly must
0103      * not be gated off.
0104      */
0105     { 10, "ddr-gate", "ahb", CLK_IS_CRITICAL },
0106     /*
0107      * The flash controller must be on to access NOR flash through the
0108      * memory map.
0109      */
0110     { 11, "flash-gate", "ahb", CLK_IGNORE_UNUSED },
0111     { 12, "tvc-gate", "ahb", 0 },
0112     { 13, "boot-gate", "apb", 0 },
0113 };
0114
0115 #define to_pciclk(_hw) container_of(_hw, struct clk_gemini_pci, hw)
0116
0117 #define to_gemini_reset(p) container_of((p), struct gemini_reset, rcdev)
0118
0119 static unsigned long gemini_pci_recalc_rate(struct clk_hw *hw,
0120                         unsigned long parent_rate)
0121 {
0122     struct clk_gemini_pci *pciclk = to_pciclk(hw);
0123     u32 val;
0124
0125     regmap_read(pciclk->map, GEMINI_GLOBAL_MISC_CONTROL, &val);
0126     if (val & PCI_CLK_66MHZ)
0127         return 66000000;
0128     return 33000000;
0129 }
0130
0131 static long gemini_pci_round_rate(struct clk_hw *hw, unsigned long rate,
0132                   unsigned long *prate)
0133 {
0134     /* We support 33 and 66 MHz */
0135     if (rate < 48000000)
0136         return 33000000;
0137     return 66000000;
0138 }
0139
0140 static int gemini_pci_set_rate(struct clk_hw *hw, unsigned long rate,
0141                    unsigned long parent_rate)
0142 {
0143     struct clk_gemini_pci *pciclk = to_pciclk(hw);
0144
0145     if (rate == 33000000)
0146         return regmap_update_bits(pciclk->map,
0147                       GEMINI_GLOBAL_MISC_CONTROL,
0148                       PCI_CLK_66MHZ, 0);
0149     if (rate == 66000000)
0150         return regmap_update_bits(pciclk->map,
0151                       GEMINI_GLOBAL_MISC_CONTROL,
0152                       0, PCI_CLK_66MHZ);
0153     return -EINVAL;
0154 }
0155
0156 static int gemini_pci_enable(struct clk_hw *hw)
0157 {
0158     struct clk_gemini_pci *pciclk = to_pciclk(hw);
0159
0160     regmap_update_bits(pciclk->map, GEMINI_GLOBAL_CLOCK_CONTROL,
0161                0, PCI_CLKRUN_EN);
0162     return 0;
0163 }
0164
0165 static void gemini_pci_disable(struct clk_hw *hw)
0166 {
0167     struct clk_gemini_pci *pciclk = to_pciclk(hw);
0168
0169     regmap_update_bits(pciclk->map, GEMINI_GLOBAL_CLOCK_CONTROL,
0170                PCI_CLKRUN_EN, 0);
0171 }
0172
0173 static int gemini_pci_is_enabled(struct clk_hw *hw)
0174 {
0175     struct clk_gemini_pci *pciclk = to_pciclk(hw);
0176     unsigned int val;
0177
0178     regmap_read(pciclk->map, GEMINI_GLOBAL_CLOCK_CONTROL, &val);
0179     return !!(val & PCI_CLKRUN_EN);
0180 }
0181
0182 static const struct clk_ops gemini_pci_clk_ops = {
0183     .recalc_rate = gemini_pci_recalc_rate,
0184     .round_rate = gemini_pci_round_rate,
0185     .set_rate = gemini_pci_set_rate,
0186     .enable = gemini_pci_enable,
0187     .disable = gemini_pci_disable,
0188     .is_enabled = gemini_pci_is_enabled,
0189 };
0190
0191 static struct clk_hw *gemini_pci_clk_setup(const char *name,
0192                        const char *parent_name,
0193                        struct regmap *map)
0194 {
0195     struct clk_gemini_pci *pciclk;
0196     struct clk_init_data init;
0197     int ret;
0198
0199     pciclk = kzalloc(sizeof(*pciclk), GFP_KERNEL);
0200     if (!pciclk)
0201         return ERR_PTR(-ENOMEM);
0202
0203     init.name = name;
0204     init.ops = &gemini_pci_clk_ops;
0205     init.flags = 0;
0206     init.parent_names = &parent_name;
0207     init.num_parents = 1;
0208     pciclk->map = map;
0209     pciclk->hw.init = &init;
0210
0211     ret = clk_hw_register(NULL, &pciclk->hw);
0212     if (ret) {
0213         kfree(pciclk);
0214         return ERR_PTR(ret);
0215     }
0216
0217     return &pciclk->hw;
0218 }
0219
0220 /*
0221  * This is a self-deasserting reset controller.
0222  */
0223 static int gemini_reset(struct reset_controller_dev *rcdev,
0224             unsigned long id)
0225 {
0226     struct gemini_reset *gr = to_gemini_reset(rcdev);
0227
0228     /* Manual says to always set BIT 30 (CPU1) to 1 */
0229     return regmap_write(gr->map,
0230                 GEMINI_GLOBAL_SOFT_RESET,
0231                 BIT(GEMINI_RESET_CPU1) | BIT(id));
0232 }
0233
0234 static int gemini_reset_assert(struct reset_controller_dev *rcdev,
0235                    unsigned long id)
0236 {
0237     return 0;
0238 }
0239
0240 static int gemini_reset_deassert(struct reset_controller_dev *rcdev,
0241                  unsigned long id)
0242 {
0243     return 0;
0244 }
0245
0246 static int gemini_reset_status(struct reset_controller_dev *rcdev,
0247                  unsigned long id)
0248 {
0249     struct gemini_reset *gr = to_gemini_reset(rcdev);
0250     u32 val;
0251     int ret;
0252
0253     ret = regmap_read(gr->map, GEMINI_GLOBAL_SOFT_RESET, &val);
0254     if (ret)
0255         return ret;
0256
0257     return !!(val & BIT(id));
0258 }
0259
0260 static const struct reset_control_ops gemini_reset_ops = {
0261     .reset = gemini_reset,
0262     .assert = gemini_reset_assert,
0263     .deassert = gemini_reset_deassert,
0264     .status = gemini_reset_status,
0265 };
0266
0267 static int gemini_clk_probe(struct platform_device *pdev)
0268 {
0269     /* Gives the fracions 1x, 1.5x, 1.85x and 2x */
0270     unsigned int cpu_ahb_mult[4] = { 1, 3, 24, 2 };
0271     unsigned int cpu_ahb_div[4] = { 1, 2, 13, 1 };
0272     void __iomem *base;
0273     struct gemini_reset *gr;
0274     struct regmap *map;
0275     struct clk_hw *hw;
0276     struct device *dev = &pdev->dev;
0277     struct device_node *np = dev->of_node;
0278     unsigned int mult, div;
0279     struct resource *res;
0280     u32 val;
0281     int ret;
0282     int i;
0283
0284     gr = devm_kzalloc(dev, sizeof(*gr), GFP_KERNEL);
0285     if (!gr)
0286         return -ENOMEM;
0287
0288     /* Remap the system controller for the exclusive register */
0289     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0290     base = devm_ioremap_resource(dev, res);
0291     if (IS_ERR(base))
0292         return PTR_ERR(base);
0293
0294     map = syscon_node_to_regmap(np);
0295     if (IS_ERR(map)) {
0296         dev_err(dev, "no syscon regmap\n");
0297         return PTR_ERR(map);
0298     }
0299
0300     gr->map = map;
0301     gr->rcdev.owner = THIS_MODULE;
0302     gr->rcdev.nr_resets = 32;
0303     gr->rcdev.ops = &gemini_reset_ops;
0304     gr->rcdev.of_node = np;
0305
0306     ret = devm_reset_controller_register(dev, &gr->rcdev);
0307     if (ret) {
0308         dev_err(dev, "could not register reset controller\n");
0309         return ret;
0310     }
0311
0312     /* RTC clock 32768 Hz */
0313     hw = clk_hw_register_fixed_rate(NULL, "rtc", NULL, 0, 32768);
0314     gemini_clk_data->hws[GEMINI_CLK_RTC] = hw;
0315
0316     /* CPU clock derived as a fixed ratio from the AHB clock */
0317     regmap_read(map, GEMINI_GLOBAL_STATUS, &val);
0318     val >>= CPU_AHB_RATIO_SHIFT;
0319     val &= CPU_AHB_RATIO_MASK;
0320     hw = clk_hw_register_fixed_factor(NULL, "cpu", "ahb", 0,
0321                       cpu_ahb_mult[val],
0322                       cpu_ahb_div[val]);
0323     gemini_clk_data->hws[GEMINI_CLK_CPU] = hw;
0324
0325     /* Security clock is 1:1 or 0.75 of APB */
0326     regmap_read(map, GEMINI_GLOBAL_CLOCK_CONTROL, &val);
0327     if (val & SECURITY_CLK_SEL) {
0328         mult = 1;
0329         div = 1;
0330     } else {
0331         mult = 3;
0332         div = 4;
0333     }
0334     hw = clk_hw_register_fixed_factor(NULL, "secdiv", "ahb", 0, mult, div);
0335
0336     /*
0337      * These are the leaf gates, at boot no clocks are gated.
0338      */
0339     for (i = 0; i < ARRAY_SIZE(gemini_gates); i++) {
0340         const struct gemini_gate_data *gd;
0341
0342         gd = &gemini_gates[i];
0343         gemini_clk_data->hws[GEMINI_CLK_GATES + i] =
0344             clk_hw_register_gate(NULL, gd->name,
0345                          gd->parent_name,
0346                          gd->flags,
0347                          base + GEMINI_GLOBAL_CLOCK_CONTROL,
0348                          gd->bit_idx,
0349                          CLK_GATE_SET_TO_DISABLE,
0350                          &gemini_clk_lock);
0351     }
0352
0353     /*
0354      * The TV Interface Controller has a 5-bit half divider register.
0355      * This clock is supposed to be 27MHz as this is an exact multiple
0356      * of PAL and NTSC frequencies. The register is undocumented :(
0357      * FIXME: figure out the parent and how the divider works.
0358      */
0359     mult = 1;
0360     div = ((val >> TVC_HALFDIV_SHIFT) & TVC_HALFDIV_MASK);
0361     dev_dbg(dev, "TVC half divider value = %d\n", div);
0362     div += 1;
0363     hw = clk_hw_register_fixed_rate(NULL, "tvcdiv", "xtal", 0, 27000000);
0364     gemini_clk_data->hws[GEMINI_CLK_TVC] = hw;
0365
0366     /* FIXME: very unclear what the parent is */
0367     hw = gemini_pci_clk_setup("PCI", "xtal", map);
0368     gemini_clk_data->hws[GEMINI_CLK_PCI] = hw;
0369
0370     /* FIXME: very unclear what the parent is */
0371     hw = clk_hw_register_fixed_rate(NULL, "uart", "xtal", 0, 48000000);
0372     gemini_clk_data->hws[GEMINI_CLK_UART] = hw;
0373
0374     return 0;
0375 }
0376
0377 static const struct of_device_id gemini_clk_dt_ids[] = {
0378     { .compatible = "cortina,gemini-syscon", },
0379     { /* sentinel */ },
0380 };
0381
0382 static struct platform_driver gemini_clk_driver = {
0383     .probe  = gemini_clk_probe,
0384     .driver = {
0385         .name = "gemini-clk",
0386         .of_match_table = gemini_clk_dt_ids,
0387         .suppress_bind_attrs = true,
0388     },
0389 };
0390 builtin_platform_driver(gemini_clk_driver);
0391
0392 static void __init gemini_cc_init(struct device_node *np)
0393 {
0394     struct regmap *map;
0395     struct clk_hw *hw;
0396     unsigned long freq;
0397     unsigned int mult, div;
0398     u32 val;
0399     int ret;
0400     int i;
0401
0402     gemini_clk_data = kzalloc(struct_size(gemini_clk_data, hws,
0403                           GEMINI_NUM_CLKS),
0404                   GFP_KERNEL);
0405     if (!gemini_clk_data)
0406         return;
0407
0408     /*
0409      * This way all clock fetched before the platform device probes,
0410      * except those we assign here for early use, will be deferred.
0411      */
0412     for (i = 0; i < GEMINI_NUM_CLKS; i++)
0413         gemini_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);
0414
0415     map = syscon_node_to_regmap(np);
0416     if (IS_ERR(map)) {
0417         pr_err("no syscon regmap\n");
0418         return;
0419     }
0420     /*
0421      * We check that the regmap works on this very first access,
0422      * but as this is an MMIO-backed regmap, subsequent regmap
0423      * access is not going to fail and we skip error checks from
0424      * this point.
0425      */
0426     ret = regmap_read(map, GEMINI_GLOBAL_STATUS, &val);
0427     if (ret) {
0428         pr_err("failed to read global status register\n");
0429         return;
0430     }
0431
0432     /*
0433      * XTAL is the crystal oscillator, 60 or 30 MHz selected from
0434      * strap pin E6
0435      */
0436     if (val & PLL_OSC_SEL)
0437         freq = 30000000;
0438     else
0439         freq = 60000000;
0440     hw = clk_hw_register_fixed_rate(NULL, "xtal", NULL, 0, freq);
0441     pr_debug("main crystal @%lu MHz\n", freq / 1000000);
0442
0443     /* VCO clock derived from the crystal */
0444     mult = 13 + ((val >> AHBSPEED_SHIFT) & AHBSPEED_MASK);
0445     div = 2;
0446     /* If we run on 30 MHz crystal we have to multiply with two */
0447     if (val & PLL_OSC_SEL)
0448         mult *= 2;
0449     hw = clk_hw_register_fixed_factor(NULL, "vco", "xtal", 0, mult, div);
0450
0451     /* The AHB clock is always 1/3 of the VCO */
0452     hw = clk_hw_register_fixed_factor(NULL, "ahb", "vco", 0, 1, 3);
0453     gemini_clk_data->hws[GEMINI_CLK_AHB] = hw;
0454
0455     /* The APB clock is always 1/6 of the AHB */
0456     hw = clk_hw_register_fixed_factor(NULL, "apb", "ahb", 0, 1, 6);
0457     gemini_clk_data->hws[GEMINI_CLK_APB] = hw;
0458
0459     /* Register the clocks to be accessed by the device tree */
0460     gemini_clk_data->num = GEMINI_NUM_CLKS;
0461     of_clk_add_hw_provider(np, of_clk_hw_onecell_get, gemini_clk_data);
0462 }
0463 CLK_OF_DECLARE_DRIVER(gemini_cc, "cortina,gemini-syscon", gemini_cc_init);