drivers/clk/clk-fsl-sai.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Freescale SAI BCLK as a generic clock driver
0004  *
0005  * Copyright 2020 Michael Walle <michael@walle.cc>
0006  */
0007
0008 #include <linux/module.h>
0009 #include <linux/platform_device.h>
0010 #include <linux/clk-provider.h>
0011 #include <linux/err.h>
0012 #include <linux/of.h>
0013 #include <linux/of_address.h>
0014 #include <linux/slab.h>
0015
0016 #define I2S_CSR     0x00
0017 #define I2S_CR2     0x08
0018 #define CSR_BCE_BIT 28
0019 #define CR2_BCD     BIT(24)
0020 #define CR2_DIV_SHIFT   0
0021 #define CR2_DIV_WIDTH   8
0022
0023 struct fsl_sai_clk {
0024     struct clk_divider div;
0025     struct clk_gate gate;
0026     spinlock_t lock;
0027 };
0028
0029 static int fsl_sai_clk_probe(struct platform_device *pdev)
0030 {
0031     struct device *dev = &pdev->dev;
0032     struct fsl_sai_clk *sai_clk;
0033     struct clk_parent_data pdata = { .index = 0 };
0034     void __iomem *base;
0035     struct clk_hw *hw;
0036     struct resource *res;
0037
0038     sai_clk = devm_kzalloc(dev, sizeof(*sai_clk), GFP_KERNEL);
0039     if (!sai_clk)
0040         return -ENOMEM;
0041
0042     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0043     base = devm_ioremap_resource(dev, res);
0044     if (IS_ERR(base))
0045         return PTR_ERR(base);
0046
0047     spin_lock_init(&sai_clk->lock);
0048
0049     sai_clk->gate.reg = base + I2S_CSR;
0050     sai_clk->gate.bit_idx = CSR_BCE_BIT;
0051     sai_clk->gate.lock = &sai_clk->lock;
0052
0053     sai_clk->div.reg = base + I2S_CR2;
0054     sai_clk->div.shift = CR2_DIV_SHIFT;
0055     sai_clk->div.width = CR2_DIV_WIDTH;
0056     sai_clk->div.lock = &sai_clk->lock;
0057
0058     /* set clock direction, we are the BCLK master */
0059     writel(CR2_BCD, base + I2S_CR2);
0060
0061     hw = devm_clk_hw_register_composite_pdata(dev, dev->of_node->name,
0062                           &pdata, 1, NULL, NULL,
0063                           &sai_clk->div.hw,
0064                           &clk_divider_ops,
0065                           &sai_clk->gate.hw,
0066                           &clk_gate_ops,
0067                           CLK_SET_RATE_GATE);
0068     if (IS_ERR(hw))
0069         return PTR_ERR(hw);
0070
0071     return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw);
0072 }
0073
0074 static const struct of_device_id of_fsl_sai_clk_ids[] = {
0075     { .compatible = "fsl,vf610-sai-clock" },
0076     { }
0077 };
0078 MODULE_DEVICE_TABLE(of, of_fsl_sai_clk_ids);
0079
0080 static struct platform_driver fsl_sai_clk_driver = {
0081     .probe = fsl_sai_clk_probe,
0082     .driver     = {
0083         .name   = "fsl-sai-clk",
0084         .of_match_table = of_fsl_sai_clk_ids,
0085     },
0086 };
0087 module_platform_driver(fsl_sai_clk_driver);
0088
0089 MODULE_DESCRIPTION("Freescale SAI bitclock-as-a-clock driver");
0090 MODULE_AUTHOR("Michael Walle <michael@walle.cc>");
0091 MODULE_LICENSE("GPL");
0092 MODULE_ALIAS("platform:fsl-sai-clk");