drivers/clk/clk-clps711x.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  *  Cirrus Logic CLPS711X CLK driver
0004  *
0005  *  Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
0006  */
0007
0008 #include <linux/clk-provider.h>
0009 #include <linux/clkdev.h>
0010 #include <linux/io.h>
0011 #include <linux/ioport.h>
0012 #include <linux/of_address.h>
0013 #include <linux/slab.h>
0014 #include <linux/mfd/syscon/clps711x.h>
0015
0016 #include <dt-bindings/clock/clps711x-clock.h>
0017
0018 #define CLPS711X_SYSCON1    (0x0100)
0019 #define CLPS711X_SYSCON2    (0x1100)
0020 #define CLPS711X_SYSFLG2    (CLPS711X_SYSCON2 + SYSFLG_OFFSET)
0021 #define CLPS711X_PLLR       (0xa5a8)
0022
0023 #define CLPS711X_EXT_FREQ   (13000000)
0024 #define CLPS711X_OSC_FREQ   (3686400)
0025
0026 static const struct clk_div_table spi_div_table[] = {
0027     { .val = 0, .div = 32, },
0028     { .val = 1, .div = 8, },
0029     { .val = 2, .div = 2, },
0030     { .val = 3, .div = 1, },
0031     { /* sentinel */ }
0032 };
0033
0034 static const struct clk_div_table timer_div_table[] = {
0035     { .val = 0, .div = 256, },
0036     { .val = 1, .div = 1, },
0037     { /* sentinel */ }
0038 };
0039
0040 struct clps711x_clk {
0041     spinlock_t          lock;
0042     struct clk_hw_onecell_data  clk_data;
0043 };
0044
0045 static void __init clps711x_clk_init_dt(struct device_node *np)
0046 {
0047     u32 tmp, f_cpu, f_pll, f_bus, f_tim, f_pwm, f_spi, fref = 0;
0048     struct clps711x_clk *clps711x_clk;
0049     void __iomem *base;
0050
0051     WARN_ON(of_property_read_u32(np, "startup-frequency", &fref));
0052
0053     base = of_iomap(np, 0);
0054     BUG_ON(!base);
0055
0056     clps711x_clk = kzalloc(struct_size(clps711x_clk, clk_data.hws,
0057                        CLPS711X_CLK_MAX),
0058                    GFP_KERNEL);
0059     BUG_ON(!clps711x_clk);
0060
0061     spin_lock_init(&clps711x_clk->lock);
0062
0063     /* Read PLL multiplier value and sanity check */
0064     tmp = readl(base + CLPS711X_PLLR) >> 24;
0065     if (((tmp >= 10) && (tmp <= 50)) || !fref)
0066         f_pll = DIV_ROUND_UP(CLPS711X_OSC_FREQ * tmp, 2);
0067     else
0068         f_pll = fref;
0069
0070     tmp = readl(base + CLPS711X_SYSFLG2);
0071     if (tmp & SYSFLG2_CKMODE) {
0072         f_cpu = CLPS711X_EXT_FREQ;
0073         f_bus = CLPS711X_EXT_FREQ;
0074         f_spi = DIV_ROUND_CLOSEST(CLPS711X_EXT_FREQ, 96);
0075         f_pll = 0;
0076         f_pwm = DIV_ROUND_CLOSEST(CLPS711X_EXT_FREQ, 128);
0077     } else {
0078         f_cpu = f_pll;
0079         if (f_cpu > 36864000)
0080             f_bus = DIV_ROUND_UP(f_cpu, 2);
0081         else
0082             f_bus = 36864000 / 2;
0083         f_spi = DIV_ROUND_CLOSEST(f_cpu, 576);
0084         f_pwm = DIV_ROUND_CLOSEST(f_cpu, 768);
0085     }
0086
0087     if (tmp & SYSFLG2_CKMODE) {
0088         if (readl(base + CLPS711X_SYSCON2) & SYSCON2_OSTB)
0089             f_tim = DIV_ROUND_CLOSEST(CLPS711X_EXT_FREQ, 26);
0090         else
0091             f_tim = DIV_ROUND_CLOSEST(CLPS711X_EXT_FREQ, 24);
0092     } else
0093         f_tim = DIV_ROUND_CLOSEST(f_cpu, 144);
0094
0095     tmp = readl(base + CLPS711X_SYSCON1);
0096     /* Timer1 in free running mode.
0097      * Counter will wrap around to 0xffff when it underflows
0098      * and will continue to count down.
0099      */
0100     tmp &= ~(SYSCON1_TC1M | SYSCON1_TC1S);
0101     /* Timer2 in prescale mode.
0102      * Value writen is automatically re-loaded when
0103      * the counter underflows.
0104      */
0105     tmp |= SYSCON1_TC2M | SYSCON1_TC2S;
0106     writel(tmp, base + CLPS711X_SYSCON1);
0107
0108     clps711x_clk->clk_data.hws[CLPS711X_CLK_DUMMY] =
0109         clk_hw_register_fixed_rate(NULL, "dummy", NULL, 0, 0);
0110     clps711x_clk->clk_data.hws[CLPS711X_CLK_CPU] =
0111         clk_hw_register_fixed_rate(NULL, "cpu", NULL, 0, f_cpu);
0112     clps711x_clk->clk_data.hws[CLPS711X_CLK_BUS] =
0113         clk_hw_register_fixed_rate(NULL, "bus", NULL, 0, f_bus);
0114     clps711x_clk->clk_data.hws[CLPS711X_CLK_PLL] =
0115         clk_hw_register_fixed_rate(NULL, "pll", NULL, 0, f_pll);
0116     clps711x_clk->clk_data.hws[CLPS711X_CLK_TIMERREF] =
0117         clk_hw_register_fixed_rate(NULL, "timer_ref", NULL, 0, f_tim);
0118     clps711x_clk->clk_data.hws[CLPS711X_CLK_TIMER1] =
0119         clk_hw_register_divider_table(NULL, "timer1", "timer_ref", 0,
0120                        base + CLPS711X_SYSCON1, 5, 1, 0,
0121                        timer_div_table, &clps711x_clk->lock);
0122     clps711x_clk->clk_data.hws[CLPS711X_CLK_TIMER2] =
0123         clk_hw_register_divider_table(NULL, "timer2", "timer_ref", 0,
0124                        base + CLPS711X_SYSCON1, 7, 1, 0,
0125                        timer_div_table, &clps711x_clk->lock);
0126     clps711x_clk->clk_data.hws[CLPS711X_CLK_PWM] =
0127         clk_hw_register_fixed_rate(NULL, "pwm", NULL, 0, f_pwm);
0128     clps711x_clk->clk_data.hws[CLPS711X_CLK_SPIREF] =
0129         clk_hw_register_fixed_rate(NULL, "spi_ref", NULL, 0, f_spi);
0130     clps711x_clk->clk_data.hws[CLPS711X_CLK_SPI] =
0131         clk_hw_register_divider_table(NULL, "spi", "spi_ref", 0,
0132                        base + CLPS711X_SYSCON1, 16, 2, 0,
0133                        spi_div_table, &clps711x_clk->lock);
0134     clps711x_clk->clk_data.hws[CLPS711X_CLK_UART] =
0135         clk_hw_register_fixed_factor(NULL, "uart", "bus", 0, 1, 10);
0136     clps711x_clk->clk_data.hws[CLPS711X_CLK_TICK] =
0137         clk_hw_register_fixed_rate(NULL, "tick", NULL, 0, 64);
0138     for (tmp = 0; tmp < CLPS711X_CLK_MAX; tmp++)
0139         if (IS_ERR(clps711x_clk->clk_data.hws[tmp]))
0140             pr_err("clk %i: register failed with %ld\n",
0141                    tmp, PTR_ERR(clps711x_clk->clk_data.hws[tmp]));
0142
0143     clps711x_clk->clk_data.num = CLPS711X_CLK_MAX;
0144     of_clk_add_hw_provider(np, of_clk_hw_onecell_get,
0145                    &clps711x_clk->clk_data);
0146 }
0147 CLK_OF_DECLARE(clps711x, "cirrus,ep7209-clk", clps711x_clk_init_dt);