drivers/clk/clk-cdce925.c

0001 /*
0002  * Driver for TI Multi PLL CDCE913/925/937/949 clock synthesizer
0003  *
0004  * This driver always connects the Y1 to the input clock, Y2/Y3 to PLL1,
0005  * Y4/Y5 to PLL2, and so on. PLL frequency is set on a first-come-first-serve
0006  * basis. Clients can directly request any frequency that the chip can
0007  * deliver using the standard clk framework. In addition, the device can
0008  * be configured and activated via the devicetree.
0009  *
0010  * Copyright (C) 2014, Topic Embedded Products
0011  * Licenced under GPL
0012  */
0013 #include <linux/clk.h>
0014 #include <linux/clk-provider.h>
0015 #include <linux/delay.h>
0016 #include <linux/module.h>
0017 #include <linux/i2c.h>
0018 #include <linux/regmap.h>
0019 #include <linux/regulator/consumer.h>
0020 #include <linux/slab.h>
0021 #include <linux/gcd.h>
0022
0023 /* Each chip has different number of PLLs and outputs, for example:
0024  * The CECE925 has 2 PLLs which can be routed through dividers to 5 outputs.
0025  * Model this as 2 PLL clocks which are parents to the outputs.
0026  */
0027
0028 enum {
0029     CDCE913,
0030     CDCE925,
0031     CDCE937,
0032     CDCE949,
0033 };
0034
0035 struct clk_cdce925_chip_info {
0036     int num_plls;
0037     int num_outputs;
0038 };
0039
0040 static const struct clk_cdce925_chip_info clk_cdce925_chip_info_tbl[] = {
0041     [CDCE913] = { .num_plls = 1, .num_outputs = 3 },
0042     [CDCE925] = { .num_plls = 2, .num_outputs = 5 },
0043     [CDCE937] = { .num_plls = 3, .num_outputs = 7 },
0044     [CDCE949] = { .num_plls = 4, .num_outputs = 9 },
0045 };
0046
0047 #define MAX_NUMBER_OF_PLLS  4
0048 #define MAX_NUMBER_OF_OUTPUTS   9
0049
0050 #define CDCE925_REG_GLOBAL1 0x01
0051 #define CDCE925_REG_Y1SPIPDIVH  0x02
0052 #define CDCE925_REG_PDIVL   0x03
0053 #define CDCE925_REG_XCSEL   0x05
0054 /* PLL parameters start at 0x10, steps of 0x10 */
0055 #define CDCE925_OFFSET_PLL  0x10
0056 /* Add CDCE925_OFFSET_PLL * (pll) to these registers before sending */
0057 #define CDCE925_PLL_MUX_OUTPUTS 0x14
0058 #define CDCE925_PLL_MULDIV  0x18
0059
0060 #define CDCE925_PLL_FREQUENCY_MIN    80000000ul
0061 #define CDCE925_PLL_FREQUENCY_MAX   230000000ul
0062 struct clk_cdce925_chip;
0063
0064 struct clk_cdce925_output {
0065     struct clk_hw hw;
0066     struct clk_cdce925_chip *chip;
0067     u8 index;
0068     u16 pdiv; /* 1..127 for Y2-Y9; 1..1023 for Y1 */
0069 };
0070 #define to_clk_cdce925_output(_hw) \
0071     container_of(_hw, struct clk_cdce925_output, hw)
0072
0073 struct clk_cdce925_pll {
0074     struct clk_hw hw;
0075     struct clk_cdce925_chip *chip;
0076     u8 index;
0077     u16 m;   /* 1..511 */
0078     u16 n;   /* 1..4095 */
0079 };
0080 #define to_clk_cdce925_pll(_hw) container_of(_hw, struct clk_cdce925_pll, hw)
0081
0082 struct clk_cdce925_chip {
0083     struct regmap *regmap;
0084     struct i2c_client *i2c_client;
0085     const struct clk_cdce925_chip_info *chip_info;
0086     struct clk_cdce925_pll pll[MAX_NUMBER_OF_PLLS];
0087     struct clk_cdce925_output clk[MAX_NUMBER_OF_OUTPUTS];
0088 };
0089
0090 /* ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** */
0091
0092 static unsigned long cdce925_pll_calculate_rate(unsigned long parent_rate,
0093     u16 n, u16 m)
0094 {
0095     if ((!m || !n) || (m == n))
0096         return parent_rate; /* In bypass mode runs at same frequency */
0097     return mult_frac(parent_rate, (unsigned long)n, (unsigned long)m);
0098 }
0099
0100 static unsigned long cdce925_pll_recalc_rate(struct clk_hw *hw,
0101         unsigned long parent_rate)
0102 {
0103     /* Output frequency of PLL is Fout = (Fin/Pdiv)*(N/M) */
0104     struct clk_cdce925_pll *data = to_clk_cdce925_pll(hw);
0105
0106     return cdce925_pll_calculate_rate(parent_rate, data->n, data->m);
0107 }
0108
0109 static void cdce925_pll_find_rate(unsigned long rate,
0110         unsigned long parent_rate, u16 *n, u16 *m)
0111 {
0112     unsigned long un;
0113     unsigned long um;
0114     unsigned long g;
0115
0116     if (rate <= parent_rate) {
0117         /* Can always deliver parent_rate in bypass mode */
0118         rate = parent_rate;
0119         *n = 0;
0120         *m = 0;
0121     } else {
0122         /* In PLL mode, need to apply min/max range */
0123         if (rate < CDCE925_PLL_FREQUENCY_MIN)
0124             rate = CDCE925_PLL_FREQUENCY_MIN;
0125         else if (rate > CDCE925_PLL_FREQUENCY_MAX)
0126             rate = CDCE925_PLL_FREQUENCY_MAX;
0127
0128         g = gcd(rate, parent_rate);
0129         um = parent_rate / g;
0130         un = rate / g;
0131         /* When outside hw range, reduce to fit (rounding errors) */
0132         while ((un > 4095) || (um > 511)) {
0133             un >>= 1;
0134             um >>= 1;
0135         }
0136         if (un == 0)
0137             un = 1;
0138         if (um == 0)
0139             um = 1;
0140
0141         *n = un;
0142         *m = um;
0143     }
0144 }
0145
0146 static long cdce925_pll_round_rate(struct clk_hw *hw, unsigned long rate,
0147         unsigned long *parent_rate)
0148 {
0149     u16 n, m;
0150
0151     cdce925_pll_find_rate(rate, *parent_rate, &n, &m);
0152     return (long)cdce925_pll_calculate_rate(*parent_rate, n, m);
0153 }
0154
0155 static int cdce925_pll_set_rate(struct clk_hw *hw, unsigned long rate,
0156         unsigned long parent_rate)
0157 {
0158     struct clk_cdce925_pll *data = to_clk_cdce925_pll(hw);
0159
0160     if (!rate || (rate == parent_rate)) {
0161         data->m = 0; /* Bypass mode */
0162         data->n = 0;
0163         return 0;
0164     }
0165
0166     if ((rate < CDCE925_PLL_FREQUENCY_MIN) ||
0167         (rate > CDCE925_PLL_FREQUENCY_MAX)) {
0168         pr_debug("%s: rate %lu outside PLL range.\n", __func__, rate);
0169         return -EINVAL;
0170     }
0171
0172     if (rate < parent_rate) {
0173         pr_debug("%s: rate %lu less than parent rate %lu.\n", __func__,
0174             rate, parent_rate);
0175         return -EINVAL;
0176     }
0177
0178     cdce925_pll_find_rate(rate, parent_rate, &data->n, &data->m);
0179     return 0;
0180 }
0181
0182
0183 /* calculate p = max(0, 4 - int(log2 (n/m))) */
0184 static u8 cdce925_pll_calc_p(u16 n, u16 m)
0185 {
0186     u8 p;
0187     u16 r = n / m;
0188
0189     if (r >= 16)
0190         return 0;
0191     p = 4;
0192     while (r > 1) {
0193         r >>= 1;
0194         --p;
0195     }
0196     return p;
0197 }
0198
0199 /* Returns VCO range bits for VCO1_0_RANGE */
0200 static u8 cdce925_pll_calc_range_bits(struct clk_hw *hw, u16 n, u16 m)
0201 {
0202     struct clk *parent = clk_get_parent(hw->clk);
0203     unsigned long rate = clk_get_rate(parent);
0204
0205     rate = mult_frac(rate, (unsigned long)n, (unsigned long)m);
0206     if (rate >= 175000000)
0207         return 0x3;
0208     if (rate >= 150000000)
0209         return 0x02;
0210     if (rate >= 125000000)
0211         return 0x01;
0212     return 0x00;
0213 }
0214
0215 /* I2C clock, hence everything must happen in (un)prepare because this
0216  * may sleep */
0217 static int cdce925_pll_prepare(struct clk_hw *hw)
0218 {
0219     struct clk_cdce925_pll *data = to_clk_cdce925_pll(hw);
0220     u16 n = data->n;
0221     u16 m = data->m;
0222     u16 r;
0223     u8 q;
0224     u8 p;
0225     u16 nn;
0226     u8 pll[4]; /* Bits are spread out over 4 byte registers */
0227     u8 reg_ofs = data->index * CDCE925_OFFSET_PLL;
0228     unsigned i;
0229
0230     if ((!m || !n) || (m == n)) {
0231         /* Set PLL mux to bypass mode, leave the rest as is */
0232         regmap_update_bits(data->chip->regmap,
0233             reg_ofs + CDCE925_PLL_MUX_OUTPUTS, 0x80, 0x80);
0234     } else {
0235         /* According to data sheet: */
0236         /* p = max(0, 4 - int(log2 (n/m))) */
0237         p = cdce925_pll_calc_p(n, m);
0238         /* nn = n * 2^p */
0239         nn = n * BIT(p);
0240         /* q = int(nn/m) */
0241         q = nn / m;
0242         if ((q < 16) || (q > 63)) {
0243             pr_debug("%s invalid q=%d\n", __func__, q);
0244             return -EINVAL;
0245         }
0246         r = nn - (m*q);
0247         if (r > 511) {
0248             pr_debug("%s invalid r=%d\n", __func__, r);
0249             return -EINVAL;
0250         }
0251         pr_debug("%s n=%d m=%d p=%d q=%d r=%d\n", __func__,
0252             n, m, p, q, r);
0253         /* encode into register bits */
0254         pll[0] = n >> 4;
0255         pll[1] = ((n & 0x0F) << 4) | ((r >> 5) & 0x0F);
0256         pll[2] = ((r & 0x1F) << 3) | ((q >> 3) & 0x07);
0257         pll[3] = ((q & 0x07) << 5) | (p << 2) |
0258                 cdce925_pll_calc_range_bits(hw, n, m);
0259         /* Write to registers */
0260         for (i = 0; i < ARRAY_SIZE(pll); ++i)
0261             regmap_write(data->chip->regmap,
0262                 reg_ofs + CDCE925_PLL_MULDIV + i, pll[i]);
0263         /* Enable PLL */
0264         regmap_update_bits(data->chip->regmap,
0265             reg_ofs + CDCE925_PLL_MUX_OUTPUTS, 0x80, 0x00);
0266     }
0267
0268     return 0;
0269 }
0270
0271 static void cdce925_pll_unprepare(struct clk_hw *hw)
0272 {
0273     struct clk_cdce925_pll *data = to_clk_cdce925_pll(hw);
0274     u8 reg_ofs = data->index * CDCE925_OFFSET_PLL;
0275
0276     regmap_update_bits(data->chip->regmap,
0277             reg_ofs + CDCE925_PLL_MUX_OUTPUTS, 0x80, 0x80);
0278 }
0279
0280 static const struct clk_ops cdce925_pll_ops = {
0281     .prepare = cdce925_pll_prepare,
0282     .unprepare = cdce925_pll_unprepare,
0283     .recalc_rate = cdce925_pll_recalc_rate,
0284     .round_rate = cdce925_pll_round_rate,
0285     .set_rate = cdce925_pll_set_rate,
0286 };
0287
0288
0289 static void cdce925_clk_set_pdiv(struct clk_cdce925_output *data, u16 pdiv)
0290 {
0291     switch (data->index) {
0292     case 0:
0293         regmap_update_bits(data->chip->regmap,
0294             CDCE925_REG_Y1SPIPDIVH,
0295             0x03, (pdiv >> 8) & 0x03);
0296         regmap_write(data->chip->regmap, 0x03, pdiv & 0xFF);
0297         break;
0298     case 1:
0299         regmap_update_bits(data->chip->regmap, 0x16, 0x7F, pdiv);
0300         break;
0301     case 2:
0302         regmap_update_bits(data->chip->regmap, 0x17, 0x7F, pdiv);
0303         break;
0304     case 3:
0305         regmap_update_bits(data->chip->regmap, 0x26, 0x7F, pdiv);
0306         break;
0307     case 4:
0308         regmap_update_bits(data->chip->regmap, 0x27, 0x7F, pdiv);
0309         break;
0310     case 5:
0311         regmap_update_bits(data->chip->regmap, 0x36, 0x7F, pdiv);
0312         break;
0313     case 6:
0314         regmap_update_bits(data->chip->regmap, 0x37, 0x7F, pdiv);
0315         break;
0316     case 7:
0317         regmap_update_bits(data->chip->regmap, 0x46, 0x7F, pdiv);
0318         break;
0319     case 8:
0320         regmap_update_bits(data->chip->regmap, 0x47, 0x7F, pdiv);
0321         break;
0322     }
0323 }
0324
0325 static void cdce925_clk_activate(struct clk_cdce925_output *data)
0326 {
0327     switch (data->index) {
0328     case 0:
0329         regmap_update_bits(data->chip->regmap,
0330             CDCE925_REG_Y1SPIPDIVH, 0x0c, 0x0c);
0331         break;
0332     case 1:
0333     case 2:
0334         regmap_update_bits(data->chip->regmap, 0x14, 0x03, 0x03);
0335         break;
0336     case 3:
0337     case 4:
0338         regmap_update_bits(data->chip->regmap, 0x24, 0x03, 0x03);
0339         break;
0340     case 5:
0341     case 6:
0342         regmap_update_bits(data->chip->regmap, 0x34, 0x03, 0x03);
0343         break;
0344     case 7:
0345     case 8:
0346         regmap_update_bits(data->chip->regmap, 0x44, 0x03, 0x03);
0347         break;
0348     }
0349 }
0350
0351 static int cdce925_clk_prepare(struct clk_hw *hw)
0352 {
0353     struct clk_cdce925_output *data = to_clk_cdce925_output(hw);
0354
0355     cdce925_clk_set_pdiv(data, data->pdiv);
0356     cdce925_clk_activate(data);
0357     return 0;
0358 }
0359
0360 static void cdce925_clk_unprepare(struct clk_hw *hw)
0361 {
0362     struct clk_cdce925_output *data = to_clk_cdce925_output(hw);
0363
0364     /* Disable clock by setting divider to "0" */
0365     cdce925_clk_set_pdiv(data, 0);
0366 }
0367
0368 static unsigned long cdce925_clk_recalc_rate(struct clk_hw *hw,
0369         unsigned long parent_rate)
0370 {
0371     struct clk_cdce925_output *data = to_clk_cdce925_output(hw);
0372
0373     if (data->pdiv)
0374         return parent_rate / data->pdiv;
0375     return 0;
0376 }
0377
0378 static u16 cdce925_calc_divider(unsigned long rate,
0379         unsigned long parent_rate)
0380 {
0381     unsigned long divider;
0382
0383     if (!rate)
0384         return 0;
0385     if (rate >= parent_rate)
0386         return 1;
0387
0388     divider = DIV_ROUND_CLOSEST(parent_rate, rate);
0389     if (divider > 0x7F)
0390         divider = 0x7F;
0391
0392     return (u16)divider;
0393 }
0394
0395 static unsigned long cdce925_clk_best_parent_rate(
0396     struct clk_hw *hw, unsigned long rate)
0397 {
0398     struct clk *pll = clk_get_parent(hw->clk);
0399     struct clk *root = clk_get_parent(pll);
0400     unsigned long root_rate = clk_get_rate(root);
0401     unsigned long best_rate_error = rate;
0402     u16 pdiv_min;
0403     u16 pdiv_max;
0404     u16 pdiv_best;
0405     u16 pdiv_now;
0406
0407     if (root_rate % rate == 0)
0408         return root_rate; /* Don't need the PLL, use bypass */
0409
0410     pdiv_min = (u16)max(1ul, DIV_ROUND_UP(CDCE925_PLL_FREQUENCY_MIN, rate));
0411     pdiv_max = (u16)min(127ul, CDCE925_PLL_FREQUENCY_MAX / rate);
0412
0413     if (pdiv_min > pdiv_max)
0414         return 0; /* No can do? */
0415
0416     pdiv_best = pdiv_min;
0417     for (pdiv_now = pdiv_min; pdiv_now < pdiv_max; ++pdiv_now) {
0418         unsigned long target_rate = rate * pdiv_now;
0419         long pll_rate = clk_round_rate(pll, target_rate);
0420         unsigned long actual_rate;
0421         unsigned long rate_error;
0422
0423         if (pll_rate <= 0)
0424             continue;
0425         actual_rate = pll_rate / pdiv_now;
0426         rate_error = abs((long)actual_rate - (long)rate);
0427         if (rate_error < best_rate_error) {
0428             pdiv_best = pdiv_now;
0429             best_rate_error = rate_error;
0430         }
0431         /* TODO: Consider PLL frequency based on smaller n/m values
0432          * and pick the better one if the error is equal */
0433     }
0434
0435     return rate * pdiv_best;
0436 }
0437
0438 static long cdce925_clk_round_rate(struct clk_hw *hw, unsigned long rate,
0439         unsigned long *parent_rate)
0440 {
0441     unsigned long l_parent_rate = *parent_rate;
0442     u16 divider = cdce925_calc_divider(rate, l_parent_rate);
0443
0444     if (l_parent_rate / divider != rate) {
0445         l_parent_rate = cdce925_clk_best_parent_rate(hw, rate);
0446         divider = cdce925_calc_divider(rate, l_parent_rate);
0447         *parent_rate = l_parent_rate;
0448     }
0449
0450     if (divider)
0451         return (long)(l_parent_rate / divider);
0452     return 0;
0453 }
0454
0455 static int cdce925_clk_set_rate(struct clk_hw *hw, unsigned long rate,
0456         unsigned long parent_rate)
0457 {
0458     struct clk_cdce925_output *data = to_clk_cdce925_output(hw);
0459
0460     data->pdiv = cdce925_calc_divider(rate, parent_rate);
0461
0462     return 0;
0463 }
0464
0465 static const struct clk_ops cdce925_clk_ops = {
0466     .prepare = cdce925_clk_prepare,
0467     .unprepare = cdce925_clk_unprepare,
0468     .recalc_rate = cdce925_clk_recalc_rate,
0469     .round_rate = cdce925_clk_round_rate,
0470     .set_rate = cdce925_clk_set_rate,
0471 };
0472
0473
0474 static u16 cdce925_y1_calc_divider(unsigned long rate,
0475         unsigned long parent_rate)
0476 {
0477     unsigned long divider;
0478
0479     if (!rate)
0480         return 0;
0481     if (rate >= parent_rate)
0482         return 1;
0483
0484     divider = DIV_ROUND_CLOSEST(parent_rate, rate);
0485     if (divider > 0x3FF) /* Y1 has 10-bit divider */
0486         divider = 0x3FF;
0487
0488     return (u16)divider;
0489 }
0490
0491 static long cdce925_clk_y1_round_rate(struct clk_hw *hw, unsigned long rate,
0492         unsigned long *parent_rate)
0493 {
0494     unsigned long l_parent_rate = *parent_rate;
0495     u16 divider = cdce925_y1_calc_divider(rate, l_parent_rate);
0496
0497     if (divider)
0498         return (long)(l_parent_rate / divider);
0499     return 0;
0500 }
0501
0502 static int cdce925_clk_y1_set_rate(struct clk_hw *hw, unsigned long rate,
0503         unsigned long parent_rate)
0504 {
0505     struct clk_cdce925_output *data = to_clk_cdce925_output(hw);
0506
0507     data->pdiv = cdce925_y1_calc_divider(rate, parent_rate);
0508
0509     return 0;
0510 }
0511
0512 static const struct clk_ops cdce925_clk_y1_ops = {
0513     .prepare = cdce925_clk_prepare,
0514     .unprepare = cdce925_clk_unprepare,
0515     .recalc_rate = cdce925_clk_recalc_rate,
0516     .round_rate = cdce925_clk_y1_round_rate,
0517     .set_rate = cdce925_clk_y1_set_rate,
0518 };
0519
0520 #define CDCE925_I2C_COMMAND_BLOCK_TRANSFER  0x00
0521 #define CDCE925_I2C_COMMAND_BYTE_TRANSFER   0x80
0522
0523 static int cdce925_regmap_i2c_write(
0524     void *context, const void *data, size_t count)
0525 {
0526     struct device *dev = context;
0527     struct i2c_client *i2c = to_i2c_client(dev);
0528     int ret;
0529     u8 reg_data[2];
0530
0531     if (count != 2)
0532         return -ENOTSUPP;
0533
0534     /* First byte is command code */
0535     reg_data[0] = CDCE925_I2C_COMMAND_BYTE_TRANSFER | ((u8 *)data)[0];
0536     reg_data[1] = ((u8 *)data)[1];
0537
0538     dev_dbg(&i2c->dev, "%s(%zu) %#x %#x\n", __func__, count,
0539             reg_data[0], reg_data[1]);
0540
0541     ret = i2c_master_send(i2c, reg_data, count);
0542     if (likely(ret == count))
0543         return 0;
0544     else if (ret < 0)
0545         return ret;
0546     else
0547         return -EIO;
0548 }
0549
0550 static int cdce925_regmap_i2c_read(void *context,
0551        const void *reg, size_t reg_size, void *val, size_t val_size)
0552 {
0553     struct device *dev = context;
0554     struct i2c_client *i2c = to_i2c_client(dev);
0555     struct i2c_msg xfer[2];
0556     int ret;
0557     u8 reg_data[2];
0558
0559     if (reg_size != 1)
0560         return -ENOTSUPP;
0561
0562     xfer[0].addr = i2c->addr;
0563     xfer[0].flags = 0;
0564     xfer[0].buf = reg_data;
0565     if (val_size == 1) {
0566         reg_data[0] =
0567             CDCE925_I2C_COMMAND_BYTE_TRANSFER | ((u8 *)reg)[0];
0568         xfer[0].len = 1;
0569     } else {
0570         reg_data[0] =
0571             CDCE925_I2C_COMMAND_BLOCK_TRANSFER | ((u8 *)reg)[0];
0572         reg_data[1] = val_size;
0573         xfer[0].len = 2;
0574     }
0575
0576     xfer[1].addr = i2c->addr;
0577     xfer[1].flags = I2C_M_RD;
0578     xfer[1].len = val_size;
0579     xfer[1].buf = val;
0580
0581     ret = i2c_transfer(i2c->adapter, xfer, 2);
0582     if (likely(ret == 2)) {
0583         dev_dbg(&i2c->dev, "%s(%zu, %zu) %#x %#x\n", __func__,
0584                 reg_size, val_size, reg_data[0], *((u8 *)val));
0585         return 0;
0586     } else if (ret < 0)
0587         return ret;
0588     else
0589         return -EIO;
0590 }
0591
0592 static struct clk_hw *
0593 of_clk_cdce925_get(struct of_phandle_args *clkspec, void *_data)
0594 {
0595     struct clk_cdce925_chip *data = _data;
0596     unsigned int idx = clkspec->args[0];
0597
0598     if (idx >= ARRAY_SIZE(data->clk)) {
0599         pr_err("%s: invalid index %u\n", __func__, idx);
0600         return ERR_PTR(-EINVAL);
0601     }
0602
0603     return &data->clk[idx].hw;
0604 }
0605
0606 static void cdce925_regulator_disable(void *regulator)
0607 {
0608     regulator_disable(regulator);
0609 }
0610
0611 static int cdce925_regulator_enable(struct device *dev, const char *name)
0612 {
0613     struct regulator *regulator;
0614     int err;
0615
0616     regulator = devm_regulator_get(dev, name);
0617     if (IS_ERR(regulator))
0618         return PTR_ERR(regulator);
0619
0620     err = regulator_enable(regulator);
0621     if (err) {
0622         dev_err(dev, "Failed to enable %s: %d\n", name, err);
0623         return err;
0624     }
0625
0626     return devm_add_action_or_reset(dev, cdce925_regulator_disable,
0627                     regulator);
0628 }
0629
0630 /* The CDCE925 uses a funky way to read/write registers. Bulk mode is
0631  * just weird, so just use the single byte mode exclusively. */
0632 static struct regmap_bus regmap_cdce925_bus = {
0633     .write = cdce925_regmap_i2c_write,
0634     .read = cdce925_regmap_i2c_read,
0635 };
0636
0637 static const struct i2c_device_id cdce925_id[] = {
0638     { "cdce913", CDCE913 },
0639     { "cdce925", CDCE925 },
0640     { "cdce937", CDCE937 },
0641     { "cdce949", CDCE949 },
0642     { }
0643 };
0644 MODULE_DEVICE_TABLE(i2c, cdce925_id);
0645
0646 static int cdce925_probe(struct i2c_client *client)
0647 {
0648     struct clk_cdce925_chip *data;
0649     struct device_node *node = client->dev.of_node;
0650     const struct i2c_device_id *id = i2c_match_id(cdce925_id, client);
0651     const char *parent_name;
0652     const char *pll_clk_name[MAX_NUMBER_OF_PLLS] = {NULL,};
0653     struct clk_init_data init;
0654     u32 value;
0655     int i;
0656     int err;
0657     struct device_node *np_output;
0658     char child_name[6];
0659     struct regmap_config config = {
0660         .name = "configuration0",
0661         .reg_bits = 8,
0662         .val_bits = 8,
0663         .cache_type = REGCACHE_RBTREE,
0664     };
0665
0666     dev_dbg(&client->dev, "%s\n", __func__);
0667
0668     err = cdce925_regulator_enable(&client->dev, "vdd");
0669     if (err)
0670         return err;
0671
0672     err = cdce925_regulator_enable(&client->dev, "vddout");
0673     if (err)
0674         return err;
0675
0676     data = devm_kzalloc(&client->dev, sizeof(*data), GFP_KERNEL);
0677     if (!data)
0678         return -ENOMEM;
0679
0680     data->i2c_client = client;
0681     data->chip_info = &clk_cdce925_chip_info_tbl[id->driver_data];
0682     config.max_register = CDCE925_OFFSET_PLL +
0683         data->chip_info->num_plls * 0x10 - 1;
0684     data->regmap = devm_regmap_init(&client->dev, &regmap_cdce925_bus,
0685             &client->dev, &config);
0686     if (IS_ERR(data->regmap)) {
0687         dev_err(&client->dev, "failed to allocate register map\n");
0688         return PTR_ERR(data->regmap);
0689     }
0690     i2c_set_clientdata(client, data);
0691
0692     parent_name = of_clk_get_parent_name(node, 0);
0693     if (!parent_name) {
0694         dev_err(&client->dev, "missing parent clock\n");
0695         return -ENODEV;
0696     }
0697     dev_dbg(&client->dev, "parent is: %s\n", parent_name);
0698
0699     if (of_property_read_u32(node, "xtal-load-pf", &value) == 0)
0700         regmap_write(data->regmap,
0701             CDCE925_REG_XCSEL, (value << 3) & 0xF8);
0702     /* PWDN bit */
0703     regmap_update_bits(data->regmap, CDCE925_REG_GLOBAL1, BIT(4), 0);
0704
0705     /* Set input source for Y1 to be the XTAL */
0706     regmap_update_bits(data->regmap, 0x02, BIT(7), 0);
0707
0708     init.ops = &cdce925_pll_ops;
0709     init.flags = 0;
0710     init.parent_names = &parent_name;
0711     init.num_parents = 1;
0712
0713     /* Register PLL clocks */
0714     for (i = 0; i < data->chip_info->num_plls; ++i) {
0715         pll_clk_name[i] = kasprintf(GFP_KERNEL, "%pOFn.pll%d",
0716             client->dev.of_node, i);
0717         init.name = pll_clk_name[i];
0718         data->pll[i].chip = data;
0719         data->pll[i].hw.init = &init;
0720         data->pll[i].index = i;
0721         err = devm_clk_hw_register(&client->dev, &data->pll[i].hw);
0722         if (err) {
0723             dev_err(&client->dev, "Failed register PLL %d\n", i);
0724             goto error;
0725         }
0726         sprintf(child_name, "PLL%d", i+1);
0727         np_output = of_get_child_by_name(node, child_name);
0728         if (!np_output)
0729             continue;
0730         if (!of_property_read_u32(np_output,
0731             "clock-frequency", &value)) {
0732             err = clk_set_rate(data->pll[i].hw.clk, value);
0733             if (err)
0734                 dev_err(&client->dev,
0735                     "unable to set PLL frequency %ud\n",
0736                     value);
0737         }
0738         if (!of_property_read_u32(np_output,
0739             "spread-spectrum", &value)) {
0740             u8 flag = of_property_read_bool(np_output,
0741                 "spread-spectrum-center") ? 0x80 : 0x00;
0742             regmap_update_bits(data->regmap,
0743                 0x16 + (i*CDCE925_OFFSET_PLL),
0744                 0x80, flag);
0745             regmap_update_bits(data->regmap,
0746                 0x12 + (i*CDCE925_OFFSET_PLL),
0747                 0x07, value & 0x07);
0748         }
0749         of_node_put(np_output);
0750     }
0751
0752     /* Register output clock Y1 */
0753     init.ops = &cdce925_clk_y1_ops;
0754     init.flags = 0;
0755     init.num_parents = 1;
0756     init.parent_names = &parent_name; /* Mux Y1 to input */
0757     init.name = kasprintf(GFP_KERNEL, "%pOFn.Y1", client->dev.of_node);
0758     data->clk[0].chip = data;
0759     data->clk[0].hw.init = &init;
0760     data->clk[0].index = 0;
0761     data->clk[0].pdiv = 1;
0762     err = devm_clk_hw_register(&client->dev, &data->clk[0].hw);
0763     kfree(init.name); /* clock framework made a copy of the name */
0764     if (err) {
0765         dev_err(&client->dev, "clock registration Y1 failed\n");
0766         goto error;
0767     }
0768
0769     /* Register output clocks Y2 .. Y5*/
0770     init.ops = &cdce925_clk_ops;
0771     init.flags = CLK_SET_RATE_PARENT;
0772     init.num_parents = 1;
0773     for (i = 1; i < data->chip_info->num_outputs; ++i) {
0774         init.name = kasprintf(GFP_KERNEL, "%pOFn.Y%d",
0775             client->dev.of_node, i+1);
0776         data->clk[i].chip = data;
0777         data->clk[i].hw.init = &init;
0778         data->clk[i].index = i;
0779         data->clk[i].pdiv = 1;
0780         switch (i) {
0781         case 1:
0782         case 2:
0783             /* Mux Y2/3 to PLL1 */
0784             init.parent_names = &pll_clk_name[0];
0785             break;
0786         case 3:
0787         case 4:
0788             /* Mux Y4/5 to PLL2 */
0789             init.parent_names = &pll_clk_name[1];
0790             break;
0791         case 5:
0792         case 6:
0793             /* Mux Y6/7 to PLL3 */
0794             init.parent_names = &pll_clk_name[2];
0795             break;
0796         case 7:
0797         case 8:
0798             /* Mux Y8/9 to PLL4 */
0799             init.parent_names = &pll_clk_name[3];
0800             break;
0801         }
0802         err = devm_clk_hw_register(&client->dev, &data->clk[i].hw);
0803         kfree(init.name); /* clock framework made a copy of the name */
0804         if (err) {
0805             dev_err(&client->dev, "clock registration failed\n");
0806             goto error;
0807         }
0808     }
0809
0810     /* Register the output clocks */
0811     err = of_clk_add_hw_provider(client->dev.of_node, of_clk_cdce925_get,
0812                   data);
0813     if (err)
0814         dev_err(&client->dev, "unable to add OF clock provider\n");
0815
0816     err = 0;
0817
0818 error:
0819     for (i = 0; i < data->chip_info->num_plls; ++i)
0820         /* clock framework made a copy of the name */
0821         kfree(pll_clk_name[i]);
0822
0823     return err;
0824 }
0825
0826 static const struct of_device_id clk_cdce925_of_match[] = {
0827     { .compatible = "ti,cdce913" },
0828     { .compatible = "ti,cdce925" },
0829     { .compatible = "ti,cdce937" },
0830     { .compatible = "ti,cdce949" },
0831     { },
0832 };
0833 MODULE_DEVICE_TABLE(of, clk_cdce925_of_match);
0834
0835 static struct i2c_driver cdce925_driver = {
0836     .driver = {
0837         .name = "cdce925",
0838         .of_match_table = of_match_ptr(clk_cdce925_of_match),
0839     },
0840     .probe_new  = cdce925_probe,
0841     .id_table   = cdce925_id,
0842 };
0843 module_i2c_driver(cdce925_driver);
0844
0845 MODULE_AUTHOR("Mike Looijmans <mike.looijmans@topic.nl>");
0846 MODULE_DESCRIPTION("TI CDCE913/925/937/949 driver");
0847 MODULE_LICENSE("GPL");