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0010 #include <linux/clk.h>
0011 #include <linux/clk-provider.h>
0012 #include <linux/delay.h>
0013 #include <linux/i2c.h>
0014 #include <linux/interrupt.h>
0015 #include <linux/mod_devicetable.h>
0016 #include <linux/module.h>
0017 #include <linux/of.h>
0018 #include <linux/rational.h>
0019 #include <linux/regmap.h>
0020 #include <linux/slab.h>
0021
0022 #define CDCE706_CLKIN_CLOCK 10
0023 #define CDCE706_CLKIN_SOURCE 11
0024 #define CDCE706_PLL_M_LOW(pll) (1 + 3 * (pll))
0025 #define CDCE706_PLL_N_LOW(pll) (2 + 3 * (pll))
0026 #define CDCE706_PLL_HI(pll) (3 + 3 * (pll))
0027 #define CDCE706_PLL_MUX 3
0028 #define CDCE706_PLL_FVCO 6
0029 #define CDCE706_DIVIDER(div) (13 + (div))
0030 #define CDCE706_CLKOUT(out) (19 + (out))
0031
0032 #define CDCE706_CLKIN_CLOCK_MASK 0x10
0033 #define CDCE706_CLKIN_SOURCE_SHIFT 6
0034 #define CDCE706_CLKIN_SOURCE_MASK 0xc0
0035 #define CDCE706_CLKIN_SOURCE_LVCMOS 0x40
0036
0037 #define CDCE706_PLL_MUX_MASK(pll) (0x80 >> (pll))
0038 #define CDCE706_PLL_LOW_M_MASK 0xff
0039 #define CDCE706_PLL_LOW_N_MASK 0xff
0040 #define CDCE706_PLL_HI_M_MASK 0x1
0041 #define CDCE706_PLL_HI_N_MASK 0x1e
0042 #define CDCE706_PLL_HI_N_SHIFT 1
0043 #define CDCE706_PLL_M_MAX 0x1ff
0044 #define CDCE706_PLL_N_MAX 0xfff
0045 #define CDCE706_PLL_FVCO_MASK(pll) (0x80 >> (pll))
0046 #define CDCE706_PLL_FREQ_MIN 80000000
0047 #define CDCE706_PLL_FREQ_MAX 300000000
0048 #define CDCE706_PLL_FREQ_HI 180000000
0049
0050 #define CDCE706_DIVIDER_PLL(div) (9 + (div) - ((div) > 2) - ((div) > 4))
0051 #define CDCE706_DIVIDER_PLL_SHIFT(div) ((div) < 2 ? 5 : 3 * ((div) & 1))
0052 #define CDCE706_DIVIDER_PLL_MASK(div) (0x7 << CDCE706_DIVIDER_PLL_SHIFT(div))
0053 #define CDCE706_DIVIDER_DIVIDER_MASK 0x7f
0054 #define CDCE706_DIVIDER_DIVIDER_MAX 0x7f
0055
0056 #define CDCE706_CLKOUT_DIVIDER_MASK 0x7
0057 #define CDCE706_CLKOUT_ENABLE_MASK 0x8
0058
0059 static const struct regmap_config cdce706_regmap_config = {
0060 .reg_bits = 8,
0061 .val_bits = 8,
0062 .val_format_endian = REGMAP_ENDIAN_NATIVE,
0063 };
0064
0065 #define to_hw_data(phw) (container_of((phw), struct cdce706_hw_data, hw))
0066
0067 struct cdce706_hw_data {
0068 struct cdce706_dev_data *dev_data;
0069 unsigned idx;
0070 unsigned parent;
0071 struct clk_hw hw;
0072 unsigned div;
0073 unsigned mul;
0074 unsigned mux;
0075 };
0076
0077 struct cdce706_dev_data {
0078 struct i2c_client *client;
0079 struct regmap *regmap;
0080 struct clk *clkin_clk[2];
0081 const char *clkin_name[2];
0082 struct cdce706_hw_data clkin[1];
0083 struct cdce706_hw_data pll[3];
0084 struct cdce706_hw_data divider[6];
0085 struct cdce706_hw_data clkout[6];
0086 };
0087
0088 static const char * const cdce706_source_name[] = {
0089 "clk_in0", "clk_in1",
0090 };
0091
0092 static const char * const cdce706_clkin_name[] = {
0093 "clk_in",
0094 };
0095
0096 static const char * const cdce706_pll_name[] = {
0097 "pll1", "pll2", "pll3",
0098 };
0099
0100 static const char * const cdce706_divider_parent_name[] = {
0101 "clk_in", "pll1", "pll2", "pll2", "pll3",
0102 };
0103
0104 static const char *cdce706_divider_name[] = {
0105 "p0", "p1", "p2", "p3", "p4", "p5",
0106 };
0107
0108 static const char * const cdce706_clkout_name[] = {
0109 "clk_out0", "clk_out1", "clk_out2", "clk_out3", "clk_out4", "clk_out5",
0110 };
0111
0112 static int cdce706_reg_read(struct cdce706_dev_data *dev_data, unsigned reg,
0113 unsigned *val)
0114 {
0115 int rc = regmap_read(dev_data->regmap, reg | 0x80, val);
0116
0117 if (rc < 0)
0118 dev_err(&dev_data->client->dev, "error reading reg %u", reg);
0119 return rc;
0120 }
0121
0122 static int cdce706_reg_write(struct cdce706_dev_data *dev_data, unsigned reg,
0123 unsigned val)
0124 {
0125 int rc = regmap_write(dev_data->regmap, reg | 0x80, val);
0126
0127 if (rc < 0)
0128 dev_err(&dev_data->client->dev, "error writing reg %u", reg);
0129 return rc;
0130 }
0131
0132 static int cdce706_reg_update(struct cdce706_dev_data *dev_data, unsigned reg,
0133 unsigned mask, unsigned val)
0134 {
0135 int rc = regmap_update_bits(dev_data->regmap, reg | 0x80, mask, val);
0136
0137 if (rc < 0)
0138 dev_err(&dev_data->client->dev, "error updating reg %u", reg);
0139 return rc;
0140 }
0141
0142 static int cdce706_clkin_set_parent(struct clk_hw *hw, u8 index)
0143 {
0144 struct cdce706_hw_data *hwd = to_hw_data(hw);
0145
0146 hwd->parent = index;
0147 return 0;
0148 }
0149
0150 static u8 cdce706_clkin_get_parent(struct clk_hw *hw)
0151 {
0152 struct cdce706_hw_data *hwd = to_hw_data(hw);
0153
0154 return hwd->parent;
0155 }
0156
0157 static const struct clk_ops cdce706_clkin_ops = {
0158 .set_parent = cdce706_clkin_set_parent,
0159 .get_parent = cdce706_clkin_get_parent,
0160 };
0161
0162 static unsigned long cdce706_pll_recalc_rate(struct clk_hw *hw,
0163 unsigned long parent_rate)
0164 {
0165 struct cdce706_hw_data *hwd = to_hw_data(hw);
0166
0167 dev_dbg(&hwd->dev_data->client->dev,
0168 "%s, pll: %d, mux: %d, mul: %u, div: %u\n",
0169 __func__, hwd->idx, hwd->mux, hwd->mul, hwd->div);
0170
0171 if (!hwd->mux) {
0172 if (hwd->div && hwd->mul) {
0173 u64 res = (u64)parent_rate * hwd->mul;
0174
0175 do_div(res, hwd->div);
0176 return res;
0177 }
0178 } else {
0179 if (hwd->div)
0180 return parent_rate / hwd->div;
0181 }
0182 return 0;
0183 }
0184
0185 static long cdce706_pll_round_rate(struct clk_hw *hw, unsigned long rate,
0186 unsigned long *parent_rate)
0187 {
0188 struct cdce706_hw_data *hwd = to_hw_data(hw);
0189 unsigned long mul, div;
0190 u64 res;
0191
0192 dev_dbg(&hwd->dev_data->client->dev,
0193 "%s, rate: %lu, parent_rate: %lu\n",
0194 __func__, rate, *parent_rate);
0195
0196 rational_best_approximation(rate, *parent_rate,
0197 CDCE706_PLL_N_MAX, CDCE706_PLL_M_MAX,
0198 &mul, &div);
0199 hwd->mul = mul;
0200 hwd->div = div;
0201
0202 dev_dbg(&hwd->dev_data->client->dev,
0203 "%s, pll: %d, mul: %lu, div: %lu\n",
0204 __func__, hwd->idx, mul, div);
0205
0206 res = (u64)*parent_rate * hwd->mul;
0207 do_div(res, hwd->div);
0208 return res;
0209 }
0210
0211 static int cdce706_pll_set_rate(struct clk_hw *hw, unsigned long rate,
0212 unsigned long parent_rate)
0213 {
0214 struct cdce706_hw_data *hwd = to_hw_data(hw);
0215 unsigned long mul = hwd->mul, div = hwd->div;
0216 int err;
0217
0218 dev_dbg(&hwd->dev_data->client->dev,
0219 "%s, pll: %d, mul: %lu, div: %lu\n",
0220 __func__, hwd->idx, mul, div);
0221
0222 err = cdce706_reg_update(hwd->dev_data,
0223 CDCE706_PLL_HI(hwd->idx),
0224 CDCE706_PLL_HI_M_MASK | CDCE706_PLL_HI_N_MASK,
0225 ((div >> 8) & CDCE706_PLL_HI_M_MASK) |
0226 ((mul >> (8 - CDCE706_PLL_HI_N_SHIFT)) &
0227 CDCE706_PLL_HI_N_MASK));
0228 if (err < 0)
0229 return err;
0230
0231 err = cdce706_reg_write(hwd->dev_data,
0232 CDCE706_PLL_M_LOW(hwd->idx),
0233 div & CDCE706_PLL_LOW_M_MASK);
0234 if (err < 0)
0235 return err;
0236
0237 err = cdce706_reg_write(hwd->dev_data,
0238 CDCE706_PLL_N_LOW(hwd->idx),
0239 mul & CDCE706_PLL_LOW_N_MASK);
0240 if (err < 0)
0241 return err;
0242
0243 err = cdce706_reg_update(hwd->dev_data,
0244 CDCE706_PLL_FVCO,
0245 CDCE706_PLL_FVCO_MASK(hwd->idx),
0246 rate > CDCE706_PLL_FREQ_HI ?
0247 CDCE706_PLL_FVCO_MASK(hwd->idx) : 0);
0248 return err;
0249 }
0250
0251 static const struct clk_ops cdce706_pll_ops = {
0252 .recalc_rate = cdce706_pll_recalc_rate,
0253 .round_rate = cdce706_pll_round_rate,
0254 .set_rate = cdce706_pll_set_rate,
0255 };
0256
0257 static int cdce706_divider_set_parent(struct clk_hw *hw, u8 index)
0258 {
0259 struct cdce706_hw_data *hwd = to_hw_data(hw);
0260
0261 if (hwd->parent == index)
0262 return 0;
0263 hwd->parent = index;
0264 return cdce706_reg_update(hwd->dev_data,
0265 CDCE706_DIVIDER_PLL(hwd->idx),
0266 CDCE706_DIVIDER_PLL_MASK(hwd->idx),
0267 index << CDCE706_DIVIDER_PLL_SHIFT(hwd->idx));
0268 }
0269
0270 static u8 cdce706_divider_get_parent(struct clk_hw *hw)
0271 {
0272 struct cdce706_hw_data *hwd = to_hw_data(hw);
0273
0274 return hwd->parent;
0275 }
0276
0277 static unsigned long cdce706_divider_recalc_rate(struct clk_hw *hw,
0278 unsigned long parent_rate)
0279 {
0280 struct cdce706_hw_data *hwd = to_hw_data(hw);
0281
0282 dev_dbg(&hwd->dev_data->client->dev,
0283 "%s, divider: %d, div: %u\n",
0284 __func__, hwd->idx, hwd->div);
0285 if (hwd->div)
0286 return parent_rate / hwd->div;
0287 return 0;
0288 }
0289
0290 static long cdce706_divider_round_rate(struct clk_hw *hw, unsigned long rate,
0291 unsigned long *parent_rate)
0292 {
0293 struct cdce706_hw_data *hwd = to_hw_data(hw);
0294 struct cdce706_dev_data *cdce = hwd->dev_data;
0295 unsigned long mul, div;
0296
0297 dev_dbg(&hwd->dev_data->client->dev,
0298 "%s, rate: %lu, parent_rate: %lu\n",
0299 __func__, rate, *parent_rate);
0300
0301 rational_best_approximation(rate, *parent_rate,
0302 1, CDCE706_DIVIDER_DIVIDER_MAX,
0303 &mul, &div);
0304 if (!mul)
0305 div = CDCE706_DIVIDER_DIVIDER_MAX;
0306
0307 if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
0308 unsigned long best_diff = rate;
0309 unsigned long best_div = 0;
0310 struct clk *gp_clk = cdce->clkin_clk[cdce->clkin[0].parent];
0311 unsigned long gp_rate = gp_clk ? clk_get_rate(gp_clk) : 0;
0312
0313 for (div = CDCE706_PLL_FREQ_MIN / rate; best_diff &&
0314 div <= CDCE706_PLL_FREQ_MAX / rate; ++div) {
0315 unsigned long n, m;
0316 unsigned long diff;
0317 unsigned long div_rate;
0318 u64 div_rate64;
0319
0320 if (rate * div < CDCE706_PLL_FREQ_MIN)
0321 continue;
0322
0323 rational_best_approximation(rate * div, gp_rate,
0324 CDCE706_PLL_N_MAX,
0325 CDCE706_PLL_M_MAX,
0326 &n, &m);
0327 div_rate64 = (u64)gp_rate * n;
0328 do_div(div_rate64, m);
0329 do_div(div_rate64, div);
0330 div_rate = div_rate64;
0331 diff = max(div_rate, rate) - min(div_rate, rate);
0332
0333 if (diff < best_diff) {
0334 best_diff = diff;
0335 best_div = div;
0336 dev_dbg(&hwd->dev_data->client->dev,
0337 "%s, %lu * %lu / %lu / %lu = %lu\n",
0338 __func__, gp_rate, n, m, div, div_rate);
0339 }
0340 }
0341
0342 div = best_div;
0343
0344 dev_dbg(&hwd->dev_data->client->dev,
0345 "%s, altering parent rate: %lu -> %lu\n",
0346 __func__, *parent_rate, rate * div);
0347 *parent_rate = rate * div;
0348 }
0349 hwd->div = div;
0350
0351 dev_dbg(&hwd->dev_data->client->dev,
0352 "%s, divider: %d, div: %lu\n",
0353 __func__, hwd->idx, div);
0354
0355 return *parent_rate / div;
0356 }
0357
0358 static int cdce706_divider_set_rate(struct clk_hw *hw, unsigned long rate,
0359 unsigned long parent_rate)
0360 {
0361 struct cdce706_hw_data *hwd = to_hw_data(hw);
0362
0363 dev_dbg(&hwd->dev_data->client->dev,
0364 "%s, divider: %d, div: %u\n",
0365 __func__, hwd->idx, hwd->div);
0366
0367 return cdce706_reg_update(hwd->dev_data,
0368 CDCE706_DIVIDER(hwd->idx),
0369 CDCE706_DIVIDER_DIVIDER_MASK,
0370 hwd->div);
0371 }
0372
0373 static const struct clk_ops cdce706_divider_ops = {
0374 .set_parent = cdce706_divider_set_parent,
0375 .get_parent = cdce706_divider_get_parent,
0376 .recalc_rate = cdce706_divider_recalc_rate,
0377 .round_rate = cdce706_divider_round_rate,
0378 .set_rate = cdce706_divider_set_rate,
0379 };
0380
0381 static int cdce706_clkout_prepare(struct clk_hw *hw)
0382 {
0383 struct cdce706_hw_data *hwd = to_hw_data(hw);
0384
0385 return cdce706_reg_update(hwd->dev_data, CDCE706_CLKOUT(hwd->idx),
0386 CDCE706_CLKOUT_ENABLE_MASK,
0387 CDCE706_CLKOUT_ENABLE_MASK);
0388 }
0389
0390 static void cdce706_clkout_unprepare(struct clk_hw *hw)
0391 {
0392 struct cdce706_hw_data *hwd = to_hw_data(hw);
0393
0394 cdce706_reg_update(hwd->dev_data, CDCE706_CLKOUT(hwd->idx),
0395 CDCE706_CLKOUT_ENABLE_MASK, 0);
0396 }
0397
0398 static int cdce706_clkout_set_parent(struct clk_hw *hw, u8 index)
0399 {
0400 struct cdce706_hw_data *hwd = to_hw_data(hw);
0401
0402 if (hwd->parent == index)
0403 return 0;
0404 hwd->parent = index;
0405 return cdce706_reg_update(hwd->dev_data,
0406 CDCE706_CLKOUT(hwd->idx),
0407 CDCE706_CLKOUT_ENABLE_MASK, index);
0408 }
0409
0410 static u8 cdce706_clkout_get_parent(struct clk_hw *hw)
0411 {
0412 struct cdce706_hw_data *hwd = to_hw_data(hw);
0413
0414 return hwd->parent;
0415 }
0416
0417 static unsigned long cdce706_clkout_recalc_rate(struct clk_hw *hw,
0418 unsigned long parent_rate)
0419 {
0420 return parent_rate;
0421 }
0422
0423 static long cdce706_clkout_round_rate(struct clk_hw *hw, unsigned long rate,
0424 unsigned long *parent_rate)
0425 {
0426 *parent_rate = rate;
0427 return rate;
0428 }
0429
0430 static int cdce706_clkout_set_rate(struct clk_hw *hw, unsigned long rate,
0431 unsigned long parent_rate)
0432 {
0433 return 0;
0434 }
0435
0436 static const struct clk_ops cdce706_clkout_ops = {
0437 .prepare = cdce706_clkout_prepare,
0438 .unprepare = cdce706_clkout_unprepare,
0439 .set_parent = cdce706_clkout_set_parent,
0440 .get_parent = cdce706_clkout_get_parent,
0441 .recalc_rate = cdce706_clkout_recalc_rate,
0442 .round_rate = cdce706_clkout_round_rate,
0443 .set_rate = cdce706_clkout_set_rate,
0444 };
0445
0446 static int cdce706_register_hw(struct cdce706_dev_data *cdce,
0447 struct cdce706_hw_data *hw, unsigned num_hw,
0448 const char * const *clk_names,
0449 struct clk_init_data *init)
0450 {
0451 unsigned i;
0452 int ret;
0453
0454 for (i = 0; i < num_hw; ++i, ++hw) {
0455 init->name = clk_names[i];
0456 hw->dev_data = cdce;
0457 hw->idx = i;
0458 hw->hw.init = init;
0459 ret = devm_clk_hw_register(&cdce->client->dev,
0460 &hw->hw);
0461 if (ret) {
0462 dev_err(&cdce->client->dev, "Failed to register %s\n",
0463 clk_names[i]);
0464 return ret;
0465 }
0466 }
0467 return 0;
0468 }
0469
0470 static int cdce706_register_clkin(struct cdce706_dev_data *cdce)
0471 {
0472 struct clk_init_data init = {
0473 .ops = &cdce706_clkin_ops,
0474 .parent_names = cdce->clkin_name,
0475 .num_parents = ARRAY_SIZE(cdce->clkin_name),
0476 };
0477 unsigned i;
0478 int ret;
0479 unsigned clock, source;
0480
0481 for (i = 0; i < ARRAY_SIZE(cdce->clkin_name); ++i) {
0482 struct clk *parent = devm_clk_get(&cdce->client->dev,
0483 cdce706_source_name[i]);
0484
0485 if (IS_ERR(parent)) {
0486 cdce->clkin_name[i] = cdce706_source_name[i];
0487 } else {
0488 cdce->clkin_name[i] = __clk_get_name(parent);
0489 cdce->clkin_clk[i] = parent;
0490 }
0491 }
0492
0493 ret = cdce706_reg_read(cdce, CDCE706_CLKIN_SOURCE, &source);
0494 if (ret < 0)
0495 return ret;
0496 if ((source & CDCE706_CLKIN_SOURCE_MASK) ==
0497 CDCE706_CLKIN_SOURCE_LVCMOS) {
0498 ret = cdce706_reg_read(cdce, CDCE706_CLKIN_CLOCK, &clock);
0499 if (ret < 0)
0500 return ret;
0501 cdce->clkin[0].parent = !!(clock & CDCE706_CLKIN_CLOCK_MASK);
0502 }
0503
0504 ret = cdce706_register_hw(cdce, cdce->clkin,
0505 ARRAY_SIZE(cdce->clkin),
0506 cdce706_clkin_name, &init);
0507 return ret;
0508 }
0509
0510 static int cdce706_register_plls(struct cdce706_dev_data *cdce)
0511 {
0512 struct clk_init_data init = {
0513 .ops = &cdce706_pll_ops,
0514 .parent_names = cdce706_clkin_name,
0515 .num_parents = ARRAY_SIZE(cdce706_clkin_name),
0516 };
0517 unsigned i;
0518 int ret;
0519 unsigned mux;
0520
0521 ret = cdce706_reg_read(cdce, CDCE706_PLL_MUX, &mux);
0522 if (ret < 0)
0523 return ret;
0524
0525 for (i = 0; i < ARRAY_SIZE(cdce->pll); ++i) {
0526 unsigned m, n, v;
0527
0528 ret = cdce706_reg_read(cdce, CDCE706_PLL_M_LOW(i), &m);
0529 if (ret < 0)
0530 return ret;
0531 ret = cdce706_reg_read(cdce, CDCE706_PLL_N_LOW(i), &n);
0532 if (ret < 0)
0533 return ret;
0534 ret = cdce706_reg_read(cdce, CDCE706_PLL_HI(i), &v);
0535 if (ret < 0)
0536 return ret;
0537 cdce->pll[i].div = m | ((v & CDCE706_PLL_HI_M_MASK) << 8);
0538 cdce->pll[i].mul = n | ((v & CDCE706_PLL_HI_N_MASK) <<
0539 (8 - CDCE706_PLL_HI_N_SHIFT));
0540 cdce->pll[i].mux = mux & CDCE706_PLL_MUX_MASK(i);
0541 dev_dbg(&cdce->client->dev,
0542 "%s: i: %u, div: %u, mul: %u, mux: %d\n", __func__, i,
0543 cdce->pll[i].div, cdce->pll[i].mul, cdce->pll[i].mux);
0544 }
0545
0546 ret = cdce706_register_hw(cdce, cdce->pll,
0547 ARRAY_SIZE(cdce->pll),
0548 cdce706_pll_name, &init);
0549 return ret;
0550 }
0551
0552 static int cdce706_register_dividers(struct cdce706_dev_data *cdce)
0553 {
0554 struct clk_init_data init = {
0555 .ops = &cdce706_divider_ops,
0556 .parent_names = cdce706_divider_parent_name,
0557 .num_parents = ARRAY_SIZE(cdce706_divider_parent_name),
0558 .flags = CLK_SET_RATE_PARENT,
0559 };
0560 unsigned i;
0561 int ret;
0562
0563 for (i = 0; i < ARRAY_SIZE(cdce->divider); ++i) {
0564 unsigned val;
0565
0566 ret = cdce706_reg_read(cdce, CDCE706_DIVIDER_PLL(i), &val);
0567 if (ret < 0)
0568 return ret;
0569 cdce->divider[i].parent =
0570 (val & CDCE706_DIVIDER_PLL_MASK(i)) >>
0571 CDCE706_DIVIDER_PLL_SHIFT(i);
0572
0573 ret = cdce706_reg_read(cdce, CDCE706_DIVIDER(i), &val);
0574 if (ret < 0)
0575 return ret;
0576 cdce->divider[i].div = val & CDCE706_DIVIDER_DIVIDER_MASK;
0577 dev_dbg(&cdce->client->dev,
0578 "%s: i: %u, parent: %u, div: %u\n", __func__, i,
0579 cdce->divider[i].parent, cdce->divider[i].div);
0580 }
0581
0582 ret = cdce706_register_hw(cdce, cdce->divider,
0583 ARRAY_SIZE(cdce->divider),
0584 cdce706_divider_name, &init);
0585 return ret;
0586 }
0587
0588 static int cdce706_register_clkouts(struct cdce706_dev_data *cdce)
0589 {
0590 struct clk_init_data init = {
0591 .ops = &cdce706_clkout_ops,
0592 .parent_names = cdce706_divider_name,
0593 .num_parents = ARRAY_SIZE(cdce706_divider_name),
0594 .flags = CLK_SET_RATE_PARENT,
0595 };
0596 unsigned i;
0597 int ret;
0598
0599 for (i = 0; i < ARRAY_SIZE(cdce->clkout); ++i) {
0600 unsigned val;
0601
0602 ret = cdce706_reg_read(cdce, CDCE706_CLKOUT(i), &val);
0603 if (ret < 0)
0604 return ret;
0605 cdce->clkout[i].parent = val & CDCE706_CLKOUT_DIVIDER_MASK;
0606 dev_dbg(&cdce->client->dev,
0607 "%s: i: %u, parent: %u\n", __func__, i,
0608 cdce->clkout[i].parent);
0609 }
0610
0611 return cdce706_register_hw(cdce, cdce->clkout,
0612 ARRAY_SIZE(cdce->clkout),
0613 cdce706_clkout_name, &init);
0614 }
0615
0616 static struct clk_hw *
0617 of_clk_cdce_get(struct of_phandle_args *clkspec, void *data)
0618 {
0619 struct cdce706_dev_data *cdce = data;
0620 unsigned int idx = clkspec->args[0];
0621
0622 if (idx >= ARRAY_SIZE(cdce->clkout)) {
0623 pr_err("%s: invalid index %u\n", __func__, idx);
0624 return ERR_PTR(-EINVAL);
0625 }
0626
0627 return &cdce->clkout[idx].hw;
0628 }
0629
0630 static int cdce706_probe(struct i2c_client *client)
0631 {
0632 struct i2c_adapter *adapter = client->adapter;
0633 struct cdce706_dev_data *cdce;
0634 int ret;
0635
0636 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA))
0637 return -EIO;
0638
0639 cdce = devm_kzalloc(&client->dev, sizeof(*cdce), GFP_KERNEL);
0640 if (!cdce)
0641 return -ENOMEM;
0642
0643 cdce->client = client;
0644 cdce->regmap = devm_regmap_init_i2c(client, &cdce706_regmap_config);
0645 if (IS_ERR(cdce->regmap)) {
0646 dev_err(&client->dev, "Failed to initialize regmap\n");
0647 return -EINVAL;
0648 }
0649
0650 i2c_set_clientdata(client, cdce);
0651
0652 ret = cdce706_register_clkin(cdce);
0653 if (ret < 0)
0654 return ret;
0655 ret = cdce706_register_plls(cdce);
0656 if (ret < 0)
0657 return ret;
0658 ret = cdce706_register_dividers(cdce);
0659 if (ret < 0)
0660 return ret;
0661 ret = cdce706_register_clkouts(cdce);
0662 if (ret < 0)
0663 return ret;
0664 return of_clk_add_hw_provider(client->dev.of_node, of_clk_cdce_get,
0665 cdce);
0666 }
0667
0668 static int cdce706_remove(struct i2c_client *client)
0669 {
0670 of_clk_del_provider(client->dev.of_node);
0671 return 0;
0672 }
0673
0674
0675 #ifdef CONFIG_OF
0676 static const struct of_device_id cdce706_dt_match[] = {
0677 { .compatible = "ti,cdce706" },
0678 { },
0679 };
0680 MODULE_DEVICE_TABLE(of, cdce706_dt_match);
0681 #endif
0682
0683 static const struct i2c_device_id cdce706_id[] = {
0684 { "cdce706", 0 },
0685 { }
0686 };
0687 MODULE_DEVICE_TABLE(i2c, cdce706_id);
0688
0689 static struct i2c_driver cdce706_i2c_driver = {
0690 .driver = {
0691 .name = "cdce706",
0692 .of_match_table = of_match_ptr(cdce706_dt_match),
0693 },
0694 .probe_new = cdce706_probe,
0695 .remove = cdce706_remove,
0696 .id_table = cdce706_id,
0697 };
0698 module_i2c_driver(cdce706_i2c_driver);
0699
0700 MODULE_AUTHOR("Max Filippov <jcmvbkbc@gmail.com>");
0701 MODULE_DESCRIPTION("TI CDCE 706 clock synthesizer driver");
0702 MODULE_LICENSE("GPL");
