drivers/clk/clk-aspeed.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Structures used by ASPEED clock drivers
0004  *
0005  * Copyright 2019 IBM Corp.
0006  */
0007
0008 #include <linux/clk-provider.h>
0009 #include <linux/kernel.h>
0010 #include <linux/reset-controller.h>
0011 #include <linux/spinlock.h>
0012
0013 struct clk_div_table;
0014 struct regmap;
0015
0016 /**
0017  * struct aspeed_gate_data - Aspeed gated clocks
0018  * @clock_idx: bit used to gate this clock in the clock register
0019  * @reset_idx: bit used to reset this IP in the reset register. -1 if no
0020  *             reset is required when enabling the clock
0021  * @name: the clock name
0022  * @parent_name: the name of the parent clock
0023  * @flags: standard clock framework flags
0024  */
0025 struct aspeed_gate_data {
0026     u8      clock_idx;
0027     s8      reset_idx;
0028     const char  *name;
0029     const char  *parent_name;
0030     unsigned long   flags;
0031 };
0032
0033 /**
0034  * struct aspeed_clk_gate - Aspeed specific clk_gate structure
0035  * @hw:     handle between common and hardware-specific interfaces
0036  * @reg:    register controlling gate
0037  * @clock_idx:  bit used to gate this clock in the clock register
0038  * @reset_idx:  bit used to reset this IP in the reset register. -1 if no
0039  *      reset is required when enabling the clock
0040  * @flags:  hardware-specific flags
0041  * @lock:   register lock
0042  *
0043  * Some of the clocks in the Aspeed SoC must be put in reset before enabling.
0044  * This modified version of clk_gate allows an optional reset bit to be
0045  * specified.
0046  */
0047 struct aspeed_clk_gate {
0048     struct clk_hw   hw;
0049     struct regmap   *map;
0050     u8      clock_idx;
0051     s8      reset_idx;
0052     u8      flags;
0053     spinlock_t  *lock;
0054 };
0055
0056 #define to_aspeed_clk_gate(_hw) container_of(_hw, struct aspeed_clk_gate, hw)
0057
0058 /**
0059  * struct aspeed_reset - Aspeed reset controller
0060  * @map: regmap to access the containing system controller
0061  * @rcdev: reset controller device
0062  */
0063 struct aspeed_reset {
0064     struct regmap           *map;
0065     struct reset_controller_dev rcdev;
0066 };
0067
0068 #define to_aspeed_reset(p) container_of((p), struct aspeed_reset, rcdev)
0069
0070 /**
0071  * struct aspeed_clk_soc_data - Aspeed SoC specific divisor information
0072  * @div_table: Common divider lookup table
0073  * @eclk_div_table: Divider lookup table for ECLK
0074  * @mac_div_table: Divider lookup table for MAC (Ethernet) clocks
0075  * @calc_pll: Callback to maculate common PLL settings
0076  */
0077 struct aspeed_clk_soc_data {
0078     const struct clk_div_table *div_table;
0079     const struct clk_div_table *eclk_div_table;
0080     const struct clk_div_table *mac_div_table;
0081     struct clk_hw *(*calc_pll)(const char *name, u32 val);
0082 };