drivers/clk/clk-asm9260.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2014 Oleksij Rempel <linux@rempel-privat.de>.
0004  */
0005
0006 #include <linux/clk.h>
0007 #include <linux/clkdev.h>
0008 #include <linux/err.h>
0009 #include <linux/io.h>
0010 #include <linux/clk-provider.h>
0011 #include <linux/spinlock.h>
0012 #include <linux/of.h>
0013 #include <linux/of_address.h>
0014 #include <dt-bindings/clock/alphascale,asm9260.h>
0015
0016 #define HW_AHBCLKCTRL0      0x0020
0017 #define HW_AHBCLKCTRL1      0x0030
0018 #define HW_SYSPLLCTRL       0x0100
0019 #define HW_MAINCLKSEL       0x0120
0020 #define HW_MAINCLKUEN       0x0124
0021 #define HW_UARTCLKSEL       0x0128
0022 #define HW_UARTCLKUEN       0x012c
0023 #define HW_I2S0CLKSEL       0x0130
0024 #define HW_I2S0CLKUEN       0x0134
0025 #define HW_I2S1CLKSEL       0x0138
0026 #define HW_I2S1CLKUEN       0x013c
0027 #define HW_WDTCLKSEL        0x0160
0028 #define HW_WDTCLKUEN        0x0164
0029 #define HW_CLKOUTCLKSEL     0x0170
0030 #define HW_CLKOUTCLKUEN     0x0174
0031 #define HW_CPUCLKDIV        0x017c
0032 #define HW_SYSAHBCLKDIV     0x0180
0033 #define HW_I2S0MCLKDIV      0x0190
0034 #define HW_I2S0SCLKDIV      0x0194
0035 #define HW_I2S1MCLKDIV      0x0188
0036 #define HW_I2S1SCLKDIV      0x018c
0037 #define HW_UART0CLKDIV      0x0198
0038 #define HW_UART1CLKDIV      0x019c
0039 #define HW_UART2CLKDIV      0x01a0
0040 #define HW_UART3CLKDIV      0x01a4
0041 #define HW_UART4CLKDIV      0x01a8
0042 #define HW_UART5CLKDIV      0x01ac
0043 #define HW_UART6CLKDIV      0x01b0
0044 #define HW_UART7CLKDIV      0x01b4
0045 #define HW_UART8CLKDIV      0x01b8
0046 #define HW_UART9CLKDIV      0x01bc
0047 #define HW_SPI0CLKDIV       0x01c0
0048 #define HW_SPI1CLKDIV       0x01c4
0049 #define HW_QUADSPICLKDIV    0x01c8
0050 #define HW_SSP0CLKDIV       0x01d0
0051 #define HW_NANDCLKDIV       0x01d4
0052 #define HW_TRACECLKDIV      0x01e0
0053 #define HW_CAMMCLKDIV       0x01e8
0054 #define HW_WDTCLKDIV        0x01ec
0055 #define HW_CLKOUTCLKDIV     0x01f4
0056 #define HW_MACCLKDIV        0x01f8
0057 #define HW_LCDCLKDIV        0x01fc
0058 #define HW_ADCANACLKDIV     0x0200
0059
0060 static struct clk_hw_onecell_data *clk_data;
0061 static DEFINE_SPINLOCK(asm9260_clk_lock);
0062
0063 struct asm9260_div_clk {
0064     unsigned int idx;
0065     const char *name;
0066     const char *parent_name;
0067     u32 reg;
0068 };
0069
0070 struct asm9260_gate_data {
0071     unsigned int idx;
0072     const char *name;
0073     const char *parent_name;
0074     u32 reg;
0075     u8 bit_idx;
0076     unsigned long flags;
0077 };
0078
0079 struct asm9260_mux_clock {
0080     u8          mask;
0081     u32         *table;
0082     const char      *name;
0083     const char      **parent_names;
0084     u8          num_parents;
0085     unsigned long       offset;
0086     unsigned long       flags;
0087 };
0088
0089 static void __iomem *base;
0090
0091 static const struct asm9260_div_clk asm9260_div_clks[] __initconst = {
0092     { CLKID_SYS_CPU,    "cpu_div", "main_gate", HW_CPUCLKDIV },
0093     { CLKID_SYS_AHB,    "ahb_div", "cpu_div", HW_SYSAHBCLKDIV },
0094
0095     /* i2s has two deviders: one for only external mclk and internal
0096      * devider for all clks. */
0097     { CLKID_SYS_I2S0M,  "i2s0m_div", "i2s0_mclk",  HW_I2S0MCLKDIV },
0098     { CLKID_SYS_I2S1M,  "i2s1m_div", "i2s1_mclk",  HW_I2S1MCLKDIV },
0099     { CLKID_SYS_I2S0S,  "i2s0s_div", "i2s0_gate",  HW_I2S0SCLKDIV },
0100     { CLKID_SYS_I2S1S,  "i2s1s_div", "i2s0_gate",  HW_I2S1SCLKDIV },
0101
0102     { CLKID_SYS_UART0,  "uart0_div", "uart_gate", HW_UART0CLKDIV },
0103     { CLKID_SYS_UART1,  "uart1_div", "uart_gate", HW_UART1CLKDIV },
0104     { CLKID_SYS_UART2,  "uart2_div", "uart_gate", HW_UART2CLKDIV },
0105     { CLKID_SYS_UART3,  "uart3_div", "uart_gate", HW_UART3CLKDIV },
0106     { CLKID_SYS_UART4,  "uart4_div", "uart_gate", HW_UART4CLKDIV },
0107     { CLKID_SYS_UART5,  "uart5_div", "uart_gate", HW_UART5CLKDIV },
0108     { CLKID_SYS_UART6,  "uart6_div", "uart_gate", HW_UART6CLKDIV },
0109     { CLKID_SYS_UART7,  "uart7_div", "uart_gate", HW_UART7CLKDIV },
0110     { CLKID_SYS_UART8,  "uart8_div", "uart_gate", HW_UART8CLKDIV },
0111     { CLKID_SYS_UART9,  "uart9_div", "uart_gate", HW_UART9CLKDIV },
0112
0113     { CLKID_SYS_SPI0,   "spi0_div", "main_gate", HW_SPI0CLKDIV },
0114     { CLKID_SYS_SPI1,   "spi1_div", "main_gate", HW_SPI1CLKDIV },
0115     { CLKID_SYS_QUADSPI,    "quadspi_div",  "main_gate", HW_QUADSPICLKDIV },
0116     { CLKID_SYS_SSP0,   "ssp0_div", "main_gate", HW_SSP0CLKDIV },
0117     { CLKID_SYS_NAND,   "nand_div", "main_gate", HW_NANDCLKDIV },
0118     { CLKID_SYS_TRACE,  "trace_div",    "main_gate", HW_TRACECLKDIV },
0119     { CLKID_SYS_CAMM,   "camm_div", "main_gate", HW_CAMMCLKDIV },
0120     { CLKID_SYS_MAC,    "mac_div",  "main_gate", HW_MACCLKDIV },
0121     { CLKID_SYS_LCD,    "lcd_div",  "main_gate", HW_LCDCLKDIV },
0122     { CLKID_SYS_ADCANA, "adcana_div",   "main_gate", HW_ADCANACLKDIV },
0123
0124     { CLKID_SYS_WDT,    "wdt_div",  "wdt_gate",    HW_WDTCLKDIV },
0125     { CLKID_SYS_CLKOUT, "clkout_div",   "clkout_gate", HW_CLKOUTCLKDIV },
0126 };
0127
0128 static const struct asm9260_gate_data asm9260_mux_gates[] __initconst = {
0129     { 0, "main_gate",   "main_mux", HW_MAINCLKUEN,  0 },
0130     { 0, "uart_gate",   "uart_mux", HW_UARTCLKUEN,  0 },
0131     { 0, "i2s0_gate",   "i2s0_mux", HW_I2S0CLKUEN,  0 },
0132     { 0, "i2s1_gate",   "i2s1_mux", HW_I2S1CLKUEN,  0 },
0133     { 0, "wdt_gate",    "wdt_mux",  HW_WDTCLKUEN,   0 },
0134     { 0, "clkout_gate", "clkout_mux",   HW_CLKOUTCLKUEN, 0 },
0135 };
0136 static const struct asm9260_gate_data asm9260_ahb_gates[] __initconst = {
0137     /* ahb gates */
0138     { CLKID_AHB_ROM,    "rom",      "ahb_div",
0139         HW_AHBCLKCTRL0, 1, CLK_IGNORE_UNUSED},
0140     { CLKID_AHB_RAM,    "ram",      "ahb_div",
0141         HW_AHBCLKCTRL0, 2, CLK_IGNORE_UNUSED},
0142     { CLKID_AHB_GPIO,   "gpio",     "ahb_div",
0143         HW_AHBCLKCTRL0, 4 },
0144     { CLKID_AHB_MAC,    "mac",      "ahb_div",
0145         HW_AHBCLKCTRL0, 5 },
0146     { CLKID_AHB_EMI,    "emi",      "ahb_div",
0147         HW_AHBCLKCTRL0, 6, CLK_IGNORE_UNUSED},
0148     { CLKID_AHB_USB0,   "usb0",     "ahb_div",
0149         HW_AHBCLKCTRL0, 7 },
0150     { CLKID_AHB_USB1,   "usb1",     "ahb_div",
0151         HW_AHBCLKCTRL0, 8 },
0152     { CLKID_AHB_DMA0,   "dma0",     "ahb_div",
0153         HW_AHBCLKCTRL0, 9 },
0154     { CLKID_AHB_DMA1,   "dma1",     "ahb_div",
0155         HW_AHBCLKCTRL0, 10 },
0156     { CLKID_AHB_UART0,  "uart0",    "ahb_div",
0157         HW_AHBCLKCTRL0, 11 },
0158     { CLKID_AHB_UART1,  "uart1",    "ahb_div",
0159         HW_AHBCLKCTRL0, 12 },
0160     { CLKID_AHB_UART2,  "uart2",    "ahb_div",
0161         HW_AHBCLKCTRL0, 13 },
0162     { CLKID_AHB_UART3,  "uart3",    "ahb_div",
0163         HW_AHBCLKCTRL0, 14 },
0164     { CLKID_AHB_UART4,  "uart4",    "ahb_div",
0165         HW_AHBCLKCTRL0, 15 },
0166     { CLKID_AHB_UART5,  "uart5",    "ahb_div",
0167         HW_AHBCLKCTRL0, 16 },
0168     { CLKID_AHB_UART6,  "uart6",    "ahb_div",
0169         HW_AHBCLKCTRL0, 17 },
0170     { CLKID_AHB_UART7,  "uart7",    "ahb_div",
0171         HW_AHBCLKCTRL0, 18 },
0172     { CLKID_AHB_UART8,  "uart8",    "ahb_div",
0173         HW_AHBCLKCTRL0, 19 },
0174     { CLKID_AHB_UART9,  "uart9",    "ahb_div",
0175         HW_AHBCLKCTRL0, 20 },
0176     { CLKID_AHB_I2S0,   "i2s0",     "ahb_div",
0177         HW_AHBCLKCTRL0, 21 },
0178     { CLKID_AHB_I2C0,   "i2c0",     "ahb_div",
0179         HW_AHBCLKCTRL0, 22 },
0180     { CLKID_AHB_I2C1,   "i2c1",     "ahb_div",
0181         HW_AHBCLKCTRL0, 23 },
0182     { CLKID_AHB_SSP0,   "ssp0",     "ahb_div",
0183         HW_AHBCLKCTRL0, 24 },
0184     { CLKID_AHB_IOCONFIG,   "ioconf",   "ahb_div",
0185         HW_AHBCLKCTRL0, 25 },
0186     { CLKID_AHB_WDT,    "wdt",      "ahb_div",
0187         HW_AHBCLKCTRL0, 26 },
0188     { CLKID_AHB_CAN0,   "can0",     "ahb_div",
0189         HW_AHBCLKCTRL0, 27 },
0190     { CLKID_AHB_CAN1,   "can1",     "ahb_div",
0191         HW_AHBCLKCTRL0, 28 },
0192     { CLKID_AHB_MPWM,   "mpwm",     "ahb_div",
0193         HW_AHBCLKCTRL0, 29 },
0194     { CLKID_AHB_SPI0,   "spi0",     "ahb_div",
0195         HW_AHBCLKCTRL0, 30 },
0196     { CLKID_AHB_SPI1,   "spi1",     "ahb_div",
0197         HW_AHBCLKCTRL0, 31 },
0198
0199     { CLKID_AHB_QEI,    "qei",      "ahb_div",
0200         HW_AHBCLKCTRL1, 0 },
0201     { CLKID_AHB_QUADSPI0,   "quadspi0", "ahb_div",
0202         HW_AHBCLKCTRL1, 1 },
0203     { CLKID_AHB_CAMIF,  "capmif",   "ahb_div",
0204         HW_AHBCLKCTRL1, 2 },
0205     { CLKID_AHB_LCDIF,  "lcdif",    "ahb_div",
0206         HW_AHBCLKCTRL1, 3 },
0207     { CLKID_AHB_TIMER0, "timer0",   "ahb_div",
0208         HW_AHBCLKCTRL1, 4 },
0209     { CLKID_AHB_TIMER1, "timer1",   "ahb_div",
0210         HW_AHBCLKCTRL1, 5 },
0211     { CLKID_AHB_TIMER2, "timer2",   "ahb_div",
0212         HW_AHBCLKCTRL1, 6 },
0213     { CLKID_AHB_TIMER3, "timer3",   "ahb_div",
0214         HW_AHBCLKCTRL1, 7 },
0215     { CLKID_AHB_IRQ,    "irq",      "ahb_div",
0216         HW_AHBCLKCTRL1, 8, CLK_IGNORE_UNUSED},
0217     { CLKID_AHB_RTC,    "rtc",      "ahb_div",
0218         HW_AHBCLKCTRL1, 9 },
0219     { CLKID_AHB_NAND,   "nand",     "ahb_div",
0220         HW_AHBCLKCTRL1, 10 },
0221     { CLKID_AHB_ADC0,   "adc0",     "ahb_div",
0222         HW_AHBCLKCTRL1, 11 },
0223     { CLKID_AHB_LED,    "led",      "ahb_div",
0224         HW_AHBCLKCTRL1, 12 },
0225     { CLKID_AHB_DAC0,   "dac0",     "ahb_div",
0226         HW_AHBCLKCTRL1, 13 },
0227     { CLKID_AHB_LCD,    "lcd",      "ahb_div",
0228         HW_AHBCLKCTRL1, 14 },
0229     { CLKID_AHB_I2S1,   "i2s1",     "ahb_div",
0230         HW_AHBCLKCTRL1, 15 },
0231     { CLKID_AHB_MAC1,   "mac1",     "ahb_div",
0232         HW_AHBCLKCTRL1, 16 },
0233 };
0234
0235 static const char __initdata *main_mux_p[] =   { NULL, NULL };
0236 static const char __initdata *i2s0_mux_p[] =   { NULL, NULL, "i2s0m_div"};
0237 static const char __initdata *i2s1_mux_p[] =   { NULL, NULL, "i2s1m_div"};
0238 static const char __initdata *clkout_mux_p[] = { NULL, NULL, "rtc"};
0239 static u32 three_mux_table[] = {0, 1, 3};
0240
0241 static struct asm9260_mux_clock asm9260_mux_clks[] __initdata = {
0242     { 1, three_mux_table, "main_mux",   main_mux_p,
0243         ARRAY_SIZE(main_mux_p), HW_MAINCLKSEL, },
0244     { 1, three_mux_table, "uart_mux",   main_mux_p,
0245         ARRAY_SIZE(main_mux_p), HW_UARTCLKSEL, },
0246     { 1, three_mux_table, "wdt_mux",    main_mux_p,
0247         ARRAY_SIZE(main_mux_p), HW_WDTCLKSEL, },
0248     { 3, three_mux_table, "i2s0_mux",   i2s0_mux_p,
0249         ARRAY_SIZE(i2s0_mux_p), HW_I2S0CLKSEL, },
0250     { 3, three_mux_table, "i2s1_mux",   i2s1_mux_p,
0251         ARRAY_SIZE(i2s1_mux_p), HW_I2S1CLKSEL, },
0252     { 3, three_mux_table, "clkout_mux", clkout_mux_p,
0253         ARRAY_SIZE(clkout_mux_p), HW_CLKOUTCLKSEL, },
0254 };
0255
0256 static void __init asm9260_acc_init(struct device_node *np)
0257 {
0258     struct clk_hw *hw;
0259     struct clk_hw **hws;
0260     const char *ref_clk, *pll_clk = "pll";
0261     u32 rate;
0262     int n;
0263
0264     clk_data = kzalloc(struct_size(clk_data, hws, MAX_CLKS), GFP_KERNEL);
0265     if (!clk_data)
0266         return;
0267     clk_data->num = MAX_CLKS;
0268     hws = clk_data->hws;
0269
0270     base = of_io_request_and_map(np, 0, np->name);
0271     if (IS_ERR(base))
0272         panic("%pOFn: unable to map resource", np);
0273
0274     /* register pll */
0275     rate = (ioread32(base + HW_SYSPLLCTRL) & 0xffff) * 1000000;
0276
0277     /* TODO: Convert to DT parent scheme */
0278     ref_clk = of_clk_get_parent_name(np, 0);
0279     hw = __clk_hw_register_fixed_rate(NULL, NULL, pll_clk,
0280             ref_clk, NULL, NULL, 0, rate, 0,
0281             CLK_FIXED_RATE_PARENT_ACCURACY);
0282
0283     if (IS_ERR(hw))
0284         panic("%pOFn: can't register REFCLK. Check DT!", np);
0285
0286     for (n = 0; n < ARRAY_SIZE(asm9260_mux_clks); n++) {
0287         const struct asm9260_mux_clock *mc = &asm9260_mux_clks[n];
0288
0289         mc->parent_names[0] = ref_clk;
0290         mc->parent_names[1] = pll_clk;
0291         hw = clk_hw_register_mux_table(NULL, mc->name, mc->parent_names,
0292                 mc->num_parents, mc->flags, base + mc->offset,
0293                 0, mc->mask, 0, mc->table, &asm9260_clk_lock);
0294     }
0295
0296     /* clock mux gate cells */
0297     for (n = 0; n < ARRAY_SIZE(asm9260_mux_gates); n++) {
0298         const struct asm9260_gate_data *gd = &asm9260_mux_gates[n];
0299
0300         hw = clk_hw_register_gate(NULL, gd->name,
0301             gd->parent_name, gd->flags | CLK_SET_RATE_PARENT,
0302             base + gd->reg, gd->bit_idx, 0, &asm9260_clk_lock);
0303     }
0304
0305     /* clock div cells */
0306     for (n = 0; n < ARRAY_SIZE(asm9260_div_clks); n++) {
0307         const struct asm9260_div_clk *dc = &asm9260_div_clks[n];
0308
0309         hws[dc->idx] = clk_hw_register_divider(NULL, dc->name,
0310                 dc->parent_name, CLK_SET_RATE_PARENT,
0311                 base + dc->reg, 0, 8, CLK_DIVIDER_ONE_BASED,
0312                 &asm9260_clk_lock);
0313     }
0314
0315     /* clock ahb gate cells */
0316     for (n = 0; n < ARRAY_SIZE(asm9260_ahb_gates); n++) {
0317         const struct asm9260_gate_data *gd = &asm9260_ahb_gates[n];
0318
0319         hws[gd->idx] = clk_hw_register_gate(NULL, gd->name,
0320                 gd->parent_name, gd->flags, base + gd->reg,
0321                 gd->bit_idx, 0, &asm9260_clk_lock);
0322     }
0323
0324     /* check for errors on leaf clocks */
0325     for (n = 0; n < MAX_CLKS; n++) {
0326         if (!IS_ERR(hws[n]))
0327             continue;
0328
0329         pr_err("%pOF: Unable to register leaf clock %d\n",
0330                 np, n);
0331         goto fail;
0332     }
0333
0334     /* register clk-provider */
0335     of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
0336     return;
0337 fail:
0338     iounmap(base);
0339 }
0340 CLK_OF_DECLARE(asm9260_acc, "alphascale,asm9260-clock-controller",
0341         asm9260_acc_init);