clk/berlin/berlin2-avpll.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (c) 2014 Marvell Technology Group Ltd.
0004  *
0005  * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
0006  * Alexandre Belloni <alexandre.belloni@free-electrons.com>
0007  */
0008 #include <linux/clk-provider.h>
0009 #include <linux/io.h>
0010 #include <linux/kernel.h>
0011 #include <linux/of.h>
0012 #include <linux/of_address.h>
0013 #include <linux/slab.h>
0014
0015 #include "berlin2-avpll.h"
0016
0017 /*
0018  * Berlin2 SoCs comprise up to two PLLs called AVPLL built upon a
0019  * VCO with 8 channels each, channel 8 is the odd-one-out and does
0020  * not provide mul/div.
0021  *
0022  * Unfortunately, its registers are not named but just numbered. To
0023  * get in at least some kind of structure, we split each AVPLL into
0024  * the VCOs and each channel into separate clock drivers.
0025  *
0026  * Also, here and there the VCO registers are a bit different with
0027  * respect to bit shifts. Make sure to add a comment for those.
0028  */
0029 #define NUM_CHANNELS    8
0030
0031 #define AVPLL_CTRL(x)       ((x) * 0x4)
0032
0033 #define VCO_CTRL0       AVPLL_CTRL(0)
0034 /* BG2/BG2CDs VCO_B has an additional shift of 4 for its VCO_CTRL0 reg */
0035 #define  VCO_RESET      BIT(0)
0036 #define  VCO_POWERUP        BIT(1)
0037 #define  VCO_INTERPOL_SHIFT 2
0038 #define  VCO_INTERPOL_MASK  (0xf << VCO_INTERPOL_SHIFT)
0039 #define  VCO_REG1V45_SEL_SHIFT  6
0040 #define  VCO_REG1V45_SEL(x) ((x) << VCO_REG1V45_SEL_SHIFT)
0041 #define  VCO_REG1V45_SEL_1V40   VCO_REG1V45_SEL(0)
0042 #define  VCO_REG1V45_SEL_1V45   VCO_REG1V45_SEL(1)
0043 #define  VCO_REG1V45_SEL_1V50   VCO_REG1V45_SEL(2)
0044 #define  VCO_REG1V45_SEL_1V55   VCO_REG1V45_SEL(3)
0045 #define  VCO_REG1V45_SEL_MASK   VCO_REG1V45_SEL(3)
0046 #define  VCO_REG0V9_SEL_SHIFT   8
0047 #define  VCO_REG0V9_SEL_MASK    (0xf << VCO_REG0V9_SEL_SHIFT)
0048 #define  VCO_VTHCAL_SHIFT   12
0049 #define  VCO_VTHCAL(x)      ((x) << VCO_VTHCAL_SHIFT)
0050 #define  VCO_VTHCAL_0V90    VCO_VTHCAL(0)
0051 #define  VCO_VTHCAL_0V95    VCO_VTHCAL(1)
0052 #define  VCO_VTHCAL_1V00    VCO_VTHCAL(2)
0053 #define  VCO_VTHCAL_1V05    VCO_VTHCAL(3)
0054 #define  VCO_VTHCAL_MASK    VCO_VTHCAL(3)
0055 #define  VCO_KVCOEXT_SHIFT  14
0056 #define  VCO_KVCOEXT_MASK   (0x3 << VCO_KVCOEXT_SHIFT)
0057 #define  VCO_KVCOEXT_ENABLE BIT(17)
0058 #define  VCO_V2IEXT_SHIFT   18
0059 #define  VCO_V2IEXT_MASK    (0xf << VCO_V2IEXT_SHIFT)
0060 #define  VCO_V2IEXT_ENABLE  BIT(22)
0061 #define  VCO_SPEED_SHIFT    23
0062 #define  VCO_SPEED(x)       ((x) << VCO_SPEED_SHIFT)
0063 #define  VCO_SPEED_1G08_1G21    VCO_SPEED(0)
0064 #define  VCO_SPEED_1G21_1G40    VCO_SPEED(1)
0065 #define  VCO_SPEED_1G40_1G61    VCO_SPEED(2)
0066 #define  VCO_SPEED_1G61_1G86    VCO_SPEED(3)
0067 #define  VCO_SPEED_1G86_2G00    VCO_SPEED(4)
0068 #define  VCO_SPEED_2G00_2G22    VCO_SPEED(5)
0069 #define  VCO_SPEED_2G22     VCO_SPEED(6)
0070 #define  VCO_SPEED_MASK     VCO_SPEED(0x7)
0071 #define  VCO_CLKDET_ENABLE  BIT(26)
0072 #define VCO_CTRL1       AVPLL_CTRL(1)
0073 #define  VCO_REFDIV_SHIFT   0
0074 #define  VCO_REFDIV(x)      ((x) << VCO_REFDIV_SHIFT)
0075 #define  VCO_REFDIV_1       VCO_REFDIV(0)
0076 #define  VCO_REFDIV_2       VCO_REFDIV(1)
0077 #define  VCO_REFDIV_4       VCO_REFDIV(2)
0078 #define  VCO_REFDIV_3       VCO_REFDIV(3)
0079 #define  VCO_REFDIV_MASK    VCO_REFDIV(0x3f)
0080 #define  VCO_FBDIV_SHIFT    6
0081 #define  VCO_FBDIV(x)       ((x) << VCO_FBDIV_SHIFT)
0082 #define  VCO_FBDIV_MASK     VCO_FBDIV(0xff)
0083 #define  VCO_ICP_SHIFT      14
0084 /* PLL Charge Pump Current = 10uA * (x + 1) */
0085 #define  VCO_ICP(x)     ((x) << VCO_ICP_SHIFT)
0086 #define  VCO_ICP_MASK       VCO_ICP(0xf)
0087 #define  VCO_LOAD_CAP       BIT(18)
0088 #define  VCO_CALIBRATION_START  BIT(19)
0089 #define VCO_FREQOFFSETn(x)  AVPLL_CTRL(3 + (x))
0090 #define  VCO_FREQOFFSET_MASK    0x7ffff
0091 #define VCO_CTRL10      AVPLL_CTRL(10)
0092 #define  VCO_POWERUP_CH1    BIT(20)
0093 #define VCO_CTRL11      AVPLL_CTRL(11)
0094 #define VCO_CTRL12      AVPLL_CTRL(12)
0095 #define VCO_CTRL13      AVPLL_CTRL(13)
0096 #define VCO_CTRL14      AVPLL_CTRL(14)
0097 #define VCO_CTRL15      AVPLL_CTRL(15)
0098 #define VCO_SYNC1n(x)       AVPLL_CTRL(15 + (x))
0099 #define  VCO_SYNC1_MASK     0x1ffff
0100 #define VCO_SYNC2n(x)       AVPLL_CTRL(23 + (x))
0101 #define  VCO_SYNC2_MASK     0x1ffff
0102 #define VCO_CTRL30      AVPLL_CTRL(30)
0103 #define  VCO_DPLL_CH1_ENABLE    BIT(17)
0104
0105 struct berlin2_avpll_vco {
0106     struct clk_hw hw;
0107     void __iomem *base;
0108     u8 flags;
0109 };
0110
0111 #define to_avpll_vco(hw) container_of(hw, struct berlin2_avpll_vco, hw)
0112
0113 static int berlin2_avpll_vco_is_enabled(struct clk_hw *hw)
0114 {
0115     struct berlin2_avpll_vco *vco = to_avpll_vco(hw);
0116     u32 reg;
0117
0118     reg = readl_relaxed(vco->base + VCO_CTRL0);
0119     if (vco->flags & BERLIN2_AVPLL_BIT_QUIRK)
0120         reg >>= 4;
0121
0122     return !!(reg & VCO_POWERUP);
0123 }
0124
0125 static int berlin2_avpll_vco_enable(struct clk_hw *hw)
0126 {
0127     struct berlin2_avpll_vco *vco = to_avpll_vco(hw);
0128     u32 reg;
0129
0130     reg = readl_relaxed(vco->base + VCO_CTRL0);
0131     if (vco->flags & BERLIN2_AVPLL_BIT_QUIRK)
0132         reg |= VCO_POWERUP << 4;
0133     else
0134         reg |= VCO_POWERUP;
0135     writel_relaxed(reg, vco->base + VCO_CTRL0);
0136
0137     return 0;
0138 }
0139
0140 static void berlin2_avpll_vco_disable(struct clk_hw *hw)
0141 {
0142     struct berlin2_avpll_vco *vco = to_avpll_vco(hw);
0143     u32 reg;
0144
0145     reg = readl_relaxed(vco->base + VCO_CTRL0);
0146     if (vco->flags & BERLIN2_AVPLL_BIT_QUIRK)
0147         reg &= ~(VCO_POWERUP << 4);
0148     else
0149         reg &= ~VCO_POWERUP;
0150     writel_relaxed(reg, vco->base + VCO_CTRL0);
0151 }
0152
0153 static u8 vco_refdiv[] = { 1, 2, 4, 3 };
0154
0155 static unsigned long
0156 berlin2_avpll_vco_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
0157 {
0158     struct berlin2_avpll_vco *vco = to_avpll_vco(hw);
0159     u32 reg, refdiv, fbdiv;
0160     u64 freq = parent_rate;
0161
0162     /* AVPLL VCO frequency: Fvco = (Fref / refdiv) * fbdiv */
0163     reg = readl_relaxed(vco->base + VCO_CTRL1);
0164     refdiv = (reg & VCO_REFDIV_MASK) >> VCO_REFDIV_SHIFT;
0165     refdiv = vco_refdiv[refdiv];
0166     fbdiv = (reg & VCO_FBDIV_MASK) >> VCO_FBDIV_SHIFT;
0167     freq *= fbdiv;
0168     do_div(freq, refdiv);
0169
0170     return (unsigned long)freq;
0171 }
0172
0173 static const struct clk_ops berlin2_avpll_vco_ops = {
0174     .is_enabled = berlin2_avpll_vco_is_enabled,
0175     .enable     = berlin2_avpll_vco_enable,
0176     .disable    = berlin2_avpll_vco_disable,
0177     .recalc_rate    = berlin2_avpll_vco_recalc_rate,
0178 };
0179
0180 int __init berlin2_avpll_vco_register(void __iomem *base,
0181                    const char *name, const char *parent_name,
0182                    u8 vco_flags, unsigned long flags)
0183 {
0184     struct berlin2_avpll_vco *vco;
0185     struct clk_init_data init;
0186
0187     vco = kzalloc(sizeof(*vco), GFP_KERNEL);
0188     if (!vco)
0189         return -ENOMEM;
0190
0191     vco->base = base;
0192     vco->flags = vco_flags;
0193     vco->hw.init = &init;
0194     init.name = name;
0195     init.ops = &berlin2_avpll_vco_ops;
0196     init.parent_names = &parent_name;
0197     init.num_parents = 1;
0198     init.flags = flags;
0199
0200     return clk_hw_register(NULL, &vco->hw);
0201 }
0202
0203 struct berlin2_avpll_channel {
0204     struct clk_hw hw;
0205     void __iomem *base;
0206     u8 flags;
0207     u8 index;
0208 };
0209
0210 #define to_avpll_channel(hw) container_of(hw, struct berlin2_avpll_channel, hw)
0211
0212 static int berlin2_avpll_channel_is_enabled(struct clk_hw *hw)
0213 {
0214     struct berlin2_avpll_channel *ch = to_avpll_channel(hw);
0215     u32 reg;
0216
0217     if (ch->index == 7)
0218         return 1;
0219
0220     reg = readl_relaxed(ch->base + VCO_CTRL10);
0221     reg &= VCO_POWERUP_CH1 << ch->index;
0222
0223     return !!reg;
0224 }
0225
0226 static int berlin2_avpll_channel_enable(struct clk_hw *hw)
0227 {
0228     struct berlin2_avpll_channel *ch = to_avpll_channel(hw);
0229     u32 reg;
0230
0231     reg = readl_relaxed(ch->base + VCO_CTRL10);
0232     reg |= VCO_POWERUP_CH1 << ch->index;
0233     writel_relaxed(reg, ch->base + VCO_CTRL10);
0234
0235     return 0;
0236 }
0237
0238 static void berlin2_avpll_channel_disable(struct clk_hw *hw)
0239 {
0240     struct berlin2_avpll_channel *ch = to_avpll_channel(hw);
0241     u32 reg;
0242
0243     reg = readl_relaxed(ch->base + VCO_CTRL10);
0244     reg &= ~(VCO_POWERUP_CH1 << ch->index);
0245     writel_relaxed(reg, ch->base + VCO_CTRL10);
0246 }
0247
0248 static const u8 div_hdmi[] = { 1, 2, 4, 6 };
0249 static const u8 div_av1[] = { 1, 2, 5, 5 };
0250
0251 static unsigned long
0252 berlin2_avpll_channel_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
0253 {
0254     struct berlin2_avpll_channel *ch = to_avpll_channel(hw);
0255     u32 reg, div_av2, div_av3, divider = 1;
0256     u64 freq = parent_rate;
0257
0258     reg = readl_relaxed(ch->base + VCO_CTRL30);
0259     if ((reg & (VCO_DPLL_CH1_ENABLE << ch->index)) == 0)
0260         goto skip_div;
0261
0262     /*
0263      * Fch = (Fref * sync2) /
0264      *    (sync1 * div_hdmi * div_av1 * div_av2 * div_av3)
0265      */
0266
0267     reg = readl_relaxed(ch->base + VCO_SYNC1n(ch->index));
0268     /* BG2/BG2CDs SYNC1 reg on AVPLL_B channel 1 is shifted by 4 */
0269     if (ch->flags & BERLIN2_AVPLL_BIT_QUIRK && ch->index == 0)
0270         reg >>= 4;
0271     divider = reg & VCO_SYNC1_MASK;
0272
0273     reg = readl_relaxed(ch->base + VCO_SYNC2n(ch->index));
0274     freq *= reg & VCO_SYNC2_MASK;
0275
0276     /* Channel 8 has no dividers */
0277     if (ch->index == 7)
0278         goto skip_div;
0279
0280     /*
0281      * HDMI divider start at VCO_CTRL11, bit 7; MSB is enable, lower 2 bit
0282      * determine divider.
0283      */
0284     reg = readl_relaxed(ch->base + VCO_CTRL11) >> 7;
0285     reg = (reg >> (ch->index * 3));
0286     if (reg & BIT(2))
0287         divider *= div_hdmi[reg & 0x3];
0288
0289     /*
0290      * AV1 divider start at VCO_CTRL11, bit 28; MSB is enable, lower 2 bit
0291      * determine divider.
0292      */
0293     if (ch->index == 0) {
0294         reg = readl_relaxed(ch->base + VCO_CTRL11);
0295         reg >>= 28;
0296     } else {
0297         reg = readl_relaxed(ch->base + VCO_CTRL12);
0298         reg >>= (ch->index-1) * 3;
0299     }
0300     if (reg & BIT(2))
0301         divider *= div_av1[reg & 0x3];
0302
0303     /*
0304      * AV2 divider start at VCO_CTRL12, bit 18; each 7 bits wide,
0305      * zero is not a valid value.
0306      */
0307     if (ch->index < 2) {
0308         reg = readl_relaxed(ch->base + VCO_CTRL12);
0309         reg >>= 18 + (ch->index * 7);
0310     } else if (ch->index < 7) {
0311         reg = readl_relaxed(ch->base + VCO_CTRL13);
0312         reg >>= (ch->index - 2) * 7;
0313     } else {
0314         reg = readl_relaxed(ch->base + VCO_CTRL14);
0315     }
0316     div_av2 = reg & 0x7f;
0317     if (div_av2)
0318         divider *= div_av2;
0319
0320     /*
0321      * AV3 divider start at VCO_CTRL14, bit 7; each 4 bits wide.
0322      * AV2/AV3 form a fractional divider, where only specfic values for AV3
0323      * are allowed. AV3 != 0 divides by AV2/2, AV3=0 is bypass.
0324      */
0325     if (ch->index < 6) {
0326         reg = readl_relaxed(ch->base + VCO_CTRL14);
0327         reg >>= 7 + (ch->index * 4);
0328     } else {
0329         reg = readl_relaxed(ch->base + VCO_CTRL15);
0330     }
0331     div_av3 = reg & 0xf;
0332     if (div_av2 && div_av3)
0333         freq *= 2;
0334
0335 skip_div:
0336     do_div(freq, divider);
0337     return (unsigned long)freq;
0338 }
0339
0340 static const struct clk_ops berlin2_avpll_channel_ops = {
0341     .is_enabled = berlin2_avpll_channel_is_enabled,
0342     .enable     = berlin2_avpll_channel_enable,
0343     .disable    = berlin2_avpll_channel_disable,
0344     .recalc_rate    = berlin2_avpll_channel_recalc_rate,
0345 };
0346
0347 /*
0348  * Another nice quirk:
0349  * On some production SoCs, AVPLL channels are scrambled with respect
0350  * to the channel numbering in the registers but still referenced by
0351  * their original channel numbers. We deal with it by having a flag
0352  * and a translation table for the index.
0353  */
0354 static const u8 quirk_index[] __initconst = { 0, 6, 5, 4, 3, 2, 1, 7 };
0355
0356 int __init berlin2_avpll_channel_register(void __iomem *base,
0357                const char *name, u8 index, const char *parent_name,
0358                u8 ch_flags, unsigned long flags)
0359 {
0360     struct berlin2_avpll_channel *ch;
0361     struct clk_init_data init;
0362
0363     ch = kzalloc(sizeof(*ch), GFP_KERNEL);
0364     if (!ch)
0365         return -ENOMEM;
0366
0367     ch->base = base;
0368     if (ch_flags & BERLIN2_AVPLL_SCRAMBLE_QUIRK)
0369         ch->index = quirk_index[index];
0370     else
0371         ch->index = index;
0372
0373     ch->flags = ch_flags;
0374     ch->hw.init = &init;
0375     init.name = name;
0376     init.ops = &berlin2_avpll_channel_ops;
0377     init.parent_names = &parent_name;
0378     init.num_parents = 1;
0379     init.flags = flags;
0380
0381     return clk_hw_register(NULL, &ch->hw);
0382 }