clk/bcm/clk-ns2.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 // Copyright (C) 2015 Broadcom Corporation
0003
0004 #include <linux/kernel.h>
0005 #include <linux/err.h>
0006 #include <linux/clk-provider.h>
0007 #include <linux/io.h>
0008 #include <linux/of.h>
0009 #include <linux/of_address.h>
0010
0011 #include <dt-bindings/clock/bcm-ns2.h>
0012 #include "clk-iproc.h"
0013
0014 #define REG_VAL(o, s, w) { .offset = o, .shift = s, .width = w, }
0015
0016 #define AON_VAL(o, pw, ps, is) { .offset = o, .pwr_width = pw, \
0017     .pwr_shift = ps, .iso_shift = is }
0018
0019 #define RESET_VAL(o, rs, prs) { .offset = o, .reset_shift = rs, \
0020     .p_reset_shift = prs }
0021
0022 #define DF_VAL(o, kis, kiw, kps, kpw, kas, kaw) { .offset = o, .ki_shift = kis,\
0023     .ki_width = kiw, .kp_shift = kps, .kp_width = kpw, .ka_shift = kas,    \
0024     .ka_width = kaw }
0025
0026 #define VCO_CTRL_VAL(uo, lo) { .u_offset = uo, .l_offset = lo }
0027
0028 #define ENABLE_VAL(o, es, hs, bs) { .offset = o, .enable_shift = es, \
0029     .hold_shift = hs, .bypass_shift = bs }
0030
0031 static const struct iproc_pll_ctrl genpll_scr = {
0032     .flags = IPROC_CLK_AON | IPROC_CLK_PLL_SPLIT_STAT_CTRL,
0033     .aon = AON_VAL(0x0, 1, 15, 12),
0034     .reset = RESET_VAL(0x4, 2, 1),
0035     .dig_filter = DF_VAL(0x0, 9, 3, 5, 4, 2, 3),
0036     .ndiv_int = REG_VAL(0x8, 4, 10),
0037     .pdiv = REG_VAL(0x8, 0, 4),
0038     .vco_ctrl = VCO_CTRL_VAL(0x10, 0xc),
0039     .status = REG_VAL(0x0, 27, 1),
0040 };
0041
0042
0043 static const struct iproc_clk_ctrl genpll_scr_clk[] = {
0044     /* bypass_shift, the last value passed into ENABLE_VAL(), is not defined
0045      * in NS2.  However, it doesn't appear to be used anywhere, so setting
0046      * it to 0.
0047      */
0048     [BCM_NS2_GENPLL_SCR_SCR_CLK] = {
0049         .channel = BCM_NS2_GENPLL_SCR_SCR_CLK,
0050         .flags = IPROC_CLK_AON,
0051         .enable = ENABLE_VAL(0x0, 18, 12, 0),
0052         .mdiv = REG_VAL(0x18, 0, 8),
0053     },
0054     [BCM_NS2_GENPLL_SCR_FS_CLK] = {
0055         .channel = BCM_NS2_GENPLL_SCR_FS_CLK,
0056         .flags = IPROC_CLK_AON,
0057         .enable = ENABLE_VAL(0x0, 19, 13, 0),
0058         .mdiv = REG_VAL(0x18, 8, 8),
0059     },
0060     [BCM_NS2_GENPLL_SCR_AUDIO_CLK] = {
0061         .channel = BCM_NS2_GENPLL_SCR_AUDIO_CLK,
0062         .flags = IPROC_CLK_AON,
0063         .enable = ENABLE_VAL(0x0, 20, 14, 0),
0064         .mdiv = REG_VAL(0x14, 0, 8),
0065     },
0066     [BCM_NS2_GENPLL_SCR_CH3_UNUSED] = {
0067         .channel = BCM_NS2_GENPLL_SCR_CH3_UNUSED,
0068         .flags = IPROC_CLK_AON,
0069         .enable = ENABLE_VAL(0x0, 21, 15, 0),
0070         .mdiv = REG_VAL(0x14, 8, 8),
0071     },
0072     [BCM_NS2_GENPLL_SCR_CH4_UNUSED] = {
0073         .channel = BCM_NS2_GENPLL_SCR_CH4_UNUSED,
0074         .flags = IPROC_CLK_AON,
0075         .enable = ENABLE_VAL(0x0, 22, 16, 0),
0076         .mdiv = REG_VAL(0x14, 16, 8),
0077     },
0078     [BCM_NS2_GENPLL_SCR_CH5_UNUSED] = {
0079         .channel = BCM_NS2_GENPLL_SCR_CH5_UNUSED,
0080         .flags = IPROC_CLK_AON,
0081         .enable = ENABLE_VAL(0x0, 23, 17, 0),
0082         .mdiv = REG_VAL(0x14, 24, 8),
0083     },
0084 };
0085
0086 static void __init ns2_genpll_scr_clk_init(struct device_node *node)
0087 {
0088     iproc_pll_clk_setup(node, &genpll_scr, NULL, 0, genpll_scr_clk,
0089                 ARRAY_SIZE(genpll_scr_clk));
0090 }
0091 CLK_OF_DECLARE(ns2_genpll_src_clk, "brcm,ns2-genpll-scr",
0092            ns2_genpll_scr_clk_init);
0093
0094 static const struct iproc_pll_ctrl genpll_sw = {
0095     .flags = IPROC_CLK_AON | IPROC_CLK_PLL_SPLIT_STAT_CTRL,
0096     .aon = AON_VAL(0x0, 1, 11, 10),
0097     .reset = RESET_VAL(0x4, 2, 1),
0098     .dig_filter = DF_VAL(0x0, 9, 3, 5, 4, 2, 3),
0099     .ndiv_int = REG_VAL(0x8, 4, 10),
0100     .pdiv = REG_VAL(0x8, 0, 4),
0101     .vco_ctrl = VCO_CTRL_VAL(0x10, 0xc),
0102     .status = REG_VAL(0x0, 13, 1),
0103 };
0104
0105 static const struct iproc_clk_ctrl genpll_sw_clk[] = {
0106     /* bypass_shift, the last value passed into ENABLE_VAL(), is not defined
0107      * in NS2.  However, it doesn't appear to be used anywhere, so setting
0108      * it to 0.
0109      */
0110     [BCM_NS2_GENPLL_SW_RPE_CLK] = {
0111         .channel = BCM_NS2_GENPLL_SW_RPE_CLK,
0112         .flags = IPROC_CLK_AON,
0113         .enable = ENABLE_VAL(0x0, 18, 12, 0),
0114         .mdiv = REG_VAL(0x18, 0, 8),
0115     },
0116     [BCM_NS2_GENPLL_SW_250_CLK] = {
0117         .channel = BCM_NS2_GENPLL_SW_250_CLK,
0118         .flags = IPROC_CLK_AON,
0119         .enable = ENABLE_VAL(0x0, 19, 13, 0),
0120         .mdiv = REG_VAL(0x18, 8, 8),
0121     },
0122     [BCM_NS2_GENPLL_SW_NIC_CLK] = {
0123         .channel = BCM_NS2_GENPLL_SW_NIC_CLK,
0124         .flags = IPROC_CLK_AON,
0125         .enable = ENABLE_VAL(0x0, 20, 14, 0),
0126         .mdiv = REG_VAL(0x14, 0, 8),
0127     },
0128     [BCM_NS2_GENPLL_SW_CHIMP_CLK] = {
0129         .channel = BCM_NS2_GENPLL_SW_CHIMP_CLK,
0130         .flags = IPROC_CLK_AON,
0131         .enable = ENABLE_VAL(0x0, 21, 15, 0),
0132         .mdiv = REG_VAL(0x14, 8, 8),
0133     },
0134     [BCM_NS2_GENPLL_SW_PORT_CLK] = {
0135         .channel = BCM_NS2_GENPLL_SW_PORT_CLK,
0136         .flags = IPROC_CLK_AON,
0137         .enable = ENABLE_VAL(0x0, 22, 16, 0),
0138         .mdiv = REG_VAL(0x14, 16, 8),
0139     },
0140     [BCM_NS2_GENPLL_SW_SDIO_CLK] = {
0141         .channel = BCM_NS2_GENPLL_SW_SDIO_CLK,
0142         .flags = IPROC_CLK_AON,
0143         .enable = ENABLE_VAL(0x0, 23, 17, 0),
0144         .mdiv = REG_VAL(0x14, 24, 8),
0145     },
0146 };
0147
0148 static void __init ns2_genpll_sw_clk_init(struct device_node *node)
0149 {
0150     iproc_pll_clk_setup(node, &genpll_sw, NULL, 0, genpll_sw_clk,
0151                 ARRAY_SIZE(genpll_sw_clk));
0152 }
0153 CLK_OF_DECLARE(ns2_genpll_sw_clk, "brcm,ns2-genpll-sw",
0154            ns2_genpll_sw_clk_init);
0155
0156 static const struct iproc_pll_ctrl lcpll_ddr = {
0157     .flags = IPROC_CLK_AON | IPROC_CLK_PLL_SPLIT_STAT_CTRL,
0158     .aon = AON_VAL(0x0, 2, 1, 0),
0159     .reset = RESET_VAL(0x4, 2, 1),
0160     .dig_filter = DF_VAL(0x0, 9, 3, 5, 4, 1, 4),
0161     .ndiv_int = REG_VAL(0x8, 4, 10),
0162     .pdiv = REG_VAL(0x8, 0, 4),
0163     .vco_ctrl = VCO_CTRL_VAL(0x10, 0xc),
0164     .status = REG_VAL(0x0, 0, 1),
0165 };
0166
0167 static const struct iproc_clk_ctrl lcpll_ddr_clk[] = {
0168     /* bypass_shift, the last value passed into ENABLE_VAL(), is not defined
0169      * in NS2.  However, it doesn't appear to be used anywhere, so setting
0170      * it to 0.
0171      */
0172     [BCM_NS2_LCPLL_DDR_PCIE_SATA_USB_CLK] = {
0173         .channel = BCM_NS2_LCPLL_DDR_PCIE_SATA_USB_CLK,
0174         .flags = IPROC_CLK_AON,
0175         .enable = ENABLE_VAL(0x0, 18, 12, 0),
0176         .mdiv = REG_VAL(0x14, 0, 8),
0177     },
0178     [BCM_NS2_LCPLL_DDR_DDR_CLK] = {
0179         .channel = BCM_NS2_LCPLL_DDR_DDR_CLK,
0180         .flags = IPROC_CLK_AON,
0181         .enable = ENABLE_VAL(0x0, 19, 13, 0),
0182         .mdiv = REG_VAL(0x14, 8, 8),
0183     },
0184     [BCM_NS2_LCPLL_DDR_CH2_UNUSED] = {
0185         .channel = BCM_NS2_LCPLL_DDR_CH2_UNUSED,
0186         .flags = IPROC_CLK_AON,
0187         .enable = ENABLE_VAL(0x0, 20, 14, 0),
0188         .mdiv = REG_VAL(0x10, 0, 8),
0189     },
0190     [BCM_NS2_LCPLL_DDR_CH3_UNUSED] = {
0191         .channel = BCM_NS2_LCPLL_DDR_CH3_UNUSED,
0192         .flags = IPROC_CLK_AON,
0193         .enable = ENABLE_VAL(0x0, 21, 15, 0),
0194         .mdiv = REG_VAL(0x10, 8, 8),
0195     },
0196     [BCM_NS2_LCPLL_DDR_CH4_UNUSED] = {
0197         .channel = BCM_NS2_LCPLL_DDR_CH4_UNUSED,
0198         .flags = IPROC_CLK_AON,
0199         .enable = ENABLE_VAL(0x0, 22, 16, 0),
0200         .mdiv = REG_VAL(0x10, 16, 8),
0201     },
0202     [BCM_NS2_LCPLL_DDR_CH5_UNUSED] = {
0203         .channel = BCM_NS2_LCPLL_DDR_CH5_UNUSED,
0204         .flags = IPROC_CLK_AON,
0205         .enable = ENABLE_VAL(0x0, 23, 17, 0),
0206         .mdiv = REG_VAL(0x10, 24, 8),
0207     },
0208 };
0209
0210 static void __init ns2_lcpll_ddr_clk_init(struct device_node *node)
0211 {
0212     iproc_pll_clk_setup(node, &lcpll_ddr, NULL, 0, lcpll_ddr_clk,
0213                 ARRAY_SIZE(lcpll_ddr_clk));
0214 }
0215 CLK_OF_DECLARE(ns2_lcpll_ddr_clk, "brcm,ns2-lcpll-ddr",
0216            ns2_lcpll_ddr_clk_init);
0217
0218 static const struct iproc_pll_ctrl lcpll_ports = {
0219     .flags = IPROC_CLK_AON | IPROC_CLK_PLL_SPLIT_STAT_CTRL,
0220     .aon = AON_VAL(0x0, 2, 5, 4),
0221     .reset = RESET_VAL(0x4, 2, 1),
0222     .dig_filter = DF_VAL(0x0, 9, 3, 5, 4, 1, 4),
0223     .ndiv_int = REG_VAL(0x8, 4, 10),
0224     .pdiv = REG_VAL(0x8, 0, 4),
0225     .vco_ctrl = VCO_CTRL_VAL(0x10, 0xc),
0226     .status = REG_VAL(0x0, 0, 1),
0227 };
0228
0229 static const struct iproc_clk_ctrl lcpll_ports_clk[] = {
0230     /* bypass_shift, the last value passed into ENABLE_VAL(), is not defined
0231      * in NS2.  However, it doesn't appear to be used anywhere, so setting
0232      * it to 0.
0233      */
0234     [BCM_NS2_LCPLL_PORTS_WAN_CLK] = {
0235         .channel = BCM_NS2_LCPLL_PORTS_WAN_CLK,
0236         .flags = IPROC_CLK_AON,
0237         .enable = ENABLE_VAL(0x0, 18, 12, 0),
0238         .mdiv = REG_VAL(0x14, 0, 8),
0239     },
0240     [BCM_NS2_LCPLL_PORTS_RGMII_CLK] = {
0241         .channel = BCM_NS2_LCPLL_PORTS_RGMII_CLK,
0242         .flags = IPROC_CLK_AON,
0243         .enable = ENABLE_VAL(0x0, 19, 13, 0),
0244         .mdiv = REG_VAL(0x14, 8, 8),
0245     },
0246     [BCM_NS2_LCPLL_PORTS_CH2_UNUSED] = {
0247         .channel = BCM_NS2_LCPLL_PORTS_CH2_UNUSED,
0248         .flags = IPROC_CLK_AON,
0249         .enable = ENABLE_VAL(0x0, 20, 14, 0),
0250         .mdiv = REG_VAL(0x10, 0, 8),
0251     },
0252     [BCM_NS2_LCPLL_PORTS_CH3_UNUSED] = {
0253         .channel = BCM_NS2_LCPLL_PORTS_CH3_UNUSED,
0254         .flags = IPROC_CLK_AON,
0255         .enable = ENABLE_VAL(0x0, 21, 15, 0),
0256         .mdiv = REG_VAL(0x10, 8, 8),
0257     },
0258     [BCM_NS2_LCPLL_PORTS_CH4_UNUSED] = {
0259         .channel = BCM_NS2_LCPLL_PORTS_CH4_UNUSED,
0260         .flags = IPROC_CLK_AON,
0261         .enable = ENABLE_VAL(0x0, 22, 16, 0),
0262         .mdiv = REG_VAL(0x10, 16, 8),
0263     },
0264     [BCM_NS2_LCPLL_PORTS_CH5_UNUSED] = {
0265         .channel = BCM_NS2_LCPLL_PORTS_CH5_UNUSED,
0266         .flags = IPROC_CLK_AON,
0267         .enable = ENABLE_VAL(0x0, 23, 17, 0),
0268         .mdiv = REG_VAL(0x10, 24, 8),
0269     },
0270 };
0271
0272 static void __init ns2_lcpll_ports_clk_init(struct device_node *node)
0273 {
0274     iproc_pll_clk_setup(node, &lcpll_ports, NULL, 0, lcpll_ports_clk,
0275                 ARRAY_SIZE(lcpll_ports_clk));
0276 }
0277 CLK_OF_DECLARE(ns2_lcpll_ports_clk, "brcm,ns2-lcpll-ports",
0278            ns2_lcpll_ports_clk_init);