clk/bcm/clk-kona.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (C) 2013 Broadcom Corporation
0004  * Copyright 2013 Linaro Limited
0005  */
0006
0007 #include "clk-kona.h"
0008
0009 #include <linux/delay.h>
0010 #include <linux/io.h>
0011 #include <linux/kernel.h>
0012 #include <linux/clk-provider.h>
0013
0014 /*
0015  * "Policies" affect the frequencies of bus clocks provided by a
0016  * CCU.  (I believe these polices are named "Deep Sleep", "Economy",
0017  * "Normal", and "Turbo".)  A lower policy number has lower power
0018  * consumption, and policy 2 is the default.
0019  */
0020 #define CCU_POLICY_COUNT    4
0021
0022 #define CCU_ACCESS_PASSWORD      0xA5A500
0023 #define CLK_GATE_DELAY_LOOP      2000
0024
0025 /* Bitfield operations */
0026
0027 /* Produces a mask of set bits covering a range of a 32-bit value */
0028 static inline u32 bitfield_mask(u32 shift, u32 width)
0029 {
0030     return ((1 << width) - 1) << shift;
0031 }
0032
0033 /* Extract the value of a bitfield found within a given register value */
0034 static inline u32 bitfield_extract(u32 reg_val, u32 shift, u32 width)
0035 {
0036     return (reg_val & bitfield_mask(shift, width)) >> shift;
0037 }
0038
0039 /* Replace the value of a bitfield found within a given register value */
0040 static inline u32 bitfield_replace(u32 reg_val, u32 shift, u32 width, u32 val)
0041 {
0042     u32 mask = bitfield_mask(shift, width);
0043
0044     return (reg_val & ~mask) | (val << shift);
0045 }
0046
0047 /* Divider and scaling helpers */
0048
0049 /* Convert a divider into the scaled divisor value it represents. */
0050 static inline u64 scaled_div_value(struct bcm_clk_div *div, u32 reg_div)
0051 {
0052     return (u64)reg_div + ((u64)1 << div->u.s.frac_width);
0053 }
0054
0055 /*
0056  * Build a scaled divider value as close as possible to the
0057  * given whole part (div_value) and fractional part (expressed
0058  * in billionths).
0059  */
0060 u64 scaled_div_build(struct bcm_clk_div *div, u32 div_value, u32 billionths)
0061 {
0062     u64 combined;
0063
0064     BUG_ON(!div_value);
0065     BUG_ON(billionths >= BILLION);
0066
0067     combined = (u64)div_value * BILLION + billionths;
0068     combined <<= div->u.s.frac_width;
0069
0070     return DIV_ROUND_CLOSEST_ULL(combined, BILLION);
0071 }
0072
0073 /* The scaled minimum divisor representable by a divider */
0074 static inline u64
0075 scaled_div_min(struct bcm_clk_div *div)
0076 {
0077     if (divider_is_fixed(div))
0078         return (u64)div->u.fixed;
0079
0080     return scaled_div_value(div, 0);
0081 }
0082
0083 /* The scaled maximum divisor representable by a divider */
0084 u64 scaled_div_max(struct bcm_clk_div *div)
0085 {
0086     u32 reg_div;
0087
0088     if (divider_is_fixed(div))
0089         return (u64)div->u.fixed;
0090
0091     reg_div = ((u32)1 << div->u.s.width) - 1;
0092
0093     return scaled_div_value(div, reg_div);
0094 }
0095
0096 /*
0097  * Convert a scaled divisor into its divider representation as
0098  * stored in a divider register field.
0099  */
0100 static inline u32
0101 divider(struct bcm_clk_div *div, u64 scaled_div)
0102 {
0103     BUG_ON(scaled_div < scaled_div_min(div));
0104     BUG_ON(scaled_div > scaled_div_max(div));
0105
0106     return (u32)(scaled_div - ((u64)1 << div->u.s.frac_width));
0107 }
0108
0109 /* Return a rate scaled for use when dividing by a scaled divisor. */
0110 static inline u64
0111 scale_rate(struct bcm_clk_div *div, u32 rate)
0112 {
0113     if (divider_is_fixed(div))
0114         return (u64)rate;
0115
0116     return (u64)rate << div->u.s.frac_width;
0117 }
0118
0119 /* CCU access */
0120
0121 /* Read a 32-bit register value from a CCU's address space. */
0122 static inline u32 __ccu_read(struct ccu_data *ccu, u32 reg_offset)
0123 {
0124     return readl(ccu->base + reg_offset);
0125 }
0126
0127 /* Write a 32-bit register value into a CCU's address space. */
0128 static inline void
0129 __ccu_write(struct ccu_data *ccu, u32 reg_offset, u32 reg_val)
0130 {
0131     writel(reg_val, ccu->base + reg_offset);
0132 }
0133
0134 static inline unsigned long ccu_lock(struct ccu_data *ccu)
0135 {
0136     unsigned long flags;
0137
0138     spin_lock_irqsave(&ccu->lock, flags);
0139
0140     return flags;
0141 }
0142 static inline void ccu_unlock(struct ccu_data *ccu, unsigned long flags)
0143 {
0144     spin_unlock_irqrestore(&ccu->lock, flags);
0145 }
0146
0147 /*
0148  * Enable/disable write access to CCU protected registers.  The
0149  * WR_ACCESS register for all CCUs is at offset 0.
0150  */
0151 static inline void __ccu_write_enable(struct ccu_data *ccu)
0152 {
0153     if (ccu->write_enabled) {
0154         pr_err("%s: access already enabled for %s\n", __func__,
0155             ccu->name);
0156         return;
0157     }
0158     ccu->write_enabled = true;
0159     __ccu_write(ccu, 0, CCU_ACCESS_PASSWORD | 1);
0160 }
0161
0162 static inline void __ccu_write_disable(struct ccu_data *ccu)
0163 {
0164     if (!ccu->write_enabled) {
0165         pr_err("%s: access wasn't enabled for %s\n", __func__,
0166             ccu->name);
0167         return;
0168     }
0169
0170     __ccu_write(ccu, 0, CCU_ACCESS_PASSWORD);
0171     ccu->write_enabled = false;
0172 }
0173
0174 /*
0175  * Poll a register in a CCU's address space, returning when the
0176  * specified bit in that register's value is set (or clear).  Delay
0177  * a microsecond after each read of the register.  Returns true if
0178  * successful, or false if we gave up trying.
0179  *
0180  * Caller must ensure the CCU lock is held.
0181  */
0182 static inline bool
0183 __ccu_wait_bit(struct ccu_data *ccu, u32 reg_offset, u32 bit, bool want)
0184 {
0185     unsigned int tries;
0186     u32 bit_mask = 1 << bit;
0187
0188     for (tries = 0; tries < CLK_GATE_DELAY_LOOP; tries++) {
0189         u32 val;
0190         bool bit_val;
0191
0192         val = __ccu_read(ccu, reg_offset);
0193         bit_val = (val & bit_mask) != 0;
0194         if (bit_val == want)
0195             return true;
0196         udelay(1);
0197     }
0198     pr_warn("%s: %s/0x%04x bit %u was never %s\n", __func__,
0199         ccu->name, reg_offset, bit, want ? "set" : "clear");
0200
0201     return false;
0202 }
0203
0204 /* Policy operations */
0205
0206 static bool __ccu_policy_engine_start(struct ccu_data *ccu, bool sync)
0207 {
0208     struct bcm_policy_ctl *control = &ccu->policy.control;
0209     u32 offset;
0210     u32 go_bit;
0211     u32 mask;
0212     bool ret;
0213
0214     /* If we don't need to control policy for this CCU, we're done. */
0215     if (!policy_ctl_exists(control))
0216         return true;
0217
0218     offset = control->offset;
0219     go_bit = control->go_bit;
0220
0221     /* Ensure we're not busy before we start */
0222     ret = __ccu_wait_bit(ccu, offset, go_bit, false);
0223     if (!ret) {
0224         pr_err("%s: ccu %s policy engine wouldn't go idle\n",
0225             __func__, ccu->name);
0226         return false;
0227     }
0228
0229     /*
0230      * If it's a synchronous request, we'll wait for the voltage
0231      * and frequency of the active load to stabilize before
0232      * returning.  To do this we select the active load by
0233      * setting the ATL bit.
0234      *
0235      * An asynchronous request instead ramps the voltage in the
0236      * background, and when that process stabilizes, the target
0237      * load is copied to the active load and the CCU frequency
0238      * is switched.  We do this by selecting the target load
0239      * (ATL bit clear) and setting the request auto-copy (AC bit
0240      * set).
0241      *
0242      * Note, we do NOT read-modify-write this register.
0243      */
0244     mask = (u32)1 << go_bit;
0245     if (sync)
0246         mask |= 1 << control->atl_bit;
0247     else
0248         mask |= 1 << control->ac_bit;
0249     __ccu_write(ccu, offset, mask);
0250
0251     /* Wait for indication that operation is complete. */
0252     ret = __ccu_wait_bit(ccu, offset, go_bit, false);
0253     if (!ret)
0254         pr_err("%s: ccu %s policy engine never started\n",
0255             __func__, ccu->name);
0256
0257     return ret;
0258 }
0259
0260 static bool __ccu_policy_engine_stop(struct ccu_data *ccu)
0261 {
0262     struct bcm_lvm_en *enable = &ccu->policy.enable;
0263     u32 offset;
0264     u32 enable_bit;
0265     bool ret;
0266
0267     /* If we don't need to control policy for this CCU, we're done. */
0268     if (!policy_lvm_en_exists(enable))
0269         return true;
0270
0271     /* Ensure we're not busy before we start */
0272     offset = enable->offset;
0273     enable_bit = enable->bit;
0274     ret = __ccu_wait_bit(ccu, offset, enable_bit, false);
0275     if (!ret) {
0276         pr_err("%s: ccu %s policy engine already stopped\n",
0277             __func__, ccu->name);
0278         return false;
0279     }
0280
0281     /* Now set the bit to stop the engine (NO read-modify-write) */
0282     __ccu_write(ccu, offset, (u32)1 << enable_bit);
0283
0284     /* Wait for indication that it has stopped. */
0285     ret = __ccu_wait_bit(ccu, offset, enable_bit, false);
0286     if (!ret)
0287         pr_err("%s: ccu %s policy engine never stopped\n",
0288             __func__, ccu->name);
0289
0290     return ret;
0291 }
0292
0293 /*
0294  * A CCU has four operating conditions ("policies"), and some clocks
0295  * can be disabled or enabled based on which policy is currently in
0296  * effect.  Such clocks have a bit in a "policy mask" register for
0297  * each policy indicating whether the clock is enabled for that
0298  * policy or not.  The bit position for a clock is the same for all
0299  * four registers, and the 32-bit registers are at consecutive
0300  * addresses.
0301  */
0302 static bool policy_init(struct ccu_data *ccu, struct bcm_clk_policy *policy)
0303 {
0304     u32 offset;
0305     u32 mask;
0306     int i;
0307     bool ret;
0308
0309     if (!policy_exists(policy))
0310         return true;
0311
0312     /*
0313      * We need to stop the CCU policy engine to allow update
0314      * of our policy bits.
0315      */
0316     if (!__ccu_policy_engine_stop(ccu)) {
0317         pr_err("%s: unable to stop CCU %s policy engine\n",
0318             __func__, ccu->name);
0319         return false;
0320     }
0321
0322     /*
0323      * For now, if a clock defines its policy bit we just mark
0324      * it "enabled" for all four policies.
0325      */
0326     offset = policy->offset;
0327     mask = (u32)1 << policy->bit;
0328     for (i = 0; i < CCU_POLICY_COUNT; i++) {
0329         u32 reg_val;
0330
0331         reg_val = __ccu_read(ccu, offset);
0332         reg_val |= mask;
0333         __ccu_write(ccu, offset, reg_val);
0334         offset += sizeof(u32);
0335     }
0336
0337     /* We're done updating; fire up the policy engine again. */
0338     ret = __ccu_policy_engine_start(ccu, true);
0339     if (!ret)
0340         pr_err("%s: unable to restart CCU %s policy engine\n",
0341             __func__, ccu->name);
0342
0343     return ret;
0344 }
0345
0346 /* Gate operations */
0347
0348 /* Determine whether a clock is gated.  CCU lock must be held.  */
0349 static bool
0350 __is_clk_gate_enabled(struct ccu_data *ccu, struct bcm_clk_gate *gate)
0351 {
0352     u32 bit_mask;
0353     u32 reg_val;
0354
0355     /* If there is no gate we can assume it's enabled. */
0356     if (!gate_exists(gate))
0357         return true;
0358
0359     bit_mask = 1 << gate->status_bit;
0360     reg_val = __ccu_read(ccu, gate->offset);
0361
0362     return (reg_val & bit_mask) != 0;
0363 }
0364
0365 /* Determine whether a clock is gated. */
0366 static bool
0367 is_clk_gate_enabled(struct ccu_data *ccu, struct bcm_clk_gate *gate)
0368 {
0369     long flags;
0370     bool ret;
0371
0372     /* Avoid taking the lock if we can */
0373     if (!gate_exists(gate))
0374         return true;
0375
0376     flags = ccu_lock(ccu);
0377     ret = __is_clk_gate_enabled(ccu, gate);
0378     ccu_unlock(ccu, flags);
0379
0380     return ret;
0381 }
0382
0383 /*
0384  * Commit our desired gate state to the hardware.
0385  * Returns true if successful, false otherwise.
0386  */
0387 static bool
0388 __gate_commit(struct ccu_data *ccu, struct bcm_clk_gate *gate)
0389 {
0390     u32 reg_val;
0391     u32 mask;
0392     bool enabled = false;
0393
0394     BUG_ON(!gate_exists(gate));
0395     if (!gate_is_sw_controllable(gate))
0396         return true;        /* Nothing we can change */
0397
0398     reg_val = __ccu_read(ccu, gate->offset);
0399
0400     /* For a hardware/software gate, set which is in control */
0401     if (gate_is_hw_controllable(gate)) {
0402         mask = (u32)1 << gate->hw_sw_sel_bit;
0403         if (gate_is_sw_managed(gate))
0404             reg_val |= mask;
0405         else
0406             reg_val &= ~mask;
0407     }
0408
0409     /*
0410      * If software is in control, enable or disable the gate.
0411      * If hardware is, clear the enabled bit for good measure.
0412      * If a software controlled gate can't be disabled, we're
0413      * required to write a 0 into the enable bit (but the gate
0414      * will be enabled).
0415      */
0416     mask = (u32)1 << gate->en_bit;
0417     if (gate_is_sw_managed(gate) && (enabled = gate_is_enabled(gate)) &&
0418             !gate_is_no_disable(gate))
0419         reg_val |= mask;
0420     else
0421         reg_val &= ~mask;
0422
0423     __ccu_write(ccu, gate->offset, reg_val);
0424
0425     /* For a hardware controlled gate, we're done */
0426     if (!gate_is_sw_managed(gate))
0427         return true;
0428
0429     /* Otherwise wait for the gate to be in desired state */
0430     return __ccu_wait_bit(ccu, gate->offset, gate->status_bit, enabled);
0431 }
0432
0433 /*
0434  * Initialize a gate.  Our desired state (hardware/software select,
0435  * and if software, its enable state) is committed to hardware
0436  * without the usual checks to see if it's already set up that way.
0437  * Returns true if successful, false otherwise.
0438  */
0439 static bool gate_init(struct ccu_data *ccu, struct bcm_clk_gate *gate)
0440 {
0441     if (!gate_exists(gate))
0442         return true;
0443     return __gate_commit(ccu, gate);
0444 }
0445
0446 /*
0447  * Set a gate to enabled or disabled state.  Does nothing if the
0448  * gate is not currently under software control, or if it is already
0449  * in the requested state.  Returns true if successful, false
0450  * otherwise.  CCU lock must be held.
0451  */
0452 static bool
0453 __clk_gate(struct ccu_data *ccu, struct bcm_clk_gate *gate, bool enable)
0454 {
0455     bool ret;
0456
0457     if (!gate_exists(gate) || !gate_is_sw_managed(gate))
0458         return true;    /* Nothing to do */
0459
0460     if (!enable && gate_is_no_disable(gate)) {
0461         pr_warn("%s: invalid gate disable request (ignoring)\n",
0462             __func__);
0463         return true;
0464     }
0465
0466     if (enable == gate_is_enabled(gate))
0467         return true;    /* No change */
0468
0469     gate_flip_enabled(gate);
0470     ret = __gate_commit(ccu, gate);
0471     if (!ret)
0472         gate_flip_enabled(gate);    /* Revert the change */
0473
0474     return ret;
0475 }
0476
0477 /* Enable or disable a gate.  Returns 0 if successful, -EIO otherwise */
0478 static int clk_gate(struct ccu_data *ccu, const char *name,
0479             struct bcm_clk_gate *gate, bool enable)
0480 {
0481     unsigned long flags;
0482     bool success;
0483
0484     /*
0485      * Avoid taking the lock if we can.  We quietly ignore
0486      * requests to change state that don't make sense.
0487      */
0488     if (!gate_exists(gate) || !gate_is_sw_managed(gate))
0489         return 0;
0490     if (!enable && gate_is_no_disable(gate))
0491         return 0;
0492
0493     flags = ccu_lock(ccu);
0494     __ccu_write_enable(ccu);
0495
0496     success = __clk_gate(ccu, gate, enable);
0497
0498     __ccu_write_disable(ccu);
0499     ccu_unlock(ccu, flags);
0500
0501     if (success)
0502         return 0;
0503
0504     pr_err("%s: failed to %s gate for %s\n", __func__,
0505         enable ? "enable" : "disable", name);
0506
0507     return -EIO;
0508 }
0509
0510 /* Hysteresis operations */
0511
0512 /*
0513  * If a clock gate requires a turn-off delay it will have
0514  * "hysteresis" register bits defined.  The first, if set, enables
0515  * the delay; and if enabled, the second bit determines whether the
0516  * delay is "low" or "high" (1 means high).  For now, if it's
0517  * defined for a clock, we set it.
0518  */
0519 static bool hyst_init(struct ccu_data *ccu, struct bcm_clk_hyst *hyst)
0520 {
0521     u32 offset;
0522     u32 reg_val;
0523     u32 mask;
0524
0525     if (!hyst_exists(hyst))
0526         return true;
0527
0528     offset = hyst->offset;
0529     mask = (u32)1 << hyst->en_bit;
0530     mask |= (u32)1 << hyst->val_bit;
0531
0532     reg_val = __ccu_read(ccu, offset);
0533     reg_val |= mask;
0534     __ccu_write(ccu, offset, reg_val);
0535
0536     return true;
0537 }
0538
0539 /* Trigger operations */
0540
0541 /*
0542  * Caller must ensure CCU lock is held and access is enabled.
0543  * Returns true if successful, false otherwise.
0544  */
0545 static bool __clk_trigger(struct ccu_data *ccu, struct bcm_clk_trig *trig)
0546 {
0547     /* Trigger the clock and wait for it to finish */
0548     __ccu_write(ccu, trig->offset, 1 << trig->bit);
0549
0550     return __ccu_wait_bit(ccu, trig->offset, trig->bit, false);
0551 }
0552
0553 /* Divider operations */
0554
0555 /* Read a divider value and return the scaled divisor it represents. */
0556 static u64 divider_read_scaled(struct ccu_data *ccu, struct bcm_clk_div *div)
0557 {
0558     unsigned long flags;
0559     u32 reg_val;
0560     u32 reg_div;
0561
0562     if (divider_is_fixed(div))
0563         return (u64)div->u.fixed;
0564
0565     flags = ccu_lock(ccu);
0566     reg_val = __ccu_read(ccu, div->u.s.offset);
0567     ccu_unlock(ccu, flags);
0568
0569     /* Extract the full divider field from the register value */
0570     reg_div = bitfield_extract(reg_val, div->u.s.shift, div->u.s.width);
0571
0572     /* Return the scaled divisor value it represents */
0573     return scaled_div_value(div, reg_div);
0574 }
0575
0576 /*
0577  * Convert a divider's scaled divisor value into its recorded form
0578  * and commit it into the hardware divider register.
0579  *
0580  * Returns 0 on success.  Returns -EINVAL for invalid arguments.
0581  * Returns -ENXIO if gating failed, and -EIO if a trigger failed.
0582  */
0583 static int __div_commit(struct ccu_data *ccu, struct bcm_clk_gate *gate,
0584             struct bcm_clk_div *div, struct bcm_clk_trig *trig)
0585 {
0586     bool enabled;
0587     u32 reg_div;
0588     u32 reg_val;
0589     int ret = 0;
0590
0591     BUG_ON(divider_is_fixed(div));
0592
0593     /*
0594      * If we're just initializing the divider, and no initial
0595      * state was defined in the device tree, we just find out
0596      * what its current value is rather than updating it.
0597      */
0598     if (div->u.s.scaled_div == BAD_SCALED_DIV_VALUE) {
0599         reg_val = __ccu_read(ccu, div->u.s.offset);
0600         reg_div = bitfield_extract(reg_val, div->u.s.shift,
0601                         div->u.s.width);
0602         div->u.s.scaled_div = scaled_div_value(div, reg_div);
0603
0604         return 0;
0605     }
0606
0607     /* Convert the scaled divisor to the value we need to record */
0608     reg_div = divider(div, div->u.s.scaled_div);
0609
0610     /* Clock needs to be enabled before changing the rate */
0611     enabled = __is_clk_gate_enabled(ccu, gate);
0612     if (!enabled && !__clk_gate(ccu, gate, true)) {
0613         ret = -ENXIO;
0614         goto out;
0615     }
0616
0617     /* Replace the divider value and record the result */
0618     reg_val = __ccu_read(ccu, div->u.s.offset);
0619     reg_val = bitfield_replace(reg_val, div->u.s.shift, div->u.s.width,
0620                     reg_div);
0621     __ccu_write(ccu, div->u.s.offset, reg_val);
0622
0623     /* If the trigger fails we still want to disable the gate */
0624     if (!__clk_trigger(ccu, trig))
0625         ret = -EIO;
0626
0627     /* Disable the clock again if it was disabled to begin with */
0628     if (!enabled && !__clk_gate(ccu, gate, false))
0629         ret = ret ? ret : -ENXIO;   /* return first error */
0630 out:
0631     return ret;
0632 }
0633
0634 /*
0635  * Initialize a divider by committing our desired state to hardware
0636  * without the usual checks to see if it's already set up that way.
0637  * Returns true if successful, false otherwise.
0638  */
0639 static bool div_init(struct ccu_data *ccu, struct bcm_clk_gate *gate,
0640             struct bcm_clk_div *div, struct bcm_clk_trig *trig)
0641 {
0642     if (!divider_exists(div) || divider_is_fixed(div))
0643         return true;
0644     return !__div_commit(ccu, gate, div, trig);
0645 }
0646
0647 static int divider_write(struct ccu_data *ccu, struct bcm_clk_gate *gate,
0648             struct bcm_clk_div *div, struct bcm_clk_trig *trig,
0649             u64 scaled_div)
0650 {
0651     unsigned long flags;
0652     u64 previous;
0653     int ret;
0654
0655     BUG_ON(divider_is_fixed(div));
0656
0657     previous = div->u.s.scaled_div;
0658     if (previous == scaled_div)
0659         return 0;   /* No change */
0660
0661     div->u.s.scaled_div = scaled_div;
0662
0663     flags = ccu_lock(ccu);
0664     __ccu_write_enable(ccu);
0665
0666     ret = __div_commit(ccu, gate, div, trig);
0667
0668     __ccu_write_disable(ccu);
0669     ccu_unlock(ccu, flags);
0670
0671     if (ret)
0672         div->u.s.scaled_div = previous;     /* Revert the change */
0673
0674     return ret;
0675
0676 }
0677
0678 /* Common clock rate helpers */
0679
0680 /*
0681  * Implement the common clock framework recalc_rate method, taking
0682  * into account a divider and an optional pre-divider.  The
0683  * pre-divider register pointer may be NULL.
0684  */
0685 static unsigned long clk_recalc_rate(struct ccu_data *ccu,
0686             struct bcm_clk_div *div, struct bcm_clk_div *pre_div,
0687             unsigned long parent_rate)
0688 {
0689     u64 scaled_parent_rate;
0690     u64 scaled_div;
0691     u64 result;
0692
0693     if (!divider_exists(div))
0694         return parent_rate;
0695
0696     if (parent_rate > (unsigned long)LONG_MAX)
0697         return 0;   /* actually this would be a caller bug */
0698
0699     /*
0700      * If there is a pre-divider, divide the scaled parent rate
0701      * by the pre-divider value first.  In this case--to improve
0702      * accuracy--scale the parent rate by *both* the pre-divider
0703      * value and the divider before actually computing the
0704      * result of the pre-divider.
0705      *
0706      * If there's only one divider, just scale the parent rate.
0707      */
0708     if (pre_div && divider_exists(pre_div)) {
0709         u64 scaled_rate;
0710
0711         scaled_rate = scale_rate(pre_div, parent_rate);
0712         scaled_rate = scale_rate(div, scaled_rate);
0713         scaled_div = divider_read_scaled(ccu, pre_div);
0714         scaled_parent_rate = DIV_ROUND_CLOSEST_ULL(scaled_rate,
0715                             scaled_div);
0716     } else  {
0717         scaled_parent_rate = scale_rate(div, parent_rate);
0718     }
0719
0720     /*
0721      * Get the scaled divisor value, and divide the scaled
0722      * parent rate by that to determine this clock's resulting
0723      * rate.
0724      */
0725     scaled_div = divider_read_scaled(ccu, div);
0726     result = DIV_ROUND_CLOSEST_ULL(scaled_parent_rate, scaled_div);
0727
0728     return (unsigned long)result;
0729 }
0730
0731 /*
0732  * Compute the output rate produced when a given parent rate is fed
0733  * into two dividers.  The pre-divider can be NULL, and even if it's
0734  * non-null it may be nonexistent.  It's also OK for the divider to
0735  * be nonexistent, and in that case the pre-divider is also ignored.
0736  *
0737  * If scaled_div is non-null, it is used to return the scaled divisor
0738  * value used by the (downstream) divider to produce that rate.
0739  */
0740 static long round_rate(struct ccu_data *ccu, struct bcm_clk_div *div,
0741                 struct bcm_clk_div *pre_div,
0742                 unsigned long rate, unsigned long parent_rate,
0743                 u64 *scaled_div)
0744 {
0745     u64 scaled_parent_rate;
0746     u64 min_scaled_div;
0747     u64 max_scaled_div;
0748     u64 best_scaled_div;
0749     u64 result;
0750
0751     BUG_ON(!divider_exists(div));
0752     BUG_ON(!rate);
0753     BUG_ON(parent_rate > (u64)LONG_MAX);
0754
0755     /*
0756      * If there is a pre-divider, divide the scaled parent rate
0757      * by the pre-divider value first.  In this case--to improve
0758      * accuracy--scale the parent rate by *both* the pre-divider
0759      * value and the divider before actually computing the
0760      * result of the pre-divider.
0761      *
0762      * If there's only one divider, just scale the parent rate.
0763      *
0764      * For simplicity we treat the pre-divider as fixed (for now).
0765      */
0766     if (divider_exists(pre_div)) {
0767         u64 scaled_rate;
0768         u64 scaled_pre_div;
0769
0770         scaled_rate = scale_rate(pre_div, parent_rate);
0771         scaled_rate = scale_rate(div, scaled_rate);
0772         scaled_pre_div = divider_read_scaled(ccu, pre_div);
0773         scaled_parent_rate = DIV_ROUND_CLOSEST_ULL(scaled_rate,
0774                             scaled_pre_div);
0775     } else {
0776         scaled_parent_rate = scale_rate(div, parent_rate);
0777     }
0778
0779     /*
0780      * Compute the best possible divider and ensure it is in
0781      * range.  A fixed divider can't be changed, so just report
0782      * the best we can do.
0783      */
0784     if (!divider_is_fixed(div)) {
0785         best_scaled_div = DIV_ROUND_CLOSEST_ULL(scaled_parent_rate,
0786                             rate);
0787         min_scaled_div = scaled_div_min(div);
0788         max_scaled_div = scaled_div_max(div);
0789         if (best_scaled_div > max_scaled_div)
0790             best_scaled_div = max_scaled_div;
0791         else if (best_scaled_div < min_scaled_div)
0792             best_scaled_div = min_scaled_div;
0793     } else {
0794         best_scaled_div = divider_read_scaled(ccu, div);
0795     }
0796
0797     /* OK, figure out the resulting rate */
0798     result = DIV_ROUND_CLOSEST_ULL(scaled_parent_rate, best_scaled_div);
0799
0800     if (scaled_div)
0801         *scaled_div = best_scaled_div;
0802
0803     return (long)result;
0804 }
0805
0806 /* Common clock parent helpers */
0807
0808 /*
0809  * For a given parent selector (register field) value, find the
0810  * index into a selector's parent_sel array that contains it.
0811  * Returns the index, or BAD_CLK_INDEX if it's not found.
0812  */
0813 static u8 parent_index(struct bcm_clk_sel *sel, u8 parent_sel)
0814 {
0815     u8 i;
0816
0817     BUG_ON(sel->parent_count > (u32)U8_MAX);
0818     for (i = 0; i < sel->parent_count; i++)
0819         if (sel->parent_sel[i] == parent_sel)
0820             return i;
0821     return BAD_CLK_INDEX;
0822 }
0823
0824 /*
0825  * Fetch the current value of the selector, and translate that into
0826  * its corresponding index in the parent array we registered with
0827  * the clock framework.
0828  *
0829  * Returns parent array index that corresponds with the value found,
0830  * or BAD_CLK_INDEX if the found value is out of range.
0831  */
0832 static u8 selector_read_index(struct ccu_data *ccu, struct bcm_clk_sel *sel)
0833 {
0834     unsigned long flags;
0835     u32 reg_val;
0836     u32 parent_sel;
0837     u8 index;
0838
0839     /* If there's no selector, there's only one parent */
0840     if (!selector_exists(sel))
0841         return 0;
0842
0843     /* Get the value in the selector register */
0844     flags = ccu_lock(ccu);
0845     reg_val = __ccu_read(ccu, sel->offset);
0846     ccu_unlock(ccu, flags);
0847
0848     parent_sel = bitfield_extract(reg_val, sel->shift, sel->width);
0849
0850     /* Look up that selector's parent array index and return it */
0851     index = parent_index(sel, parent_sel);
0852     if (index == BAD_CLK_INDEX)
0853         pr_err("%s: out-of-range parent selector %u (%s 0x%04x)\n",
0854             __func__, parent_sel, ccu->name, sel->offset);
0855
0856     return index;
0857 }
0858
0859 /*
0860  * Commit our desired selector value to the hardware.
0861  *
0862  * Returns 0 on success.  Returns -EINVAL for invalid arguments.
0863  * Returns -ENXIO if gating failed, and -EIO if a trigger failed.
0864  */
0865 static int
0866 __sel_commit(struct ccu_data *ccu, struct bcm_clk_gate *gate,
0867             struct bcm_clk_sel *sel, struct bcm_clk_trig *trig)
0868 {
0869     u32 parent_sel;
0870     u32 reg_val;
0871     bool enabled;
0872     int ret = 0;
0873
0874     BUG_ON(!selector_exists(sel));
0875
0876     /*
0877      * If we're just initializing the selector, and no initial
0878      * state was defined in the device tree, we just find out
0879      * what its current value is rather than updating it.
0880      */
0881     if (sel->clk_index == BAD_CLK_INDEX) {
0882         u8 index;
0883
0884         reg_val = __ccu_read(ccu, sel->offset);
0885         parent_sel = bitfield_extract(reg_val, sel->shift, sel->width);
0886         index = parent_index(sel, parent_sel);
0887         if (index == BAD_CLK_INDEX)
0888             return -EINVAL;
0889         sel->clk_index = index;
0890
0891         return 0;
0892     }
0893
0894     BUG_ON((u32)sel->clk_index >= sel->parent_count);
0895     parent_sel = sel->parent_sel[sel->clk_index];
0896
0897     /* Clock needs to be enabled before changing the parent */
0898     enabled = __is_clk_gate_enabled(ccu, gate);
0899     if (!enabled && !__clk_gate(ccu, gate, true))
0900         return -ENXIO;
0901
0902     /* Replace the selector value and record the result */
0903     reg_val = __ccu_read(ccu, sel->offset);
0904     reg_val = bitfield_replace(reg_val, sel->shift, sel->width, parent_sel);
0905     __ccu_write(ccu, sel->offset, reg_val);
0906
0907     /* If the trigger fails we still want to disable the gate */
0908     if (!__clk_trigger(ccu, trig))
0909         ret = -EIO;
0910
0911     /* Disable the clock again if it was disabled to begin with */
0912     if (!enabled && !__clk_gate(ccu, gate, false))
0913         ret = ret ? ret : -ENXIO;   /* return first error */
0914
0915     return ret;
0916 }
0917
0918 /*
0919  * Initialize a selector by committing our desired state to hardware
0920  * without the usual checks to see if it's already set up that way.
0921  * Returns true if successful, false otherwise.
0922  */
0923 static bool sel_init(struct ccu_data *ccu, struct bcm_clk_gate *gate,
0924             struct bcm_clk_sel *sel, struct bcm_clk_trig *trig)
0925 {
0926     if (!selector_exists(sel))
0927         return true;
0928     return !__sel_commit(ccu, gate, sel, trig);
0929 }
0930
0931 /*
0932  * Write a new value into a selector register to switch to a
0933  * different parent clock.  Returns 0 on success, or an error code
0934  * (from __sel_commit()) otherwise.
0935  */
0936 static int selector_write(struct ccu_data *ccu, struct bcm_clk_gate *gate,
0937             struct bcm_clk_sel *sel, struct bcm_clk_trig *trig,
0938             u8 index)
0939 {
0940     unsigned long flags;
0941     u8 previous;
0942     int ret;
0943
0944     previous = sel->clk_index;
0945     if (previous == index)
0946         return 0;   /* No change */
0947
0948     sel->clk_index = index;
0949
0950     flags = ccu_lock(ccu);
0951     __ccu_write_enable(ccu);
0952
0953     ret = __sel_commit(ccu, gate, sel, trig);
0954
0955     __ccu_write_disable(ccu);
0956     ccu_unlock(ccu, flags);
0957
0958     if (ret)
0959         sel->clk_index = previous;  /* Revert the change */
0960
0961     return ret;
0962 }
0963
0964 /* Clock operations */
0965
0966 static int kona_peri_clk_enable(struct clk_hw *hw)
0967 {
0968     struct kona_clk *bcm_clk = to_kona_clk(hw);
0969     struct bcm_clk_gate *gate = &bcm_clk->u.peri->gate;
0970
0971     return clk_gate(bcm_clk->ccu, bcm_clk->init_data.name, gate, true);
0972 }
0973
0974 static void kona_peri_clk_disable(struct clk_hw *hw)
0975 {
0976     struct kona_clk *bcm_clk = to_kona_clk(hw);
0977     struct bcm_clk_gate *gate = &bcm_clk->u.peri->gate;
0978
0979     (void)clk_gate(bcm_clk->ccu, bcm_clk->init_data.name, gate, false);
0980 }
0981
0982 static int kona_peri_clk_is_enabled(struct clk_hw *hw)
0983 {
0984     struct kona_clk *bcm_clk = to_kona_clk(hw);
0985     struct bcm_clk_gate *gate = &bcm_clk->u.peri->gate;
0986
0987     return is_clk_gate_enabled(bcm_clk->ccu, gate) ? 1 : 0;
0988 }
0989
0990 static unsigned long kona_peri_clk_recalc_rate(struct clk_hw *hw,
0991             unsigned long parent_rate)
0992 {
0993     struct kona_clk *bcm_clk = to_kona_clk(hw);
0994     struct peri_clk_data *data = bcm_clk->u.peri;
0995
0996     return clk_recalc_rate(bcm_clk->ccu, &data->div, &data->pre_div,
0997                 parent_rate);
0998 }
0999
1000 static long kona_peri_clk_round_rate(struct clk_hw *hw, unsigned long rate,
1001             unsigned long *parent_rate)
1002 {
1003     struct kona_clk *bcm_clk = to_kona_clk(hw);
1004     struct bcm_clk_div *div = &bcm_clk->u.peri->div;
1005
1006     if (!divider_exists(div))
1007         return clk_hw_get_rate(hw);
1008
1009     /* Quietly avoid a zero rate */
1010     return round_rate(bcm_clk->ccu, div, &bcm_clk->u.peri->pre_div,
1011                 rate ? rate : 1, *parent_rate, NULL);
1012 }
1013
1014 static int kona_peri_clk_determine_rate(struct clk_hw *hw,
1015                     struct clk_rate_request *req)
1016 {
1017     struct kona_clk *bcm_clk = to_kona_clk(hw);
1018     struct clk_hw *current_parent;
1019     unsigned long parent_rate;
1020     unsigned long best_delta;
1021     unsigned long best_rate;
1022     u32 parent_count;
1023     long rate;
1024     u32 which;
1025
1026     /*
1027      * If there is no other parent to choose, use the current one.
1028      * Note:  We don't honor (or use) CLK_SET_RATE_NO_REPARENT.
1029      */
1030     WARN_ON_ONCE(bcm_clk->init_data.flags & CLK_SET_RATE_NO_REPARENT);
1031     parent_count = (u32)bcm_clk->init_data.num_parents;
1032     if (parent_count < 2) {
1033         rate = kona_peri_clk_round_rate(hw, req->rate,
1034                         &req->best_parent_rate);
1035         if (rate < 0)
1036             return rate;
1037
1038         req->rate = rate;
1039         return 0;
1040     }
1041
1042     /* Unless we can do better, stick with current parent */
1043     current_parent = clk_hw_get_parent(hw);
1044     parent_rate = clk_hw_get_rate(current_parent);
1045     best_rate = kona_peri_clk_round_rate(hw, req->rate, &parent_rate);
1046     best_delta = abs(best_rate - req->rate);
1047
1048     /* Check whether any other parent clock can produce a better result */
1049     for (which = 0; which < parent_count; which++) {
1050         struct clk_hw *parent = clk_hw_get_parent_by_index(hw, which);
1051         unsigned long delta;
1052         unsigned long other_rate;
1053
1054         BUG_ON(!parent);
1055         if (parent == current_parent)
1056             continue;
1057
1058         /* We don't support CLK_SET_RATE_PARENT */
1059         parent_rate = clk_hw_get_rate(parent);
1060         other_rate = kona_peri_clk_round_rate(hw, req->rate,
1061                               &parent_rate);
1062         delta = abs(other_rate - req->rate);
1063         if (delta < best_delta) {
1064             best_delta = delta;
1065             best_rate = other_rate;
1066             req->best_parent_hw = parent;
1067             req->best_parent_rate = parent_rate;
1068         }
1069     }
1070
1071     req->rate = best_rate;
1072     return 0;
1073 }
1074
1075 static int kona_peri_clk_set_parent(struct clk_hw *hw, u8 index)
1076 {
1077     struct kona_clk *bcm_clk = to_kona_clk(hw);
1078     struct peri_clk_data *data = bcm_clk->u.peri;
1079     struct bcm_clk_sel *sel = &data->sel;
1080     struct bcm_clk_trig *trig;
1081     int ret;
1082
1083     BUG_ON(index >= sel->parent_count);
1084
1085     /* If there's only one parent we don't require a selector */
1086     if (!selector_exists(sel))
1087         return 0;
1088
1089     /*
1090      * The regular trigger is used by default, but if there's a
1091      * pre-trigger we want to use that instead.
1092      */
1093     trig = trigger_exists(&data->pre_trig) ? &data->pre_trig
1094                            : &data->trig;
1095
1096     ret = selector_write(bcm_clk->ccu, &data->gate, sel, trig, index);
1097     if (ret == -ENXIO) {
1098         pr_err("%s: gating failure for %s\n", __func__,
1099             bcm_clk->init_data.name);
1100         ret = -EIO; /* Don't proliferate weird errors */
1101     } else if (ret == -EIO) {
1102         pr_err("%s: %strigger failed for %s\n", __func__,
1103             trig == &data->pre_trig ? "pre-" : "",
1104             bcm_clk->init_data.name);
1105     }
1106
1107     return ret;
1108 }
1109
1110 static u8 kona_peri_clk_get_parent(struct clk_hw *hw)
1111 {
1112     struct kona_clk *bcm_clk = to_kona_clk(hw);
1113     struct peri_clk_data *data = bcm_clk->u.peri;
1114     u8 index;
1115
1116     index = selector_read_index(bcm_clk->ccu, &data->sel);
1117
1118     /* Not all callers would handle an out-of-range value gracefully */
1119     return index == BAD_CLK_INDEX ? 0 : index;
1120 }
1121
1122 static int kona_peri_clk_set_rate(struct clk_hw *hw, unsigned long rate,
1123             unsigned long parent_rate)
1124 {
1125     struct kona_clk *bcm_clk = to_kona_clk(hw);
1126     struct peri_clk_data *data = bcm_clk->u.peri;
1127     struct bcm_clk_div *div = &data->div;
1128     u64 scaled_div = 0;
1129     int ret;
1130
1131     if (parent_rate > (unsigned long)LONG_MAX)
1132         return -EINVAL;
1133
1134     if (rate == clk_hw_get_rate(hw))
1135         return 0;
1136
1137     if (!divider_exists(div))
1138         return rate == parent_rate ? 0 : -EINVAL;
1139
1140     /*
1141      * A fixed divider can't be changed.  (Nor can a fixed
1142      * pre-divider be, but for now we never actually try to
1143      * change that.)  Tolerate a request for a no-op change.
1144      */
1145     if (divider_is_fixed(&data->div))
1146         return rate == parent_rate ? 0 : -EINVAL;
1147
1148     /*
1149      * Get the scaled divisor value needed to achieve a clock
1150      * rate as close as possible to what was requested, given
1151      * the parent clock rate supplied.
1152      */
1153     (void)round_rate(bcm_clk->ccu, div, &data->pre_div,
1154                 rate ? rate : 1, parent_rate, &scaled_div);
1155
1156     /*
1157      * We aren't updating any pre-divider at this point, so
1158      * we'll use the regular trigger.
1159      */
1160     ret = divider_write(bcm_clk->ccu, &data->gate, &data->div,
1161                 &data->trig, scaled_div);
1162     if (ret == -ENXIO) {
1163         pr_err("%s: gating failure for %s\n", __func__,
1164             bcm_clk->init_data.name);
1165         ret = -EIO; /* Don't proliferate weird errors */
1166     } else if (ret == -EIO) {
1167         pr_err("%s: trigger failed for %s\n", __func__,
1168             bcm_clk->init_data.name);
1169     }
1170
1171     return ret;
1172 }
1173
1174 struct clk_ops kona_peri_clk_ops = {
1175     .enable = kona_peri_clk_enable,
1176     .disable = kona_peri_clk_disable,
1177     .is_enabled = kona_peri_clk_is_enabled,
1178     .recalc_rate = kona_peri_clk_recalc_rate,
1179     .determine_rate = kona_peri_clk_determine_rate,
1180     .set_parent = kona_peri_clk_set_parent,
1181     .get_parent = kona_peri_clk_get_parent,
1182     .set_rate = kona_peri_clk_set_rate,
1183 };
1184
1185 /* Put a peripheral clock into its initial state */
1186 static bool __peri_clk_init(struct kona_clk *bcm_clk)
1187 {
1188     struct ccu_data *ccu = bcm_clk->ccu;
1189     struct peri_clk_data *peri = bcm_clk->u.peri;
1190     const char *name = bcm_clk->init_data.name;
1191     struct bcm_clk_trig *trig;
1192
1193     BUG_ON(bcm_clk->type != bcm_clk_peri);
1194
1195     if (!policy_init(ccu, &peri->policy)) {
1196         pr_err("%s: error initializing policy for %s\n",
1197             __func__, name);
1198         return false;
1199     }
1200     if (!gate_init(ccu, &peri->gate)) {
1201         pr_err("%s: error initializing gate for %s\n", __func__, name);
1202         return false;
1203     }
1204     if (!hyst_init(ccu, &peri->hyst)) {
1205         pr_err("%s: error initializing hyst for %s\n", __func__, name);
1206         return false;
1207     }
1208     if (!div_init(ccu, &peri->gate, &peri->div, &peri->trig)) {
1209         pr_err("%s: error initializing divider for %s\n", __func__,
1210             name);
1211         return false;
1212     }
1213
1214     /*
1215      * For the pre-divider and selector, the pre-trigger is used
1216      * if it's present, otherwise we just use the regular trigger.
1217      */
1218     trig = trigger_exists(&peri->pre_trig) ? &peri->pre_trig
1219                            : &peri->trig;
1220
1221     if (!div_init(ccu, &peri->gate, &peri->pre_div, trig)) {
1222         pr_err("%s: error initializing pre-divider for %s\n", __func__,
1223             name);
1224         return false;
1225     }
1226
1227     if (!sel_init(ccu, &peri->gate, &peri->sel, trig)) {
1228         pr_err("%s: error initializing selector for %s\n", __func__,
1229             name);
1230         return false;
1231     }
1232
1233     return true;
1234 }
1235
1236 static bool __kona_clk_init(struct kona_clk *bcm_clk)
1237 {
1238     switch (bcm_clk->type) {
1239     case bcm_clk_peri:
1240         return __peri_clk_init(bcm_clk);
1241     default:
1242         BUG();
1243     }
1244     return false;
1245 }
1246
1247 /* Set a CCU and all its clocks into their desired initial state */
1248 bool __init kona_ccu_init(struct ccu_data *ccu)
1249 {
1250     unsigned long flags;
1251     unsigned int which;
1252     struct kona_clk *kona_clks = ccu->kona_clks;
1253     bool success = true;
1254
1255     flags = ccu_lock(ccu);
1256     __ccu_write_enable(ccu);
1257
1258     for (which = 0; which < ccu->clk_num; which++) {
1259         struct kona_clk *bcm_clk = &kona_clks[which];
1260
1261         if (!bcm_clk->ccu)
1262             continue;
1263
1264         success &= __kona_clk_init(bcm_clk);
1265     }
1266
1267     __ccu_write_disable(ccu);
1268     ccu_unlock(ccu, flags);
1269     return success;
1270 }