clk/bcm/clk-iproc.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /* Copyright (C) 2014 Broadcom Corporation */
0003
0004 #ifndef _CLK_IPROC_H
0005 #define _CLK_IPROC_H
0006
0007 #include <linux/kernel.h>
0008 #include <linux/list.h>
0009 #include <linux/spinlock.h>
0010 #include <linux/slab.h>
0011 #include <linux/device.h>
0012 #include <linux/of.h>
0013 #include <linux/clk-provider.h>
0014
0015 #define IPROC_CLK_NAME_LEN 25
0016 #define IPROC_CLK_INVALID_OFFSET 0xffffffff
0017 #define bit_mask(width) ((1 << (width)) - 1)
0018
0019 /* clocks that should not be disabled at runtime */
0020 #define IPROC_CLK_AON BIT(0)
0021
0022 /* PLL that requires gating through ASIU */
0023 #define IPROC_CLK_PLL_ASIU BIT(1)
0024
0025 /* PLL that has fractional part of the NDIV */
0026 #define IPROC_CLK_PLL_HAS_NDIV_FRAC BIT(2)
0027
0028 /*
0029  * Some of the iProc PLL/clocks may have an ASIC bug that requires read back
0030  * of the same register following the write to flush the write transaction into
0031  * the intended register
0032  */
0033 #define IPROC_CLK_NEEDS_READ_BACK BIT(3)
0034
0035 /*
0036  * Some PLLs require the PLL SW override bit to be set before changes can be
0037  * applied to the PLL
0038  */
0039 #define IPROC_CLK_PLL_NEEDS_SW_CFG BIT(4)
0040
0041 /*
0042  * Some PLLs use a different way to control clock power, via the PWRDWN bit in
0043  * the PLL control register
0044  */
0045 #define IPROC_CLK_EMBED_PWRCTRL BIT(5)
0046
0047 /*
0048  * Some PLLs have separate registers for Status and Control.  Identify this to
0049  * let the driver know if additional registers need to be used
0050  */
0051 #define IPROC_CLK_PLL_SPLIT_STAT_CTRL BIT(6)
0052
0053 /*
0054  * Some PLLs have an additional divide by 2 in master clock calculation;
0055  * MCLK = VCO_freq / (Mdiv * 2). Identify this to let the driver know
0056  * of modified calculations
0057  */
0058 #define IPROC_CLK_MCLK_DIV_BY_2 BIT(7)
0059
0060 /*
0061  * Some PLLs provide a look up table for the leaf clock frequencies and
0062  * auto calculates VCO frequency parameters based on the provided leaf
0063  * clock frequencies. They have a user mode that allows the divider
0064  * controls to be determined by the user
0065  */
0066 #define IPROC_CLK_PLL_USER_MODE_ON BIT(8)
0067
0068 /*
0069  * Some PLLs have an active low reset
0070  */
0071 #define IPROC_CLK_PLL_RESET_ACTIVE_LOW BIT(9)
0072
0073 /*
0074  * Calculate the PLL parameters are runtime, instead of using table
0075  */
0076 #define IPROC_CLK_PLL_CALC_PARAM BIT(10)
0077
0078 /*
0079  * Parameters for VCO frequency configuration
0080  *
0081  * VCO frequency =
0082  * ((ndiv_int + ndiv_frac / 2^20) * (ref frequency  / pdiv)
0083  */
0084 struct iproc_pll_vco_param {
0085     unsigned long rate;
0086     unsigned int ndiv_int;
0087     unsigned int ndiv_frac;
0088     unsigned int pdiv;
0089 };
0090
0091 struct iproc_clk_reg_op {
0092     unsigned int offset;
0093     unsigned int shift;
0094     unsigned int width;
0095 };
0096
0097 /*
0098  * Clock gating control at the top ASIU level
0099  */
0100 struct iproc_asiu_gate {
0101     unsigned int offset;
0102     unsigned int en_shift;
0103 };
0104
0105 /*
0106  * Control of powering on/off of a PLL
0107  *
0108  * Before powering off a PLL, input isolation (ISO) needs to be enabled
0109  */
0110 struct iproc_pll_aon_pwr_ctrl {
0111     unsigned int offset;
0112     unsigned int pwr_width;
0113     unsigned int pwr_shift;
0114     unsigned int iso_shift;
0115 };
0116
0117 /*
0118  * Control of the PLL reset
0119  */
0120 struct iproc_pll_reset_ctrl {
0121     unsigned int offset;
0122     unsigned int reset_shift;
0123     unsigned int p_reset_shift;
0124 };
0125
0126 /*
0127  * Control of the Ki, Kp, and Ka parameters
0128  */
0129 struct iproc_pll_dig_filter_ctrl {
0130     unsigned int offset;
0131     unsigned int ki_shift;
0132     unsigned int ki_width;
0133     unsigned int kp_shift;
0134     unsigned int kp_width;
0135     unsigned int ka_shift;
0136     unsigned int ka_width;
0137 };
0138
0139 /*
0140  * To enable SW control of the PLL
0141  */
0142 struct iproc_pll_sw_ctrl {
0143     unsigned int offset;
0144     unsigned int shift;
0145 };
0146
0147 struct iproc_pll_vco_ctrl {
0148     unsigned int u_offset;
0149     unsigned int l_offset;
0150 };
0151
0152 /*
0153  * Main PLL control parameters
0154  */
0155 struct iproc_pll_ctrl {
0156     unsigned long flags;
0157     struct iproc_pll_aon_pwr_ctrl aon;
0158     struct iproc_asiu_gate asiu;
0159     struct iproc_pll_reset_ctrl reset;
0160     struct iproc_pll_dig_filter_ctrl dig_filter;
0161     struct iproc_pll_sw_ctrl sw_ctrl;
0162     struct iproc_clk_reg_op ndiv_int;
0163     struct iproc_clk_reg_op ndiv_frac;
0164     struct iproc_clk_reg_op pdiv;
0165     struct iproc_pll_vco_ctrl vco_ctrl;
0166     struct iproc_clk_reg_op status;
0167     struct iproc_clk_reg_op macro_mode;
0168 };
0169
0170 /*
0171  * Controls enabling/disabling a PLL derived clock
0172  */
0173 struct iproc_clk_enable_ctrl {
0174     unsigned int offset;
0175     unsigned int enable_shift;
0176     unsigned int hold_shift;
0177     unsigned int bypass_shift;
0178 };
0179
0180 /*
0181  * Main clock control parameters for clocks derived from the PLLs
0182  */
0183 struct iproc_clk_ctrl {
0184     unsigned int channel;
0185     unsigned long flags;
0186     struct iproc_clk_enable_ctrl enable;
0187     struct iproc_clk_reg_op mdiv;
0188 };
0189
0190 /*
0191  * Divisor of the ASIU clocks
0192  */
0193 struct iproc_asiu_div {
0194     unsigned int offset;
0195     unsigned int en_shift;
0196     unsigned int high_shift;
0197     unsigned int high_width;
0198     unsigned int low_shift;
0199     unsigned int low_width;
0200 };
0201
0202 void iproc_armpll_setup(struct device_node *node);
0203 void iproc_pll_clk_setup(struct device_node *node,
0204              const struct iproc_pll_ctrl *pll_ctrl,
0205              const struct iproc_pll_vco_param *vco,
0206              unsigned int num_vco_entries,
0207              const struct iproc_clk_ctrl *clk_ctrl,
0208              unsigned int num_clks);
0209 void iproc_asiu_setup(struct device_node *node,
0210               const struct iproc_asiu_div *div,
0211               const struct iproc_asiu_gate *gate,
0212               unsigned int num_clks);
0213
0214 #endif /* _CLK_IPROC_H */