clk/bcm/clk-cygnus.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 // Copyright (C) 2014 Broadcom Corporation
0003
0004 #include <linux/kernel.h>
0005 #include <linux/err.h>
0006 #include <linux/clk-provider.h>
0007 #include <linux/io.h>
0008 #include <linux/of.h>
0009 #include <linux/clkdev.h>
0010 #include <linux/of_address.h>
0011 #include <linux/delay.h>
0012
0013 #include <dt-bindings/clock/bcm-cygnus.h>
0014 #include "clk-iproc.h"
0015
0016 #define REG_VAL(o, s, w) { .offset = o, .shift = s, .width = w, }
0017
0018 #define AON_VAL(o, pw, ps, is) { .offset = o, .pwr_width = pw, \
0019     .pwr_shift = ps, .iso_shift = is }
0020
0021 #define SW_CTRL_VAL(o, s) { .offset = o, .shift = s, }
0022
0023 #define ASIU_DIV_VAL(o, es, hs, hw, ls, lw) \
0024         { .offset = o, .en_shift = es, .high_shift = hs, \
0025         .high_width = hw, .low_shift = ls, .low_width = lw }
0026
0027 #define RESET_VAL(o, rs, prs) { .offset = o, .reset_shift = rs, \
0028     .p_reset_shift = prs }
0029
0030 #define DF_VAL(o, kis, kiw, kps, kpw, kas, kaw) { .offset = o, .ki_shift = kis,\
0031     .ki_width = kiw, .kp_shift = kps, .kp_width = kpw, .ka_shift = kas,    \
0032     .ka_width = kaw }
0033
0034 #define VCO_CTRL_VAL(uo, lo) { .u_offset = uo, .l_offset = lo }
0035
0036 #define ENABLE_VAL(o, es, hs, bs) { .offset = o, .enable_shift = es, \
0037     .hold_shift = hs, .bypass_shift = bs }
0038
0039 #define ASIU_GATE_VAL(o, es) { .offset = o, .en_shift = es }
0040
0041 static void __init cygnus_armpll_init(struct device_node *node)
0042 {
0043     iproc_armpll_setup(node);
0044 }
0045 CLK_OF_DECLARE(cygnus_armpll, "brcm,cygnus-armpll", cygnus_armpll_init);
0046
0047 static const struct iproc_pll_ctrl genpll = {
0048     .flags = IPROC_CLK_AON | IPROC_CLK_PLL_HAS_NDIV_FRAC |
0049         IPROC_CLK_PLL_NEEDS_SW_CFG,
0050     .aon = AON_VAL(0x0, 2, 1, 0),
0051     .reset = RESET_VAL(0x0, 11, 10),
0052     .dig_filter = DF_VAL(0x0, 4, 3, 0, 4, 7, 3),
0053     .sw_ctrl = SW_CTRL_VAL(0x10, 31),
0054     .ndiv_int = REG_VAL(0x10, 20, 10),
0055     .ndiv_frac = REG_VAL(0x10, 0, 20),
0056     .pdiv = REG_VAL(0x14, 0, 4),
0057     .vco_ctrl = VCO_CTRL_VAL(0x18, 0x1c),
0058     .status = REG_VAL(0x28, 12, 1),
0059 };
0060
0061 static const struct iproc_clk_ctrl genpll_clk[] = {
0062     [BCM_CYGNUS_GENPLL_AXI21_CLK] = {
0063         .channel = BCM_CYGNUS_GENPLL_AXI21_CLK,
0064         .flags = IPROC_CLK_AON,
0065         .enable = ENABLE_VAL(0x4, 6, 0, 12),
0066         .mdiv = REG_VAL(0x20, 0, 8),
0067     },
0068     [BCM_CYGNUS_GENPLL_250MHZ_CLK] = {
0069         .channel = BCM_CYGNUS_GENPLL_250MHZ_CLK,
0070         .flags = IPROC_CLK_AON,
0071         .enable = ENABLE_VAL(0x4, 7, 1, 13),
0072         .mdiv = REG_VAL(0x20, 10, 8),
0073     },
0074     [BCM_CYGNUS_GENPLL_IHOST_SYS_CLK] = {
0075         .channel = BCM_CYGNUS_GENPLL_IHOST_SYS_CLK,
0076         .flags = IPROC_CLK_AON,
0077         .enable = ENABLE_VAL(0x4, 8, 2, 14),
0078         .mdiv = REG_VAL(0x20, 20, 8),
0079     },
0080     [BCM_CYGNUS_GENPLL_ENET_SW_CLK] = {
0081         .channel = BCM_CYGNUS_GENPLL_ENET_SW_CLK,
0082         .flags = IPROC_CLK_AON,
0083         .enable = ENABLE_VAL(0x4, 9, 3, 15),
0084         .mdiv = REG_VAL(0x24, 0, 8),
0085     },
0086     [BCM_CYGNUS_GENPLL_AUDIO_125_CLK] = {
0087         .channel = BCM_CYGNUS_GENPLL_AUDIO_125_CLK,
0088         .flags = IPROC_CLK_AON,
0089         .enable = ENABLE_VAL(0x4, 10, 4, 16),
0090         .mdiv = REG_VAL(0x24, 10, 8),
0091     },
0092     [BCM_CYGNUS_GENPLL_CAN_CLK] = {
0093         .channel = BCM_CYGNUS_GENPLL_CAN_CLK,
0094         .flags = IPROC_CLK_AON,
0095         .enable = ENABLE_VAL(0x4, 11, 5, 17),
0096         .mdiv = REG_VAL(0x24, 20, 8),
0097     },
0098 };
0099
0100 static void __init cygnus_genpll_clk_init(struct device_node *node)
0101 {
0102     iproc_pll_clk_setup(node, &genpll, NULL, 0, genpll_clk,
0103                 ARRAY_SIZE(genpll_clk));
0104 }
0105 CLK_OF_DECLARE(cygnus_genpll, "brcm,cygnus-genpll", cygnus_genpll_clk_init);
0106
0107 static const struct iproc_pll_ctrl lcpll0 = {
0108     .flags = IPROC_CLK_AON | IPROC_CLK_PLL_NEEDS_SW_CFG,
0109     .aon = AON_VAL(0x0, 2, 5, 4),
0110     .reset = RESET_VAL(0x0, 31, 30),
0111     .dig_filter = DF_VAL(0x0, 27, 3, 23, 4, 19, 4),
0112     .sw_ctrl = SW_CTRL_VAL(0x4, 31),
0113     .ndiv_int = REG_VAL(0x4, 16, 10),
0114     .pdiv = REG_VAL(0x4, 26, 4),
0115     .vco_ctrl = VCO_CTRL_VAL(0x10, 0x14),
0116     .status = REG_VAL(0x18, 12, 1),
0117 };
0118
0119 static const struct iproc_clk_ctrl lcpll0_clk[] = {
0120     [BCM_CYGNUS_LCPLL0_PCIE_PHY_REF_CLK] = {
0121         .channel = BCM_CYGNUS_LCPLL0_PCIE_PHY_REF_CLK,
0122         .flags = IPROC_CLK_AON,
0123         .enable = ENABLE_VAL(0x0, 7, 1, 13),
0124         .mdiv = REG_VAL(0x8, 0, 8),
0125     },
0126     [BCM_CYGNUS_LCPLL0_DDR_PHY_CLK] = {
0127         .channel = BCM_CYGNUS_LCPLL0_DDR_PHY_CLK,
0128         .flags = IPROC_CLK_AON,
0129         .enable = ENABLE_VAL(0x0, 8, 2, 14),
0130         .mdiv = REG_VAL(0x8, 10, 8),
0131     },
0132     [BCM_CYGNUS_LCPLL0_SDIO_CLK] = {
0133         .channel = BCM_CYGNUS_LCPLL0_SDIO_CLK,
0134         .flags = IPROC_CLK_AON,
0135         .enable = ENABLE_VAL(0x0, 9, 3, 15),
0136         .mdiv = REG_VAL(0x8, 20, 8),
0137     },
0138     [BCM_CYGNUS_LCPLL0_USB_PHY_REF_CLK] = {
0139         .channel = BCM_CYGNUS_LCPLL0_USB_PHY_REF_CLK,
0140         .flags = IPROC_CLK_AON,
0141         .enable = ENABLE_VAL(0x0, 10, 4, 16),
0142         .mdiv = REG_VAL(0xc, 0, 8),
0143     },
0144     [BCM_CYGNUS_LCPLL0_SMART_CARD_CLK] = {
0145         .channel = BCM_CYGNUS_LCPLL0_SMART_CARD_CLK,
0146         .flags = IPROC_CLK_AON,
0147         .enable = ENABLE_VAL(0x0, 11, 5, 17),
0148         .mdiv = REG_VAL(0xc, 10, 8),
0149     },
0150     [BCM_CYGNUS_LCPLL0_CH5_UNUSED] = {
0151         .channel = BCM_CYGNUS_LCPLL0_CH5_UNUSED,
0152         .flags = IPROC_CLK_AON,
0153         .enable = ENABLE_VAL(0x0, 12, 6, 18),
0154         .mdiv = REG_VAL(0xc, 20, 8),
0155     },
0156 };
0157
0158 static void __init cygnus_lcpll0_clk_init(struct device_node *node)
0159 {
0160     iproc_pll_clk_setup(node, &lcpll0, NULL, 0, lcpll0_clk,
0161                 ARRAY_SIZE(lcpll0_clk));
0162 }
0163 CLK_OF_DECLARE(cygnus_lcpll0, "brcm,cygnus-lcpll0", cygnus_lcpll0_clk_init);
0164
0165 /*
0166  * MIPI PLL VCO frequency parameter table
0167  */
0168 static const struct iproc_pll_vco_param mipipll_vco_params[] = {
0169     /* rate (Hz) ndiv_int ndiv_frac pdiv */
0170     { 750000000UL,   30,     0,        1 },
0171     { 1000000000UL,  40,     0,        1 },
0172     { 1350000000ul,  54,     0,        1 },
0173     { 2000000000UL,  80,     0,        1 },
0174     { 2100000000UL,  84,     0,        1 },
0175     { 2250000000UL,  90,     0,        1 },
0176     { 2500000000UL,  100,    0,        1 },
0177     { 2700000000UL,  54,     0,        0 },
0178     { 2975000000UL,  119,    0,        1 },
0179     { 3100000000UL,  124,    0,        1 },
0180     { 3150000000UL,  126,    0,        1 },
0181 };
0182
0183 static const struct iproc_pll_ctrl mipipll = {
0184     .flags = IPROC_CLK_PLL_ASIU | IPROC_CLK_PLL_HAS_NDIV_FRAC |
0185          IPROC_CLK_NEEDS_READ_BACK,
0186     .aon = AON_VAL(0x0, 4, 17, 16),
0187     .asiu = ASIU_GATE_VAL(0x0, 3),
0188     .reset = RESET_VAL(0x0, 11, 10),
0189     .dig_filter = DF_VAL(0x0, 4, 3, 0, 4, 7, 4),
0190     .ndiv_int = REG_VAL(0x10, 20, 10),
0191     .ndiv_frac = REG_VAL(0x10, 0, 20),
0192     .pdiv = REG_VAL(0x14, 0, 4),
0193     .vco_ctrl = VCO_CTRL_VAL(0x18, 0x1c),
0194     .status = REG_VAL(0x28, 12, 1),
0195 };
0196
0197 static const struct iproc_clk_ctrl mipipll_clk[] = {
0198     [BCM_CYGNUS_MIPIPLL_CH0_UNUSED] = {
0199         .channel = BCM_CYGNUS_MIPIPLL_CH0_UNUSED,
0200         .flags = IPROC_CLK_NEEDS_READ_BACK,
0201         .enable = ENABLE_VAL(0x4, 12, 6, 18),
0202         .mdiv = REG_VAL(0x20, 0, 8),
0203     },
0204     [BCM_CYGNUS_MIPIPLL_CH1_LCD] = {
0205         .channel = BCM_CYGNUS_MIPIPLL_CH1_LCD,
0206         .flags = IPROC_CLK_NEEDS_READ_BACK,
0207         .enable = ENABLE_VAL(0x4, 13, 7, 19),
0208         .mdiv = REG_VAL(0x20, 10, 8),
0209     },
0210     [BCM_CYGNUS_MIPIPLL_CH2_V3D] = {
0211         .channel = BCM_CYGNUS_MIPIPLL_CH2_V3D,
0212         .flags = IPROC_CLK_NEEDS_READ_BACK,
0213         .enable = ENABLE_VAL(0x4, 14, 8, 20),
0214         .mdiv = REG_VAL(0x20, 20, 8),
0215     },
0216     [BCM_CYGNUS_MIPIPLL_CH3_UNUSED] = {
0217         .channel = BCM_CYGNUS_MIPIPLL_CH3_UNUSED,
0218         .flags = IPROC_CLK_NEEDS_READ_BACK,
0219         .enable = ENABLE_VAL(0x4, 15, 9, 21),
0220         .mdiv = REG_VAL(0x24, 0, 8),
0221     },
0222     [BCM_CYGNUS_MIPIPLL_CH4_UNUSED] = {
0223         .channel = BCM_CYGNUS_MIPIPLL_CH4_UNUSED,
0224         .flags = IPROC_CLK_NEEDS_READ_BACK,
0225         .enable = ENABLE_VAL(0x4, 16, 10, 22),
0226         .mdiv = REG_VAL(0x24, 10, 8),
0227     },
0228     [BCM_CYGNUS_MIPIPLL_CH5_UNUSED] = {
0229         .channel = BCM_CYGNUS_MIPIPLL_CH5_UNUSED,
0230         .flags = IPROC_CLK_NEEDS_READ_BACK,
0231         .enable = ENABLE_VAL(0x4, 17, 11, 23),
0232         .mdiv = REG_VAL(0x24, 20, 8),
0233     },
0234 };
0235
0236 static void __init cygnus_mipipll_clk_init(struct device_node *node)
0237 {
0238     iproc_pll_clk_setup(node, &mipipll, mipipll_vco_params,
0239                 ARRAY_SIZE(mipipll_vco_params), mipipll_clk,
0240                 ARRAY_SIZE(mipipll_clk));
0241 }
0242 CLK_OF_DECLARE(cygnus_mipipll, "brcm,cygnus-mipipll", cygnus_mipipll_clk_init);
0243
0244 static const struct iproc_asiu_div asiu_div[] = {
0245     [BCM_CYGNUS_ASIU_KEYPAD_CLK] = ASIU_DIV_VAL(0x0, 31, 16, 10, 0, 10),
0246     [BCM_CYGNUS_ASIU_ADC_CLK] = ASIU_DIV_VAL(0x4, 31, 16, 10, 0, 10),
0247     [BCM_CYGNUS_ASIU_PWM_CLK] = ASIU_DIV_VAL(0x8, 31, 16, 10, 0, 10),
0248 };
0249
0250 static const struct iproc_asiu_gate asiu_gate[] = {
0251     [BCM_CYGNUS_ASIU_KEYPAD_CLK] = ASIU_GATE_VAL(0x0, 7),
0252     [BCM_CYGNUS_ASIU_ADC_CLK] = ASIU_GATE_VAL(0x0, 9),
0253     [BCM_CYGNUS_ASIU_PWM_CLK] = ASIU_GATE_VAL(IPROC_CLK_INVALID_OFFSET, 0),
0254 };
0255
0256 static void __init cygnus_asiu_init(struct device_node *node)
0257 {
0258     iproc_asiu_setup(node, asiu_div, asiu_gate, ARRAY_SIZE(asiu_div));
0259 }
0260 CLK_OF_DECLARE(cygnus_asiu_clk, "brcm,cygnus-asiu-clk", cygnus_asiu_init);
0261
0262 static const struct iproc_pll_ctrl audiopll = {
0263     .flags = IPROC_CLK_PLL_NEEDS_SW_CFG | IPROC_CLK_PLL_HAS_NDIV_FRAC |
0264         IPROC_CLK_PLL_USER_MODE_ON | IPROC_CLK_PLL_RESET_ACTIVE_LOW |
0265         IPROC_CLK_PLL_CALC_PARAM,
0266     .reset = RESET_VAL(0x5c, 0, 1),
0267     .dig_filter = DF_VAL(0x48, 0, 3, 6, 4, 3, 3),
0268     .sw_ctrl = SW_CTRL_VAL(0x4, 0),
0269     .ndiv_int = REG_VAL(0x8, 0, 10),
0270     .ndiv_frac = REG_VAL(0x8, 10, 20),
0271     .pdiv = REG_VAL(0x44, 0, 4),
0272     .vco_ctrl = VCO_CTRL_VAL(0x0c, 0x10),
0273     .status = REG_VAL(0x54, 0, 1),
0274     .macro_mode = REG_VAL(0x0, 0, 3),
0275 };
0276
0277 static const struct iproc_clk_ctrl audiopll_clk[] = {
0278     [BCM_CYGNUS_AUDIOPLL_CH0] = {
0279         .channel = BCM_CYGNUS_AUDIOPLL_CH0,
0280         .flags = IPROC_CLK_AON | IPROC_CLK_MCLK_DIV_BY_2,
0281         .enable = ENABLE_VAL(0x14, 8, 10, 9),
0282         .mdiv = REG_VAL(0x14, 0, 8),
0283     },
0284     [BCM_CYGNUS_AUDIOPLL_CH1] = {
0285         .channel = BCM_CYGNUS_AUDIOPLL_CH1,
0286         .flags = IPROC_CLK_AON,
0287         .enable = ENABLE_VAL(0x18, 8, 10, 9),
0288         .mdiv = REG_VAL(0x18, 0, 8),
0289     },
0290     [BCM_CYGNUS_AUDIOPLL_CH2] = {
0291         .channel = BCM_CYGNUS_AUDIOPLL_CH2,
0292         .flags = IPROC_CLK_AON,
0293         .enable = ENABLE_VAL(0x1c, 8, 10, 9),
0294         .mdiv = REG_VAL(0x1c, 0, 8),
0295     },
0296 };
0297
0298 static void __init cygnus_audiopll_clk_init(struct device_node *node)
0299 {
0300     iproc_pll_clk_setup(node, &audiopll, NULL, 0,
0301                 audiopll_clk,  ARRAY_SIZE(audiopll_clk));
0302 }
0303 CLK_OF_DECLARE(cygnus_audiopll, "brcm,cygnus-audiopll",
0304             cygnus_audiopll_clk_init);