clk/bcm/clk-bcm281xx.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (C) 2013 Broadcom Corporation
0004  * Copyright 2013 Linaro Limited
0005  */
0006
0007 #include "clk-kona.h"
0008 #include "dt-bindings/clock/bcm281xx.h"
0009
0010 #define BCM281XX_CCU_COMMON(_name, _ucase_name) \
0011     KONA_CCU_COMMON(BCM281XX, _name, _ucase_name)
0012
0013 /* Root CCU */
0014
0015 static struct peri_clk_data frac_1m_data = {
0016     .gate       = HW_SW_GATE(0x214, 16, 0, 1),
0017     .trig       = TRIGGER(0x0e04, 0),
0018     .div        = FRAC_DIVIDER(0x0e00, 0, 22, 16),
0019     .clocks     = CLOCKS("ref_crystal"),
0020 };
0021
0022 static struct ccu_data root_ccu_data = {
0023     BCM281XX_CCU_COMMON(root, ROOT),
0024     .kona_clks  = {
0025         [BCM281XX_ROOT_CCU_FRAC_1M] =
0026             KONA_CLK(root, frac_1m, peri),
0027         [BCM281XX_ROOT_CCU_CLOCK_COUNT] = LAST_KONA_CLK,
0028     },
0029 };
0030
0031 /* AON CCU */
0032
0033 static struct peri_clk_data hub_timer_data = {
0034     .gate       = HW_SW_GATE(0x0414, 16, 0, 1),
0035     .clocks     = CLOCKS("bbl_32k",
0036                  "frac_1m",
0037                  "dft_19_5m"),
0038     .sel        = SELECTOR(0x0a10, 0, 2),
0039     .trig       = TRIGGER(0x0a40, 4),
0040 };
0041
0042 static struct peri_clk_data pmu_bsc_data = {
0043     .gate       = HW_SW_GATE(0x0418, 16, 0, 1),
0044     .clocks     = CLOCKS("ref_crystal",
0045                  "pmu_bsc_var",
0046                  "bbl_32k"),
0047     .sel        = SELECTOR(0x0a04, 0, 2),
0048     .div        = DIVIDER(0x0a04, 3, 4),
0049     .trig       = TRIGGER(0x0a40, 0),
0050 };
0051
0052 static struct peri_clk_data pmu_bsc_var_data = {
0053     .clocks     = CLOCKS("var_312m",
0054                  "ref_312m"),
0055     .sel        = SELECTOR(0x0a00, 0, 2),
0056     .div        = DIVIDER(0x0a00, 4, 5),
0057     .trig       = TRIGGER(0x0a40, 2),
0058 };
0059
0060 static struct ccu_data aon_ccu_data = {
0061     BCM281XX_CCU_COMMON(aon, AON),
0062     .kona_clks  = {
0063         [BCM281XX_AON_CCU_HUB_TIMER] =
0064             KONA_CLK(aon, hub_timer, peri),
0065         [BCM281XX_AON_CCU_PMU_BSC] =
0066             KONA_CLK(aon, pmu_bsc, peri),
0067         [BCM281XX_AON_CCU_PMU_BSC_VAR] =
0068             KONA_CLK(aon, pmu_bsc_var, peri),
0069         [BCM281XX_AON_CCU_CLOCK_COUNT] = LAST_KONA_CLK,
0070     },
0071 };
0072
0073 /* Hub CCU */
0074
0075 static struct peri_clk_data tmon_1m_data = {
0076     .gate       = HW_SW_GATE(0x04a4, 18, 2, 3),
0077     .clocks     = CLOCKS("ref_crystal",
0078                  "frac_1m"),
0079     .sel        = SELECTOR(0x0e74, 0, 2),
0080     .trig       = TRIGGER(0x0e84, 1),
0081 };
0082
0083 static struct ccu_data hub_ccu_data = {
0084     BCM281XX_CCU_COMMON(hub, HUB),
0085     .kona_clks  = {
0086         [BCM281XX_HUB_CCU_TMON_1M] =
0087             KONA_CLK(hub, tmon_1m, peri),
0088         [BCM281XX_HUB_CCU_CLOCK_COUNT] = LAST_KONA_CLK,
0089     },
0090 };
0091
0092 /* Master CCU */
0093
0094 static struct peri_clk_data sdio1_data = {
0095     .gate       = HW_SW_GATE(0x0358, 18, 2, 3),
0096     .clocks     = CLOCKS("ref_crystal",
0097                  "var_52m",
0098                  "ref_52m",
0099                  "var_96m",
0100                  "ref_96m"),
0101     .sel        = SELECTOR(0x0a28, 0, 3),
0102     .div        = DIVIDER(0x0a28, 4, 14),
0103     .trig       = TRIGGER(0x0afc, 9),
0104 };
0105
0106 static struct peri_clk_data sdio2_data = {
0107     .gate       = HW_SW_GATE(0x035c, 18, 2, 3),
0108     .clocks     = CLOCKS("ref_crystal",
0109                  "var_52m",
0110                  "ref_52m",
0111                  "var_96m",
0112                  "ref_96m"),
0113     .sel        = SELECTOR(0x0a2c, 0, 3),
0114     .div        = DIVIDER(0x0a2c, 4, 14),
0115     .trig       = TRIGGER(0x0afc, 10),
0116 };
0117
0118 static struct peri_clk_data sdio3_data = {
0119     .gate       = HW_SW_GATE(0x0364, 18, 2, 3),
0120     .clocks     = CLOCKS("ref_crystal",
0121                  "var_52m",
0122                  "ref_52m",
0123                  "var_96m",
0124                  "ref_96m"),
0125     .sel        = SELECTOR(0x0a34, 0, 3),
0126     .div        = DIVIDER(0x0a34, 4, 14),
0127     .trig       = TRIGGER(0x0afc, 12),
0128 };
0129
0130 static struct peri_clk_data sdio4_data = {
0131     .gate       = HW_SW_GATE(0x0360, 18, 2, 3),
0132     .clocks     = CLOCKS("ref_crystal",
0133                  "var_52m",
0134                  "ref_52m",
0135                  "var_96m",
0136                  "ref_96m"),
0137     .sel        = SELECTOR(0x0a30, 0, 3),
0138     .div        = DIVIDER(0x0a30, 4, 14),
0139     .trig       = TRIGGER(0x0afc, 11),
0140 };
0141
0142 static struct peri_clk_data usb_ic_data = {
0143     .gate       = HW_SW_GATE(0x0354, 18, 2, 3),
0144     .clocks     = CLOCKS("ref_crystal",
0145                  "var_96m",
0146                  "ref_96m"),
0147     .div        = FIXED_DIVIDER(2),
0148     .sel        = SELECTOR(0x0a24, 0, 2),
0149     .trig       = TRIGGER(0x0afc, 7),
0150 };
0151
0152 /* also called usbh_48m */
0153 static struct peri_clk_data hsic2_48m_data = {
0154     .gate       = HW_SW_GATE(0x0370, 18, 2, 3),
0155     .clocks     = CLOCKS("ref_crystal",
0156                  "var_96m",
0157                  "ref_96m"),
0158     .sel        = SELECTOR(0x0a38, 0, 2),
0159     .div        = FIXED_DIVIDER(2),
0160     .trig       = TRIGGER(0x0afc, 5),
0161 };
0162
0163 /* also called usbh_12m */
0164 static struct peri_clk_data hsic2_12m_data = {
0165     .gate       = HW_SW_GATE(0x0370, 20, 4, 5),
0166     .div        = DIVIDER(0x0a38, 12, 2),
0167     .clocks     = CLOCKS("ref_crystal",
0168                  "var_96m",
0169                  "ref_96m"),
0170     .pre_div    = FIXED_DIVIDER(2),
0171     .sel        = SELECTOR(0x0a38, 0, 2),
0172     .trig       = TRIGGER(0x0afc, 5),
0173 };
0174
0175 static struct ccu_data master_ccu_data = {
0176     BCM281XX_CCU_COMMON(master, MASTER),
0177     .kona_clks  = {
0178         [BCM281XX_MASTER_CCU_SDIO1] =
0179             KONA_CLK(master, sdio1, peri),
0180         [BCM281XX_MASTER_CCU_SDIO2] =
0181             KONA_CLK(master, sdio2, peri),
0182         [BCM281XX_MASTER_CCU_SDIO3] =
0183             KONA_CLK(master, sdio3, peri),
0184         [BCM281XX_MASTER_CCU_SDIO4] =
0185             KONA_CLK(master, sdio4, peri),
0186         [BCM281XX_MASTER_CCU_USB_IC] =
0187             KONA_CLK(master, usb_ic, peri),
0188         [BCM281XX_MASTER_CCU_HSIC2_48M] =
0189             KONA_CLK(master, hsic2_48m, peri),
0190         [BCM281XX_MASTER_CCU_HSIC2_12M] =
0191             KONA_CLK(master, hsic2_12m, peri),
0192         [BCM281XX_MASTER_CCU_CLOCK_COUNT] = LAST_KONA_CLK,
0193     },
0194 };
0195
0196 /* Slave CCU */
0197
0198 static struct peri_clk_data uartb_data = {
0199     .gate       = HW_SW_GATE(0x0400, 18, 2, 3),
0200     .clocks     = CLOCKS("ref_crystal",
0201                  "var_156m",
0202                  "ref_156m"),
0203     .sel        = SELECTOR(0x0a10, 0, 2),
0204     .div        = FRAC_DIVIDER(0x0a10, 4, 12, 8),
0205     .trig       = TRIGGER(0x0afc, 2),
0206 };
0207
0208 static struct peri_clk_data uartb2_data = {
0209     .gate       = HW_SW_GATE(0x0404, 18, 2, 3),
0210     .clocks     = CLOCKS("ref_crystal",
0211                  "var_156m",
0212                  "ref_156m"),
0213     .sel        = SELECTOR(0x0a14, 0, 2),
0214     .div        = FRAC_DIVIDER(0x0a14, 4, 12, 8),
0215     .trig       = TRIGGER(0x0afc, 3),
0216 };
0217
0218 static struct peri_clk_data uartb3_data = {
0219     .gate       = HW_SW_GATE(0x0408, 18, 2, 3),
0220     .clocks     = CLOCKS("ref_crystal",
0221                  "var_156m",
0222                  "ref_156m"),
0223     .sel        = SELECTOR(0x0a18, 0, 2),
0224     .div        = FRAC_DIVIDER(0x0a18, 4, 12, 8),
0225     .trig       = TRIGGER(0x0afc, 4),
0226 };
0227
0228 static struct peri_clk_data uartb4_data = {
0229     .gate       = HW_SW_GATE(0x0408, 18, 2, 3),
0230     .clocks     = CLOCKS("ref_crystal",
0231                  "var_156m",
0232                  "ref_156m"),
0233     .sel        = SELECTOR(0x0a1c, 0, 2),
0234     .div        = FRAC_DIVIDER(0x0a1c, 4, 12, 8),
0235     .trig       = TRIGGER(0x0afc, 5),
0236 };
0237
0238 static struct peri_clk_data ssp0_data = {
0239     .gate       = HW_SW_GATE(0x0410, 18, 2, 3),
0240     .clocks     = CLOCKS("ref_crystal",
0241                  "var_104m",
0242                  "ref_104m",
0243                  "var_96m",
0244                  "ref_96m"),
0245     .sel        = SELECTOR(0x0a20, 0, 3),
0246     .div        = DIVIDER(0x0a20, 4, 14),
0247     .trig       = TRIGGER(0x0afc, 6),
0248 };
0249
0250 static struct peri_clk_data ssp2_data = {
0251     .gate       = HW_SW_GATE(0x0418, 18, 2, 3),
0252     .clocks     = CLOCKS("ref_crystal",
0253                  "var_104m",
0254                  "ref_104m",
0255                  "var_96m",
0256                  "ref_96m"),
0257     .sel        = SELECTOR(0x0a28, 0, 3),
0258     .div        = DIVIDER(0x0a28, 4, 14),
0259     .trig       = TRIGGER(0x0afc, 8),
0260 };
0261
0262 static struct peri_clk_data bsc1_data = {
0263     .gate       = HW_SW_GATE(0x0458, 18, 2, 3),
0264     .clocks     = CLOCKS("ref_crystal",
0265                  "var_104m",
0266                  "ref_104m",
0267                  "var_13m",
0268                  "ref_13m"),
0269     .sel        = SELECTOR(0x0a64, 0, 3),
0270     .trig       = TRIGGER(0x0afc, 23),
0271 };
0272
0273 static struct peri_clk_data bsc2_data = {
0274     .gate       = HW_SW_GATE(0x045c, 18, 2, 3),
0275     .clocks = CLOCKS("ref_crystal",
0276                  "var_104m",
0277                  "ref_104m",
0278                  "var_13m",
0279                  "ref_13m"),
0280     .sel        = SELECTOR(0x0a68, 0, 3),
0281     .trig       = TRIGGER(0x0afc, 24),
0282 };
0283
0284 static struct peri_clk_data bsc3_data = {
0285     .gate       = HW_SW_GATE(0x0484, 18, 2, 3),
0286     .clocks     = CLOCKS("ref_crystal",
0287                  "var_104m",
0288                  "ref_104m",
0289                  "var_13m",
0290                  "ref_13m"),
0291     .sel        = SELECTOR(0x0a84, 0, 3),
0292     .trig       = TRIGGER(0x0b00, 2),
0293 };
0294
0295 static struct peri_clk_data pwm_data = {
0296     .gate       = HW_SW_GATE(0x0468, 18, 2, 3),
0297     .clocks     = CLOCKS("ref_crystal",
0298                  "var_104m"),
0299     .sel        = SELECTOR(0x0a70, 0, 2),
0300     .div        = DIVIDER(0x0a70, 4, 3),
0301     .trig       = TRIGGER(0x0afc, 15),
0302 };
0303
0304 static struct ccu_data slave_ccu_data = {
0305     BCM281XX_CCU_COMMON(slave, SLAVE),
0306     .kona_clks  = {
0307         [BCM281XX_SLAVE_CCU_UARTB] =
0308             KONA_CLK(slave, uartb, peri),
0309         [BCM281XX_SLAVE_CCU_UARTB2] =
0310             KONA_CLK(slave, uartb2, peri),
0311         [BCM281XX_SLAVE_CCU_UARTB3] =
0312             KONA_CLK(slave, uartb3, peri),
0313         [BCM281XX_SLAVE_CCU_UARTB4] =
0314             KONA_CLK(slave, uartb4, peri),
0315         [BCM281XX_SLAVE_CCU_SSP0] =
0316             KONA_CLK(slave, ssp0, peri),
0317         [BCM281XX_SLAVE_CCU_SSP2] =
0318             KONA_CLK(slave, ssp2, peri),
0319         [BCM281XX_SLAVE_CCU_BSC1] =
0320             KONA_CLK(slave, bsc1, peri),
0321         [BCM281XX_SLAVE_CCU_BSC2] =
0322             KONA_CLK(slave, bsc2, peri),
0323         [BCM281XX_SLAVE_CCU_BSC3] =
0324             KONA_CLK(slave, bsc3, peri),
0325         [BCM281XX_SLAVE_CCU_PWM] =
0326             KONA_CLK(slave, pwm, peri),
0327         [BCM281XX_SLAVE_CCU_CLOCK_COUNT] = LAST_KONA_CLK,
0328     },
0329 };
0330
0331 /* Device tree match table callback functions */
0332
0333 static void __init kona_dt_root_ccu_setup(struct device_node *node)
0334 {
0335     kona_dt_ccu_setup(&root_ccu_data, node);
0336 }
0337
0338 static void __init kona_dt_aon_ccu_setup(struct device_node *node)
0339 {
0340     kona_dt_ccu_setup(&aon_ccu_data, node);
0341 }
0342
0343 static void __init kona_dt_hub_ccu_setup(struct device_node *node)
0344 {
0345     kona_dt_ccu_setup(&hub_ccu_data, node);
0346 }
0347
0348 static void __init kona_dt_master_ccu_setup(struct device_node *node)
0349 {
0350     kona_dt_ccu_setup(&master_ccu_data, node);
0351 }
0352
0353 static void __init kona_dt_slave_ccu_setup(struct device_node *node)
0354 {
0355     kona_dt_ccu_setup(&slave_ccu_data, node);
0356 }
0357
0358 CLK_OF_DECLARE(bcm281xx_root_ccu, BCM281XX_DT_ROOT_CCU_COMPAT,
0359             kona_dt_root_ccu_setup);
0360 CLK_OF_DECLARE(bcm281xx_aon_ccu, BCM281XX_DT_AON_CCU_COMPAT,
0361             kona_dt_aon_ccu_setup);
0362 CLK_OF_DECLARE(bcm281xx_hub_ccu, BCM281XX_DT_HUB_CCU_COMPAT,
0363             kona_dt_hub_ccu_setup);
0364 CLK_OF_DECLARE(bcm281xx_master_ccu, BCM281XX_DT_MASTER_CCU_COMPAT,
0365             kona_dt_master_ccu_setup);
0366 CLK_OF_DECLARE(bcm281xx_slave_ccu, BCM281XX_DT_SLAVE_CCU_COMPAT,
0367             kona_dt_slave_ccu_setup);