clk/bcm/clk-bcm21664.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (C) 2014 Broadcom Corporation
0004  * Copyright 2014 Linaro Limited
0005  */
0006
0007 #include "clk-kona.h"
0008 #include "dt-bindings/clock/bcm21664.h"
0009
0010 #define BCM21664_CCU_COMMON(_name, _capname) \
0011     KONA_CCU_COMMON(BCM21664, _name, _capname)
0012
0013 /* Root CCU */
0014
0015 static struct peri_clk_data frac_1m_data = {
0016     .gate       = HW_SW_GATE(0x214, 16, 0, 1),
0017     .clocks     = CLOCKS("ref_crystal"),
0018 };
0019
0020 static struct ccu_data root_ccu_data = {
0021     BCM21664_CCU_COMMON(root, ROOT),
0022     /* no policy control */
0023     .kona_clks  = {
0024         [BCM21664_ROOT_CCU_FRAC_1M] =
0025             KONA_CLK(root, frac_1m, peri),
0026         [BCM21664_ROOT_CCU_CLOCK_COUNT] = LAST_KONA_CLK,
0027     },
0028 };
0029
0030 /* AON CCU */
0031
0032 static struct peri_clk_data hub_timer_data = {
0033     .gate       = HW_SW_GATE(0x0414, 16, 0, 1),
0034     .hyst       = HYST(0x0414, 8, 9),
0035     .clocks     = CLOCKS("bbl_32k",
0036                  "frac_1m",
0037                  "dft_19_5m"),
0038     .sel        = SELECTOR(0x0a10, 0, 2),
0039     .trig       = TRIGGER(0x0a40, 4),
0040 };
0041
0042 static struct ccu_data aon_ccu_data = {
0043     BCM21664_CCU_COMMON(aon, AON),
0044     .policy     = {
0045         .enable     = CCU_LVM_EN(0x0034, 0),
0046         .control    = CCU_POLICY_CTL(0x000c, 0, 1, 2),
0047     },
0048     .kona_clks  = {
0049         [BCM21664_AON_CCU_HUB_TIMER] =
0050             KONA_CLK(aon, hub_timer, peri),
0051         [BCM21664_AON_CCU_CLOCK_COUNT] = LAST_KONA_CLK,
0052     },
0053 };
0054
0055 /* Master CCU */
0056
0057 static struct peri_clk_data sdio1_data = {
0058     .gate       = HW_SW_GATE(0x0358, 18, 2, 3),
0059     .clocks     = CLOCKS("ref_crystal",
0060                  "var_52m",
0061                  "ref_52m",
0062                  "var_96m",
0063                  "ref_96m"),
0064     .sel        = SELECTOR(0x0a28, 0, 3),
0065     .div        = DIVIDER(0x0a28, 4, 14),
0066     .trig       = TRIGGER(0x0afc, 9),
0067 };
0068
0069 static struct peri_clk_data sdio2_data = {
0070     .gate       = HW_SW_GATE(0x035c, 18, 2, 3),
0071     .clocks     = CLOCKS("ref_crystal",
0072                  "var_52m",
0073                  "ref_52m",
0074                  "var_96m",
0075                  "ref_96m"),
0076     .sel        = SELECTOR(0x0a2c, 0, 3),
0077     .div        = DIVIDER(0x0a2c, 4, 14),
0078     .trig       = TRIGGER(0x0afc, 10),
0079 };
0080
0081 static struct peri_clk_data sdio3_data = {
0082     .gate       = HW_SW_GATE(0x0364, 18, 2, 3),
0083     .clocks     = CLOCKS("ref_crystal",
0084                  "var_52m",
0085                  "ref_52m",
0086                  "var_96m",
0087                  "ref_96m"),
0088     .sel        = SELECTOR(0x0a34, 0, 3),
0089     .div        = DIVIDER(0x0a34, 4, 14),
0090     .trig       = TRIGGER(0x0afc, 12),
0091 };
0092
0093 static struct peri_clk_data sdio4_data = {
0094     .gate       = HW_SW_GATE(0x0360, 18, 2, 3),
0095     .clocks     = CLOCKS("ref_crystal",
0096                  "var_52m",
0097                  "ref_52m",
0098                  "var_96m",
0099                  "ref_96m"),
0100     .sel        = SELECTOR(0x0a30, 0, 3),
0101     .div        = DIVIDER(0x0a30, 4, 14),
0102     .trig       = TRIGGER(0x0afc, 11),
0103 };
0104
0105 static struct peri_clk_data sdio1_sleep_data = {
0106     .clocks     = CLOCKS("ref_32k"),    /* Verify */
0107     .gate       = HW_SW_GATE(0x0358, 18, 2, 3),
0108 };
0109
0110 static struct peri_clk_data sdio2_sleep_data = {
0111     .clocks     = CLOCKS("ref_32k"),    /* Verify */
0112     .gate       = HW_SW_GATE(0x035c, 18, 2, 3),
0113 };
0114
0115 static struct peri_clk_data sdio3_sleep_data = {
0116     .clocks     = CLOCKS("ref_32k"),    /* Verify */
0117     .gate       = HW_SW_GATE(0x0364, 18, 2, 3),
0118 };
0119
0120 static struct peri_clk_data sdio4_sleep_data = {
0121     .clocks     = CLOCKS("ref_32k"),    /* Verify */
0122     .gate       = HW_SW_GATE(0x0360, 18, 2, 3),
0123 };
0124
0125 static struct ccu_data master_ccu_data = {
0126     BCM21664_CCU_COMMON(master, MASTER),
0127     .policy     = {
0128         .enable     = CCU_LVM_EN(0x0034, 0),
0129         .control    = CCU_POLICY_CTL(0x000c, 0, 1, 2),
0130     },
0131     .kona_clks  = {
0132         [BCM21664_MASTER_CCU_SDIO1] =
0133             KONA_CLK(master, sdio1, peri),
0134         [BCM21664_MASTER_CCU_SDIO2] =
0135             KONA_CLK(master, sdio2, peri),
0136         [BCM21664_MASTER_CCU_SDIO3] =
0137             KONA_CLK(master, sdio3, peri),
0138         [BCM21664_MASTER_CCU_SDIO4] =
0139             KONA_CLK(master, sdio4, peri),
0140         [BCM21664_MASTER_CCU_SDIO1_SLEEP] =
0141             KONA_CLK(master, sdio1_sleep, peri),
0142         [BCM21664_MASTER_CCU_SDIO2_SLEEP] =
0143             KONA_CLK(master, sdio2_sleep, peri),
0144         [BCM21664_MASTER_CCU_SDIO3_SLEEP] =
0145             KONA_CLK(master, sdio3_sleep, peri),
0146         [BCM21664_MASTER_CCU_SDIO4_SLEEP] =
0147             KONA_CLK(master, sdio4_sleep, peri),
0148         [BCM21664_MASTER_CCU_CLOCK_COUNT] = LAST_KONA_CLK,
0149     },
0150 };
0151
0152 /* Slave CCU */
0153
0154 static struct peri_clk_data uartb_data = {
0155     .gate       = HW_SW_GATE(0x0400, 18, 2, 3),
0156     .clocks     = CLOCKS("ref_crystal",
0157                  "var_156m",
0158                  "ref_156m"),
0159     .sel        = SELECTOR(0x0a10, 0, 2),
0160     .div        = FRAC_DIVIDER(0x0a10, 4, 12, 8),
0161     .trig       = TRIGGER(0x0afc, 2),
0162 };
0163
0164 static struct peri_clk_data uartb2_data = {
0165     .gate       = HW_SW_GATE(0x0404, 18, 2, 3),
0166     .clocks     = CLOCKS("ref_crystal",
0167                  "var_156m",
0168                  "ref_156m"),
0169     .sel        = SELECTOR(0x0a14, 0, 2),
0170     .div        = FRAC_DIVIDER(0x0a14, 4, 12, 8),
0171     .trig       = TRIGGER(0x0afc, 3),
0172 };
0173
0174 static struct peri_clk_data uartb3_data = {
0175     .gate       = HW_SW_GATE(0x0408, 18, 2, 3),
0176     .clocks     = CLOCKS("ref_crystal",
0177                  "var_156m",
0178                  "ref_156m"),
0179     .sel        = SELECTOR(0x0a18, 0, 2),
0180     .div        = FRAC_DIVIDER(0x0a18, 4, 12, 8),
0181     .trig       = TRIGGER(0x0afc, 4),
0182 };
0183
0184 static struct peri_clk_data bsc1_data = {
0185     .gate       = HW_SW_GATE(0x0458, 18, 2, 3),
0186     .clocks     = CLOCKS("ref_crystal",
0187                  "var_104m",
0188                  "ref_104m",
0189                  "var_13m",
0190                  "ref_13m"),
0191     .sel        = SELECTOR(0x0a64, 0, 3),
0192     .trig       = TRIGGER(0x0afc, 23),
0193 };
0194
0195 static struct peri_clk_data bsc2_data = {
0196     .gate       = HW_SW_GATE(0x045c, 18, 2, 3),
0197     .clocks     = CLOCKS("ref_crystal",
0198                  "var_104m",
0199                  "ref_104m",
0200                  "var_13m",
0201                  "ref_13m"),
0202     .sel        = SELECTOR(0x0a68, 0, 3),
0203     .trig       = TRIGGER(0x0afc, 24),
0204 };
0205
0206 static struct peri_clk_data bsc3_data = {
0207     .gate       = HW_SW_GATE(0x0470, 18, 2, 3),
0208     .clocks     = CLOCKS("ref_crystal",
0209                  "var_104m",
0210                  "ref_104m",
0211                  "var_13m",
0212                  "ref_13m"),
0213     .sel        = SELECTOR(0x0a7c, 0, 3),
0214     .trig       = TRIGGER(0x0afc, 18),
0215 };
0216
0217 static struct peri_clk_data bsc4_data = {
0218     .gate       = HW_SW_GATE(0x0474, 18, 2, 3),
0219     .clocks     = CLOCKS("ref_crystal",
0220                  "var_104m",
0221                  "ref_104m",
0222                  "var_13m",
0223                  "ref_13m"),
0224     .sel        = SELECTOR(0x0a80, 0, 3),
0225     .trig       = TRIGGER(0x0afc, 19),
0226 };
0227
0228 static struct ccu_data slave_ccu_data = {
0229     BCM21664_CCU_COMMON(slave, SLAVE),
0230        .policy      = {
0231         .enable     = CCU_LVM_EN(0x0034, 0),
0232         .control    = CCU_POLICY_CTL(0x000c, 0, 1, 2),
0233     },
0234     .kona_clks  = {
0235         [BCM21664_SLAVE_CCU_UARTB] =
0236             KONA_CLK(slave, uartb, peri),
0237         [BCM21664_SLAVE_CCU_UARTB2] =
0238             KONA_CLK(slave, uartb2, peri),
0239         [BCM21664_SLAVE_CCU_UARTB3] =
0240             KONA_CLK(slave, uartb3, peri),
0241         [BCM21664_SLAVE_CCU_BSC1] =
0242             KONA_CLK(slave, bsc1, peri),
0243         [BCM21664_SLAVE_CCU_BSC2] =
0244             KONA_CLK(slave, bsc2, peri),
0245         [BCM21664_SLAVE_CCU_BSC3] =
0246             KONA_CLK(slave, bsc3, peri),
0247         [BCM21664_SLAVE_CCU_BSC4] =
0248             KONA_CLK(slave, bsc4, peri),
0249         [BCM21664_SLAVE_CCU_CLOCK_COUNT] = LAST_KONA_CLK,
0250     },
0251 };
0252
0253 /* Device tree match table callback functions */
0254
0255 static void __init kona_dt_root_ccu_setup(struct device_node *node)
0256 {
0257     kona_dt_ccu_setup(&root_ccu_data, node);
0258 }
0259
0260 static void __init kona_dt_aon_ccu_setup(struct device_node *node)
0261 {
0262     kona_dt_ccu_setup(&aon_ccu_data, node);
0263 }
0264
0265 static void __init kona_dt_master_ccu_setup(struct device_node *node)
0266 {
0267     kona_dt_ccu_setup(&master_ccu_data, node);
0268 }
0269
0270 static void __init kona_dt_slave_ccu_setup(struct device_node *node)
0271 {
0272     kona_dt_ccu_setup(&slave_ccu_data, node);
0273 }
0274
0275 CLK_OF_DECLARE(bcm21664_root_ccu, BCM21664_DT_ROOT_CCU_COMPAT,
0276             kona_dt_root_ccu_setup);
0277 CLK_OF_DECLARE(bcm21664_aon_ccu, BCM21664_DT_AON_CCU_COMPAT,
0278             kona_dt_aon_ccu_setup);
0279 CLK_OF_DECLARE(bcm21664_master_ccu, BCM21664_DT_MASTER_CCU_COMPAT,
0280             kona_dt_master_ccu_setup);
0281 CLK_OF_DECLARE(bcm21664_slave_ccu, BCM21664_DT_SLAVE_CCU_COMPAT,
0282             kona_dt_slave_ccu_setup);