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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
0004  *
0005  * Authors:
0006  *   Serge Semin <Sergey.Semin@baikalelectronics.ru>
0007  *   Dmitry Dunaev <dmitry.dunaev@baikalelectronics.ru>
0008  *
0009  * Baikal-T1 CCU Dividers clock driver
0010  */
0011 
0012 #define pr_fmt(fmt) "bt1-ccu-div: " fmt
0013 
0014 #include <linux/kernel.h>
0015 #include <linux/printk.h>
0016 #include <linux/slab.h>
0017 #include <linux/clk-provider.h>
0018 #include <linux/reset-controller.h>
0019 #include <linux/mfd/syscon.h>
0020 #include <linux/of.h>
0021 #include <linux/of_address.h>
0022 #include <linux/of_platform.h>
0023 #include <linux/ioport.h>
0024 #include <linux/regmap.h>
0025 
0026 #include <dt-bindings/clock/bt1-ccu.h>
0027 #include <dt-bindings/reset/bt1-ccu.h>
0028 
0029 #include "ccu-div.h"
0030 
0031 #define CCU_AXI_MAIN_BASE       0x030
0032 #define CCU_AXI_DDR_BASE        0x034
0033 #define CCU_AXI_SATA_BASE       0x038
0034 #define CCU_AXI_GMAC0_BASE      0x03C
0035 #define CCU_AXI_GMAC1_BASE      0x040
0036 #define CCU_AXI_XGMAC_BASE      0x044
0037 #define CCU_AXI_PCIE_M_BASE     0x048
0038 #define CCU_AXI_PCIE_S_BASE     0x04C
0039 #define CCU_AXI_USB_BASE        0x050
0040 #define CCU_AXI_HWA_BASE        0x054
0041 #define CCU_AXI_SRAM_BASE       0x058
0042 
0043 #define CCU_SYS_SATA_REF_BASE       0x060
0044 #define CCU_SYS_APB_BASE        0x064
0045 #define CCU_SYS_GMAC0_BASE      0x068
0046 #define CCU_SYS_GMAC1_BASE      0x06C
0047 #define CCU_SYS_XGMAC_BASE      0x070
0048 #define CCU_SYS_USB_BASE        0x074
0049 #define CCU_SYS_PVT_BASE        0x078
0050 #define CCU_SYS_HWA_BASE        0x07C
0051 #define CCU_SYS_UART_BASE       0x084
0052 #define CCU_SYS_TIMER0_BASE     0x088
0053 #define CCU_SYS_TIMER1_BASE     0x08C
0054 #define CCU_SYS_TIMER2_BASE     0x090
0055 #define CCU_SYS_WDT_BASE        0x150
0056 
0057 #define CCU_DIV_VAR_INFO(_id, _name, _pname, _base, _width, _flags, _features) \
0058     {                               \
0059         .id = _id,                      \
0060         .name = _name,                      \
0061         .parent_name = _pname,                  \
0062         .base = _base,                      \
0063         .type = CCU_DIV_VAR,                    \
0064         .width = _width,                    \
0065         .flags = _flags,                    \
0066         .features = _features                   \
0067     }
0068 
0069 #define CCU_DIV_GATE_INFO(_id, _name, _pname, _base, _divider)  \
0070     {                           \
0071         .id = _id,                  \
0072         .name = _name,                  \
0073         .parent_name = _pname,              \
0074         .base = _base,                  \
0075         .type = CCU_DIV_GATE,               \
0076         .divider = _divider             \
0077     }
0078 
0079 #define CCU_DIV_FIXED_INFO(_id, _name, _pname, _divider)    \
0080     {                           \
0081         .id = _id,                  \
0082         .name = _name,                  \
0083         .parent_name = _pname,              \
0084         .type = CCU_DIV_FIXED,              \
0085         .divider = _divider             \
0086     }
0087 
0088 #define CCU_DIV_RST_MAP(_rst_id, _clk_id)   \
0089     {                   \
0090         .rst_id = _rst_id,      \
0091         .clk_id = _clk_id       \
0092     }
0093 
0094 struct ccu_div_info {
0095     unsigned int id;
0096     const char *name;
0097     const char *parent_name;
0098     unsigned int base;
0099     enum ccu_div_type type;
0100     union {
0101         unsigned int width;
0102         unsigned int divider;
0103     };
0104     unsigned long flags;
0105     unsigned long features;
0106 };
0107 
0108 struct ccu_div_rst_map {
0109     unsigned int rst_id;
0110     unsigned int clk_id;
0111 };
0112 
0113 struct ccu_div_data {
0114     struct device_node *np;
0115     struct regmap *sys_regs;
0116 
0117     unsigned int divs_num;
0118     const struct ccu_div_info *divs_info;
0119     struct ccu_div **divs;
0120 
0121     unsigned int rst_num;
0122     const struct ccu_div_rst_map *rst_map;
0123     struct reset_controller_dev rcdev;
0124 };
0125 #define to_ccu_div_data(_rcdev) container_of(_rcdev, struct ccu_div_data, rcdev)
0126 
0127 /*
0128  * AXI Main Interconnect (axi_main_clk) and DDR AXI-bus (axi_ddr_clk) clocks
0129  * must be left enabled in any case, since former one is responsible for
0130  * clocking a bus between CPU cores and the rest of the SoC components, while
0131  * the later is clocking the AXI-bus between DDR controller and the Main
0132  * Interconnect. So should any of these clocks get to be disabled, the system
0133  * will literally stop working. That's why we marked them as critical.
0134  */
0135 static const struct ccu_div_info axi_info[] = {
0136     CCU_DIV_VAR_INFO(CCU_AXI_MAIN_CLK, "axi_main_clk", "pcie_clk",
0137              CCU_AXI_MAIN_BASE, 4,
0138              CLK_IS_CRITICAL, CCU_DIV_RESET_DOMAIN),
0139     CCU_DIV_VAR_INFO(CCU_AXI_DDR_CLK, "axi_ddr_clk", "sata_clk",
0140              CCU_AXI_DDR_BASE, 4,
0141              CLK_IS_CRITICAL | CLK_SET_RATE_GATE,
0142              CCU_DIV_RESET_DOMAIN),
0143     CCU_DIV_VAR_INFO(CCU_AXI_SATA_CLK, "axi_sata_clk", "sata_clk",
0144              CCU_AXI_SATA_BASE, 4,
0145              CLK_SET_RATE_GATE, CCU_DIV_RESET_DOMAIN),
0146     CCU_DIV_VAR_INFO(CCU_AXI_GMAC0_CLK, "axi_gmac0_clk", "eth_clk",
0147              CCU_AXI_GMAC0_BASE, 4,
0148              CLK_SET_RATE_GATE, CCU_DIV_RESET_DOMAIN),
0149     CCU_DIV_VAR_INFO(CCU_AXI_GMAC1_CLK, "axi_gmac1_clk", "eth_clk",
0150              CCU_AXI_GMAC1_BASE, 4,
0151              CLK_SET_RATE_GATE, CCU_DIV_RESET_DOMAIN),
0152     CCU_DIV_VAR_INFO(CCU_AXI_XGMAC_CLK, "axi_xgmac_clk", "eth_clk",
0153              CCU_AXI_XGMAC_BASE, 4,
0154              CLK_SET_RATE_GATE, CCU_DIV_RESET_DOMAIN),
0155     CCU_DIV_VAR_INFO(CCU_AXI_PCIE_M_CLK, "axi_pcie_m_clk", "pcie_clk",
0156              CCU_AXI_PCIE_M_BASE, 4,
0157              CLK_SET_RATE_GATE, CCU_DIV_RESET_DOMAIN),
0158     CCU_DIV_VAR_INFO(CCU_AXI_PCIE_S_CLK, "axi_pcie_s_clk", "pcie_clk",
0159              CCU_AXI_PCIE_S_BASE, 4,
0160              CLK_SET_RATE_GATE, CCU_DIV_RESET_DOMAIN),
0161     CCU_DIV_VAR_INFO(CCU_AXI_USB_CLK, "axi_usb_clk", "sata_clk",
0162              CCU_AXI_USB_BASE, 4,
0163              CLK_SET_RATE_GATE, CCU_DIV_RESET_DOMAIN),
0164     CCU_DIV_VAR_INFO(CCU_AXI_HWA_CLK, "axi_hwa_clk", "sata_clk",
0165              CCU_AXI_HWA_BASE, 4,
0166              CLK_SET_RATE_GATE, CCU_DIV_RESET_DOMAIN),
0167     CCU_DIV_VAR_INFO(CCU_AXI_SRAM_CLK, "axi_sram_clk", "eth_clk",
0168              CCU_AXI_SRAM_BASE, 4,
0169              CLK_SET_RATE_GATE, CCU_DIV_RESET_DOMAIN)
0170 };
0171 
0172 static const struct ccu_div_rst_map axi_rst_map[] = {
0173     CCU_DIV_RST_MAP(CCU_AXI_MAIN_RST, CCU_AXI_MAIN_CLK),
0174     CCU_DIV_RST_MAP(CCU_AXI_DDR_RST, CCU_AXI_DDR_CLK),
0175     CCU_DIV_RST_MAP(CCU_AXI_SATA_RST, CCU_AXI_SATA_CLK),
0176     CCU_DIV_RST_MAP(CCU_AXI_GMAC0_RST, CCU_AXI_GMAC0_CLK),
0177     CCU_DIV_RST_MAP(CCU_AXI_GMAC1_RST, CCU_AXI_GMAC1_CLK),
0178     CCU_DIV_RST_MAP(CCU_AXI_XGMAC_RST, CCU_AXI_XGMAC_CLK),
0179     CCU_DIV_RST_MAP(CCU_AXI_PCIE_M_RST, CCU_AXI_PCIE_M_CLK),
0180     CCU_DIV_RST_MAP(CCU_AXI_PCIE_S_RST, CCU_AXI_PCIE_S_CLK),
0181     CCU_DIV_RST_MAP(CCU_AXI_USB_RST, CCU_AXI_USB_CLK),
0182     CCU_DIV_RST_MAP(CCU_AXI_HWA_RST, CCU_AXI_HWA_CLK),
0183     CCU_DIV_RST_MAP(CCU_AXI_SRAM_RST, CCU_AXI_SRAM_CLK)
0184 };
0185 
0186 /*
0187  * APB-bus clock is marked as critical since it's a main communication bus
0188  * for the SoC devices registers IO-operations.
0189  */
0190 static const struct ccu_div_info sys_info[] = {
0191     CCU_DIV_VAR_INFO(CCU_SYS_SATA_REF_CLK, "sys_sata_ref_clk",
0192              "sata_clk", CCU_SYS_SATA_REF_BASE, 4,
0193              CLK_SET_RATE_GATE,
0194              CCU_DIV_SKIP_ONE | CCU_DIV_LOCK_SHIFTED |
0195              CCU_DIV_RESET_DOMAIN),
0196     CCU_DIV_VAR_INFO(CCU_SYS_APB_CLK, "sys_apb_clk",
0197              "pcie_clk", CCU_SYS_APB_BASE, 5,
0198              CLK_IS_CRITICAL, CCU_DIV_RESET_DOMAIN),
0199     CCU_DIV_GATE_INFO(CCU_SYS_GMAC0_TX_CLK, "sys_gmac0_tx_clk",
0200               "eth_clk", CCU_SYS_GMAC0_BASE, 5),
0201     CCU_DIV_FIXED_INFO(CCU_SYS_GMAC0_PTP_CLK, "sys_gmac0_ptp_clk",
0202                "eth_clk", 10),
0203     CCU_DIV_GATE_INFO(CCU_SYS_GMAC1_TX_CLK, "sys_gmac1_tx_clk",
0204               "eth_clk", CCU_SYS_GMAC1_BASE, 5),
0205     CCU_DIV_FIXED_INFO(CCU_SYS_GMAC1_PTP_CLK, "sys_gmac1_ptp_clk",
0206                "eth_clk", 10),
0207     CCU_DIV_GATE_INFO(CCU_SYS_XGMAC_REF_CLK, "sys_xgmac_ref_clk",
0208               "eth_clk", CCU_SYS_XGMAC_BASE, 8),
0209     CCU_DIV_FIXED_INFO(CCU_SYS_XGMAC_PTP_CLK, "sys_xgmac_ptp_clk",
0210                "eth_clk", 10),
0211     CCU_DIV_GATE_INFO(CCU_SYS_USB_CLK, "sys_usb_clk",
0212               "eth_clk", CCU_SYS_USB_BASE, 10),
0213     CCU_DIV_VAR_INFO(CCU_SYS_PVT_CLK, "sys_pvt_clk",
0214              "ref_clk", CCU_SYS_PVT_BASE, 5,
0215              CLK_SET_RATE_GATE, 0),
0216     CCU_DIV_VAR_INFO(CCU_SYS_HWA_CLK, "sys_hwa_clk",
0217              "sata_clk", CCU_SYS_HWA_BASE, 4,
0218              CLK_SET_RATE_GATE, 0),
0219     CCU_DIV_VAR_INFO(CCU_SYS_UART_CLK, "sys_uart_clk",
0220              "eth_clk", CCU_SYS_UART_BASE, 17,
0221              CLK_SET_RATE_GATE, 0),
0222     CCU_DIV_FIXED_INFO(CCU_SYS_I2C1_CLK, "sys_i2c1_clk",
0223                "eth_clk", 10),
0224     CCU_DIV_FIXED_INFO(CCU_SYS_I2C2_CLK, "sys_i2c2_clk",
0225                "eth_clk", 10),
0226     CCU_DIV_FIXED_INFO(CCU_SYS_GPIO_CLK, "sys_gpio_clk",
0227                "ref_clk", 25),
0228     CCU_DIV_VAR_INFO(CCU_SYS_TIMER0_CLK, "sys_timer0_clk",
0229              "ref_clk", CCU_SYS_TIMER0_BASE, 17,
0230              CLK_SET_RATE_GATE, 0),
0231     CCU_DIV_VAR_INFO(CCU_SYS_TIMER1_CLK, "sys_timer1_clk",
0232              "ref_clk", CCU_SYS_TIMER1_BASE, 17,
0233              CLK_SET_RATE_GATE, 0),
0234     CCU_DIV_VAR_INFO(CCU_SYS_TIMER2_CLK, "sys_timer2_clk",
0235              "ref_clk", CCU_SYS_TIMER2_BASE, 17,
0236              CLK_SET_RATE_GATE, 0),
0237     CCU_DIV_VAR_INFO(CCU_SYS_WDT_CLK, "sys_wdt_clk",
0238              "eth_clk", CCU_SYS_WDT_BASE, 17,
0239              CLK_SET_RATE_GATE, CCU_DIV_SKIP_ONE_TO_THREE)
0240 };
0241 
0242 static const struct ccu_div_rst_map sys_rst_map[] = {
0243     CCU_DIV_RST_MAP(CCU_SYS_SATA_REF_RST, CCU_SYS_SATA_REF_CLK),
0244     CCU_DIV_RST_MAP(CCU_SYS_APB_RST, CCU_SYS_APB_CLK),
0245 };
0246 
0247 static struct ccu_div *ccu_div_find_desc(struct ccu_div_data *data,
0248                      unsigned int clk_id)
0249 {
0250     struct ccu_div *div;
0251     int idx;
0252 
0253     for (idx = 0; idx < data->divs_num; ++idx) {
0254         div = data->divs[idx];
0255         if (div && div->id == clk_id)
0256             return div;
0257     }
0258 
0259     return ERR_PTR(-EINVAL);
0260 }
0261 
0262 static int ccu_div_reset(struct reset_controller_dev *rcdev,
0263              unsigned long rst_id)
0264 {
0265     struct ccu_div_data *data = to_ccu_div_data(rcdev);
0266     const struct ccu_div_rst_map *map;
0267     struct ccu_div *div;
0268     int idx, ret;
0269 
0270     for (idx = 0, map = data->rst_map; idx < data->rst_num; ++idx, ++map) {
0271         if (map->rst_id == rst_id)
0272             break;
0273     }
0274     if (idx == data->rst_num) {
0275         pr_err("Invalid reset ID %lu specified\n", rst_id);
0276         return -EINVAL;
0277     }
0278 
0279     div = ccu_div_find_desc(data, map->clk_id);
0280     if (IS_ERR(div)) {
0281         pr_err("Invalid clock ID %d in mapping\n", map->clk_id);
0282         return PTR_ERR(div);
0283     }
0284 
0285     ret = ccu_div_reset_domain(div);
0286     if (ret) {
0287         pr_err("Reset isn't supported by divider %s\n",
0288             clk_hw_get_name(ccu_div_get_clk_hw(div)));
0289     }
0290 
0291     return ret;
0292 }
0293 
0294 static const struct reset_control_ops ccu_div_rst_ops = {
0295     .reset = ccu_div_reset,
0296 };
0297 
0298 static struct ccu_div_data *ccu_div_create_data(struct device_node *np)
0299 {
0300     struct ccu_div_data *data;
0301     int ret;
0302 
0303     data = kzalloc(sizeof(*data), GFP_KERNEL);
0304     if (!data)
0305         return ERR_PTR(-ENOMEM);
0306 
0307     data->np = np;
0308     if (of_device_is_compatible(np, "baikal,bt1-ccu-axi")) {
0309         data->divs_num = ARRAY_SIZE(axi_info);
0310         data->divs_info = axi_info;
0311         data->rst_num = ARRAY_SIZE(axi_rst_map);
0312         data->rst_map = axi_rst_map;
0313     } else if (of_device_is_compatible(np, "baikal,bt1-ccu-sys")) {
0314         data->divs_num = ARRAY_SIZE(sys_info);
0315         data->divs_info = sys_info;
0316         data->rst_num = ARRAY_SIZE(sys_rst_map);
0317         data->rst_map = sys_rst_map;
0318     } else {
0319         pr_err("Incompatible DT node '%s' specified\n",
0320             of_node_full_name(np));
0321         ret = -EINVAL;
0322         goto err_kfree_data;
0323     }
0324 
0325     data->divs = kcalloc(data->divs_num, sizeof(*data->divs), GFP_KERNEL);
0326     if (!data->divs) {
0327         ret = -ENOMEM;
0328         goto err_kfree_data;
0329     }
0330 
0331     return data;
0332 
0333 err_kfree_data:
0334     kfree(data);
0335 
0336     return ERR_PTR(ret);
0337 }
0338 
0339 static void ccu_div_free_data(struct ccu_div_data *data)
0340 {
0341     kfree(data->divs);
0342 
0343     kfree(data);
0344 }
0345 
0346 static int ccu_div_find_sys_regs(struct ccu_div_data *data)
0347 {
0348     data->sys_regs = syscon_node_to_regmap(data->np->parent);
0349     if (IS_ERR(data->sys_regs)) {
0350         pr_err("Failed to find syscon regs for '%s'\n",
0351             of_node_full_name(data->np));
0352         return PTR_ERR(data->sys_regs);
0353     }
0354 
0355     return 0;
0356 }
0357 
0358 static struct clk_hw *ccu_div_of_clk_hw_get(struct of_phandle_args *clkspec,
0359                         void *priv)
0360 {
0361     struct ccu_div_data *data = priv;
0362     struct ccu_div *div;
0363     unsigned int clk_id;
0364 
0365     clk_id = clkspec->args[0];
0366     div = ccu_div_find_desc(data, clk_id);
0367     if (IS_ERR(div)) {
0368         pr_info("Invalid clock ID %d specified\n", clk_id);
0369         return ERR_CAST(div);
0370     }
0371 
0372     return ccu_div_get_clk_hw(div);
0373 }
0374 
0375 static int ccu_div_clk_register(struct ccu_div_data *data)
0376 {
0377     int idx, ret;
0378 
0379     for (idx = 0; idx < data->divs_num; ++idx) {
0380         const struct ccu_div_info *info = &data->divs_info[idx];
0381         struct ccu_div_init_data init = {0};
0382 
0383         init.id = info->id;
0384         init.name = info->name;
0385         init.parent_name = info->parent_name;
0386         init.np = data->np;
0387         init.type = info->type;
0388         init.flags = info->flags;
0389         init.features = info->features;
0390 
0391         if (init.type == CCU_DIV_VAR) {
0392             init.base = info->base;
0393             init.sys_regs = data->sys_regs;
0394             init.width = info->width;
0395         } else if (init.type == CCU_DIV_GATE) {
0396             init.base = info->base;
0397             init.sys_regs = data->sys_regs;
0398             init.divider = info->divider;
0399         } else {
0400             init.divider = info->divider;
0401         }
0402 
0403         data->divs[idx] = ccu_div_hw_register(&init);
0404         if (IS_ERR(data->divs[idx])) {
0405             ret = PTR_ERR(data->divs[idx]);
0406             pr_err("Couldn't register divider '%s' hw\n",
0407                 init.name);
0408             goto err_hw_unregister;
0409         }
0410     }
0411 
0412     ret = of_clk_add_hw_provider(data->np, ccu_div_of_clk_hw_get, data);
0413     if (ret) {
0414         pr_err("Couldn't register dividers '%s' clock provider\n",
0415             of_node_full_name(data->np));
0416         goto err_hw_unregister;
0417     }
0418 
0419     return 0;
0420 
0421 err_hw_unregister:
0422     for (--idx; idx >= 0; --idx)
0423         ccu_div_hw_unregister(data->divs[idx]);
0424 
0425     return ret;
0426 }
0427 
0428 static void ccu_div_clk_unregister(struct ccu_div_data *data)
0429 {
0430     int idx;
0431 
0432     of_clk_del_provider(data->np);
0433 
0434     for (idx = 0; idx < data->divs_num; ++idx)
0435         ccu_div_hw_unregister(data->divs[idx]);
0436 }
0437 
0438 static int ccu_div_rst_register(struct ccu_div_data *data)
0439 {
0440     int ret;
0441 
0442     data->rcdev.ops = &ccu_div_rst_ops;
0443     data->rcdev.of_node = data->np;
0444     data->rcdev.nr_resets = data->rst_num;
0445 
0446     ret = reset_controller_register(&data->rcdev);
0447     if (ret)
0448         pr_err("Couldn't register divider '%s' reset controller\n",
0449             of_node_full_name(data->np));
0450 
0451     return ret;
0452 }
0453 
0454 static void ccu_div_init(struct device_node *np)
0455 {
0456     struct ccu_div_data *data;
0457     int ret;
0458 
0459     data = ccu_div_create_data(np);
0460     if (IS_ERR(data))
0461         return;
0462 
0463     ret = ccu_div_find_sys_regs(data);
0464     if (ret)
0465         goto err_free_data;
0466 
0467     ret = ccu_div_clk_register(data);
0468     if (ret)
0469         goto err_free_data;
0470 
0471     ret = ccu_div_rst_register(data);
0472     if (ret)
0473         goto err_clk_unregister;
0474 
0475     return;
0476 
0477 err_clk_unregister:
0478     ccu_div_clk_unregister(data);
0479 
0480 err_free_data:
0481     ccu_div_free_data(data);
0482 }
0483 
0484 CLK_OF_DECLARE(ccu_axi, "baikal,bt1-ccu-axi", ccu_div_init);
0485 CLK_OF_DECLARE(ccu_sys, "baikal,bt1-ccu-sys", ccu_div_init);
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