Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
0004  *
0005  * Authors:
0006  *   Serge Semin <Sergey.Semin@baikalelectronics.ru>
0007  *   Dmitry Dunaev <dmitry.dunaev@baikalelectronics.ru>
0008  *
0009  * Baikal-T1 CCU Dividers interface driver
0010  */
0011 
0012 #define pr_fmt(fmt) "bt1-ccu-div: " fmt
0013 
0014 #include <linux/kernel.h>
0015 #include <linux/printk.h>
0016 #include <linux/bits.h>
0017 #include <linux/bitfield.h>
0018 #include <linux/slab.h>
0019 #include <linux/clk-provider.h>
0020 #include <linux/of.h>
0021 #include <linux/spinlock.h>
0022 #include <linux/regmap.h>
0023 #include <linux/delay.h>
0024 #include <linux/time64.h>
0025 #include <linux/debugfs.h>
0026 
0027 #include "ccu-div.h"
0028 
0029 #define CCU_DIV_CTL         0x00
0030 #define CCU_DIV_CTL_EN          BIT(0)
0031 #define CCU_DIV_CTL_RST         BIT(1)
0032 #define CCU_DIV_CTL_SET_CLKDIV      BIT(2)
0033 #define CCU_DIV_CTL_CLKDIV_FLD      4
0034 #define CCU_DIV_CTL_CLKDIV_MASK(_width) \
0035     GENMASK((_width) + CCU_DIV_CTL_CLKDIV_FLD - 1, CCU_DIV_CTL_CLKDIV_FLD)
0036 #define CCU_DIV_CTL_LOCK_SHIFTED    BIT(27)
0037 #define CCU_DIV_CTL_LOCK_NORMAL     BIT(31)
0038 
0039 #define CCU_DIV_RST_DELAY_US        1
0040 #define CCU_DIV_LOCK_CHECK_RETRIES  50
0041 
0042 #define CCU_DIV_CLKDIV_MIN      0
0043 #define CCU_DIV_CLKDIV_MAX(_mask) \
0044     ((_mask) >> CCU_DIV_CTL_CLKDIV_FLD)
0045 
0046 /*
0047  * Use the next two methods until there are generic field setter and
0048  * getter available with non-constant mask support.
0049  */
0050 static inline u32 ccu_div_get(u32 mask, u32 val)
0051 {
0052     return (val & mask) >> CCU_DIV_CTL_CLKDIV_FLD;
0053 }
0054 
0055 static inline u32 ccu_div_prep(u32 mask, u32 val)
0056 {
0057     return (val << CCU_DIV_CTL_CLKDIV_FLD) & mask;
0058 }
0059 
0060 static inline unsigned long ccu_div_lock_delay_ns(unsigned long ref_clk,
0061                           unsigned long div)
0062 {
0063     u64 ns = 4ULL * (div ?: 1) * NSEC_PER_SEC;
0064 
0065     do_div(ns, ref_clk);
0066 
0067     return ns;
0068 }
0069 
0070 static inline unsigned long ccu_div_calc_freq(unsigned long ref_clk,
0071                           unsigned long div)
0072 {
0073     return ref_clk / (div ?: 1);
0074 }
0075 
0076 static int ccu_div_var_update_clkdiv(struct ccu_div *div,
0077                      unsigned long parent_rate,
0078                      unsigned long divider)
0079 {
0080     unsigned long nd;
0081     u32 val = 0;
0082     u32 lock;
0083     int count;
0084 
0085     nd = ccu_div_lock_delay_ns(parent_rate, divider);
0086 
0087     if (div->features & CCU_DIV_LOCK_SHIFTED)
0088         lock = CCU_DIV_CTL_LOCK_SHIFTED;
0089     else
0090         lock = CCU_DIV_CTL_LOCK_NORMAL;
0091 
0092     regmap_update_bits(div->sys_regs, div->reg_ctl,
0093                CCU_DIV_CTL_SET_CLKDIV, CCU_DIV_CTL_SET_CLKDIV);
0094 
0095     /*
0096      * Until there is nsec-version of readl_poll_timeout() is available
0097      * we have to implement the next polling loop.
0098      */
0099     count = CCU_DIV_LOCK_CHECK_RETRIES;
0100     do {
0101         ndelay(nd);
0102         regmap_read(div->sys_regs, div->reg_ctl, &val);
0103         if (val & lock)
0104             return 0;
0105     } while (--count);
0106 
0107     return -ETIMEDOUT;
0108 }
0109 
0110 static int ccu_div_var_enable(struct clk_hw *hw)
0111 {
0112     struct clk_hw *parent_hw = clk_hw_get_parent(hw);
0113     struct ccu_div *div = to_ccu_div(hw);
0114     unsigned long flags;
0115     u32 val = 0;
0116     int ret;
0117 
0118     if (!parent_hw) {
0119         pr_err("Can't enable '%s' with no parent", clk_hw_get_name(hw));
0120         return -EINVAL;
0121     }
0122 
0123     regmap_read(div->sys_regs, div->reg_ctl, &val);
0124     if (val & CCU_DIV_CTL_EN)
0125         return 0;
0126 
0127     spin_lock_irqsave(&div->lock, flags);
0128     ret = ccu_div_var_update_clkdiv(div, clk_hw_get_rate(parent_hw),
0129                     ccu_div_get(div->mask, val));
0130     if (!ret)
0131         regmap_update_bits(div->sys_regs, div->reg_ctl,
0132                    CCU_DIV_CTL_EN, CCU_DIV_CTL_EN);
0133     spin_unlock_irqrestore(&div->lock, flags);
0134     if (ret)
0135         pr_err("Divider '%s' lock timed out\n", clk_hw_get_name(hw));
0136 
0137     return ret;
0138 }
0139 
0140 static int ccu_div_gate_enable(struct clk_hw *hw)
0141 {
0142     struct ccu_div *div = to_ccu_div(hw);
0143     unsigned long flags;
0144 
0145     spin_lock_irqsave(&div->lock, flags);
0146     regmap_update_bits(div->sys_regs, div->reg_ctl,
0147                CCU_DIV_CTL_EN, CCU_DIV_CTL_EN);
0148     spin_unlock_irqrestore(&div->lock, flags);
0149 
0150     return 0;
0151 }
0152 
0153 static void ccu_div_gate_disable(struct clk_hw *hw)
0154 {
0155     struct ccu_div *div = to_ccu_div(hw);
0156     unsigned long flags;
0157 
0158     spin_lock_irqsave(&div->lock, flags);
0159     regmap_update_bits(div->sys_regs, div->reg_ctl, CCU_DIV_CTL_EN, 0);
0160     spin_unlock_irqrestore(&div->lock, flags);
0161 }
0162 
0163 static int ccu_div_gate_is_enabled(struct clk_hw *hw)
0164 {
0165     struct ccu_div *div = to_ccu_div(hw);
0166     u32 val = 0;
0167 
0168     regmap_read(div->sys_regs, div->reg_ctl, &val);
0169 
0170     return !!(val & CCU_DIV_CTL_EN);
0171 }
0172 
0173 static unsigned long ccu_div_var_recalc_rate(struct clk_hw *hw,
0174                          unsigned long parent_rate)
0175 {
0176     struct ccu_div *div = to_ccu_div(hw);
0177     unsigned long divider;
0178     u32 val = 0;
0179 
0180     regmap_read(div->sys_regs, div->reg_ctl, &val);
0181     divider = ccu_div_get(div->mask, val);
0182 
0183     return ccu_div_calc_freq(parent_rate, divider);
0184 }
0185 
0186 static inline unsigned long ccu_div_var_calc_divider(unsigned long rate,
0187                              unsigned long parent_rate,
0188                              unsigned int mask)
0189 {
0190     unsigned long divider;
0191 
0192     divider = parent_rate / rate;
0193     return clamp_t(unsigned long, divider, CCU_DIV_CLKDIV_MIN,
0194                CCU_DIV_CLKDIV_MAX(mask));
0195 }
0196 
0197 static long ccu_div_var_round_rate(struct clk_hw *hw, unsigned long rate,
0198                    unsigned long *parent_rate)
0199 {
0200     struct ccu_div *div = to_ccu_div(hw);
0201     unsigned long divider;
0202 
0203     divider = ccu_div_var_calc_divider(rate, *parent_rate, div->mask);
0204 
0205     return ccu_div_calc_freq(*parent_rate, divider);
0206 }
0207 
0208 /*
0209  * This method is used for the clock divider blocks, which support the
0210  * on-the-fly rate change. So due to lacking the EN bit functionality
0211  * they can't be gated before the rate adjustment.
0212  */
0213 static int ccu_div_var_set_rate_slow(struct clk_hw *hw, unsigned long rate,
0214                      unsigned long parent_rate)
0215 {
0216     struct ccu_div *div = to_ccu_div(hw);
0217     unsigned long flags, divider;
0218     u32 val;
0219     int ret;
0220 
0221     divider = ccu_div_var_calc_divider(rate, parent_rate, div->mask);
0222     if (divider == 1 && div->features & CCU_DIV_SKIP_ONE) {
0223         divider = 0;
0224     } else if (div->features & CCU_DIV_SKIP_ONE_TO_THREE) {
0225         if (divider == 1 || divider == 2)
0226             divider = 0;
0227         else if (divider == 3)
0228             divider = 4;
0229     }
0230 
0231     val = ccu_div_prep(div->mask, divider);
0232 
0233     spin_lock_irqsave(&div->lock, flags);
0234     regmap_update_bits(div->sys_regs, div->reg_ctl, div->mask, val);
0235     ret = ccu_div_var_update_clkdiv(div, parent_rate, divider);
0236     spin_unlock_irqrestore(&div->lock, flags);
0237     if (ret)
0238         pr_err("Divider '%s' lock timed out\n", clk_hw_get_name(hw));
0239 
0240     return ret;
0241 }
0242 
0243 /*
0244  * This method is used for the clock divider blocks, which don't support
0245  * the on-the-fly rate change.
0246  */
0247 static int ccu_div_var_set_rate_fast(struct clk_hw *hw, unsigned long rate,
0248                      unsigned long parent_rate)
0249 {
0250     struct ccu_div *div = to_ccu_div(hw);
0251     unsigned long flags, divider;
0252     u32 val;
0253 
0254     divider = ccu_div_var_calc_divider(rate, parent_rate, div->mask);
0255     val = ccu_div_prep(div->mask, divider);
0256 
0257     /*
0258      * Also disable the clock divider block if it was enabled by default
0259      * or by the bootloader.
0260      */
0261     spin_lock_irqsave(&div->lock, flags);
0262     regmap_update_bits(div->sys_regs, div->reg_ctl,
0263                div->mask | CCU_DIV_CTL_EN, val);
0264     spin_unlock_irqrestore(&div->lock, flags);
0265 
0266     return 0;
0267 }
0268 
0269 static unsigned long ccu_div_fixed_recalc_rate(struct clk_hw *hw,
0270                            unsigned long parent_rate)
0271 {
0272     struct ccu_div *div = to_ccu_div(hw);
0273 
0274     return ccu_div_calc_freq(parent_rate, div->divider);
0275 }
0276 
0277 static long ccu_div_fixed_round_rate(struct clk_hw *hw, unsigned long rate,
0278                      unsigned long *parent_rate)
0279 {
0280     struct ccu_div *div = to_ccu_div(hw);
0281 
0282     return ccu_div_calc_freq(*parent_rate, div->divider);
0283 }
0284 
0285 static int ccu_div_fixed_set_rate(struct clk_hw *hw, unsigned long rate,
0286                   unsigned long parent_rate)
0287 {
0288     return 0;
0289 }
0290 
0291 int ccu_div_reset_domain(struct ccu_div *div)
0292 {
0293     unsigned long flags;
0294 
0295     if (!div || !(div->features & CCU_DIV_RESET_DOMAIN))
0296         return -EINVAL;
0297 
0298     spin_lock_irqsave(&div->lock, flags);
0299     regmap_update_bits(div->sys_regs, div->reg_ctl,
0300                CCU_DIV_CTL_RST, CCU_DIV_CTL_RST);
0301     spin_unlock_irqrestore(&div->lock, flags);
0302 
0303     /* The next delay must be enough to cover all the resets. */
0304     udelay(CCU_DIV_RST_DELAY_US);
0305 
0306     return 0;
0307 }
0308 
0309 #ifdef CONFIG_DEBUG_FS
0310 
0311 struct ccu_div_dbgfs_bit {
0312     struct ccu_div *div;
0313     const char *name;
0314     u32 mask;
0315 };
0316 
0317 #define CCU_DIV_DBGFS_BIT_ATTR(_name, _mask) {  \
0318         .name = _name,          \
0319         .mask = _mask           \
0320     }
0321 
0322 static const struct ccu_div_dbgfs_bit ccu_div_bits[] = {
0323     CCU_DIV_DBGFS_BIT_ATTR("div_en", CCU_DIV_CTL_EN),
0324     CCU_DIV_DBGFS_BIT_ATTR("div_rst", CCU_DIV_CTL_RST),
0325     CCU_DIV_DBGFS_BIT_ATTR("div_bypass", CCU_DIV_CTL_SET_CLKDIV),
0326     CCU_DIV_DBGFS_BIT_ATTR("div_lock", CCU_DIV_CTL_LOCK_NORMAL)
0327 };
0328 
0329 #define CCU_DIV_DBGFS_BIT_NUM   ARRAY_SIZE(ccu_div_bits)
0330 
0331 /*
0332  * It can be dangerous to change the Divider settings behind clock framework
0333  * back, therefore we don't provide any kernel config based compile time option
0334  * for this feature to enable.
0335  */
0336 #undef CCU_DIV_ALLOW_WRITE_DEBUGFS
0337 #ifdef CCU_DIV_ALLOW_WRITE_DEBUGFS
0338 
0339 static int ccu_div_dbgfs_bit_set(void *priv, u64 val)
0340 {
0341     const struct ccu_div_dbgfs_bit *bit = priv;
0342     struct ccu_div *div = bit->div;
0343     unsigned long flags;
0344 
0345     spin_lock_irqsave(&div->lock, flags);
0346     regmap_update_bits(div->sys_regs, div->reg_ctl,
0347                bit->mask, val ? bit->mask : 0);
0348     spin_unlock_irqrestore(&div->lock, flags);
0349 
0350     return 0;
0351 }
0352 
0353 static int ccu_div_dbgfs_var_clkdiv_set(void *priv, u64 val)
0354 {
0355     struct ccu_div *div = priv;
0356     unsigned long flags;
0357     u32 data;
0358 
0359     val = clamp_t(u64, val, CCU_DIV_CLKDIV_MIN,
0360               CCU_DIV_CLKDIV_MAX(div->mask));
0361     data = ccu_div_prep(div->mask, val);
0362 
0363     spin_lock_irqsave(&div->lock, flags);
0364     regmap_update_bits(div->sys_regs, div->reg_ctl, div->mask, data);
0365     spin_unlock_irqrestore(&div->lock, flags);
0366 
0367     return 0;
0368 }
0369 
0370 #define ccu_div_dbgfs_mode      0644
0371 
0372 #else /* !CCU_DIV_ALLOW_WRITE_DEBUGFS */
0373 
0374 #define ccu_div_dbgfs_bit_set       NULL
0375 #define ccu_div_dbgfs_var_clkdiv_set    NULL
0376 #define ccu_div_dbgfs_mode      0444
0377 
0378 #endif /* !CCU_DIV_ALLOW_WRITE_DEBUGFS */
0379 
0380 static int ccu_div_dbgfs_bit_get(void *priv, u64 *val)
0381 {
0382     const struct ccu_div_dbgfs_bit *bit = priv;
0383     struct ccu_div *div = bit->div;
0384     u32 data = 0;
0385 
0386     regmap_read(div->sys_regs, div->reg_ctl, &data);
0387     *val = !!(data & bit->mask);
0388 
0389     return 0;
0390 }
0391 DEFINE_DEBUGFS_ATTRIBUTE(ccu_div_dbgfs_bit_fops,
0392     ccu_div_dbgfs_bit_get, ccu_div_dbgfs_bit_set, "%llu\n");
0393 
0394 static int ccu_div_dbgfs_var_clkdiv_get(void *priv, u64 *val)
0395 {
0396     struct ccu_div *div = priv;
0397     u32 data = 0;
0398 
0399     regmap_read(div->sys_regs, div->reg_ctl, &data);
0400     *val = ccu_div_get(div->mask, data);
0401 
0402     return 0;
0403 }
0404 DEFINE_DEBUGFS_ATTRIBUTE(ccu_div_dbgfs_var_clkdiv_fops,
0405     ccu_div_dbgfs_var_clkdiv_get, ccu_div_dbgfs_var_clkdiv_set, "%llu\n");
0406 
0407 static int ccu_div_dbgfs_fixed_clkdiv_get(void *priv, u64 *val)
0408 {
0409     struct ccu_div *div = priv;
0410 
0411     *val = div->divider;
0412 
0413     return 0;
0414 }
0415 DEFINE_DEBUGFS_ATTRIBUTE(ccu_div_dbgfs_fixed_clkdiv_fops,
0416     ccu_div_dbgfs_fixed_clkdiv_get, NULL, "%llu\n");
0417 
0418 static void ccu_div_var_debug_init(struct clk_hw *hw, struct dentry *dentry)
0419 {
0420     struct ccu_div *div = to_ccu_div(hw);
0421     struct ccu_div_dbgfs_bit *bits;
0422     int didx, bidx, num = 2;
0423     const char *name;
0424 
0425     num += !!(div->flags & CLK_SET_RATE_GATE) +
0426         !!(div->features & CCU_DIV_RESET_DOMAIN);
0427 
0428     bits = kcalloc(num, sizeof(*bits), GFP_KERNEL);
0429     if (!bits)
0430         return;
0431 
0432     for (didx = 0, bidx = 0; bidx < CCU_DIV_DBGFS_BIT_NUM; ++bidx) {
0433         name = ccu_div_bits[bidx].name;
0434         if (!(div->flags & CLK_SET_RATE_GATE) &&
0435             !strcmp("div_en", name)) {
0436             continue;
0437         }
0438 
0439         if (!(div->features & CCU_DIV_RESET_DOMAIN) &&
0440             !strcmp("div_rst", name)) {
0441             continue;
0442         }
0443 
0444         bits[didx] = ccu_div_bits[bidx];
0445         bits[didx].div = div;
0446 
0447         if (div->features & CCU_DIV_LOCK_SHIFTED &&
0448             !strcmp("div_lock", name)) {
0449             bits[didx].mask = CCU_DIV_CTL_LOCK_SHIFTED;
0450         }
0451 
0452         debugfs_create_file_unsafe(bits[didx].name, ccu_div_dbgfs_mode,
0453                        dentry, &bits[didx],
0454                        &ccu_div_dbgfs_bit_fops);
0455         ++didx;
0456     }
0457 
0458     debugfs_create_file_unsafe("div_clkdiv", ccu_div_dbgfs_mode, dentry,
0459                    div, &ccu_div_dbgfs_var_clkdiv_fops);
0460 }
0461 
0462 static void ccu_div_gate_debug_init(struct clk_hw *hw, struct dentry *dentry)
0463 {
0464     struct ccu_div *div = to_ccu_div(hw);
0465     struct ccu_div_dbgfs_bit *bit;
0466 
0467     bit = kmalloc(sizeof(*bit), GFP_KERNEL);
0468     if (!bit)
0469         return;
0470 
0471     *bit = ccu_div_bits[0];
0472     bit->div = div;
0473     debugfs_create_file_unsafe(bit->name, ccu_div_dbgfs_mode, dentry, bit,
0474                    &ccu_div_dbgfs_bit_fops);
0475 
0476     debugfs_create_file_unsafe("div_clkdiv", 0400, dentry, div,
0477                    &ccu_div_dbgfs_fixed_clkdiv_fops);
0478 }
0479 
0480 static void ccu_div_fixed_debug_init(struct clk_hw *hw, struct dentry *dentry)
0481 {
0482     struct ccu_div *div = to_ccu_div(hw);
0483 
0484     debugfs_create_file_unsafe("div_clkdiv", 0400, dentry, div,
0485                    &ccu_div_dbgfs_fixed_clkdiv_fops);
0486 }
0487 
0488 #else /* !CONFIG_DEBUG_FS */
0489 
0490 #define ccu_div_var_debug_init NULL
0491 #define ccu_div_gate_debug_init NULL
0492 #define ccu_div_fixed_debug_init NULL
0493 
0494 #endif /* !CONFIG_DEBUG_FS */
0495 
0496 static const struct clk_ops ccu_div_var_gate_to_set_ops = {
0497     .enable = ccu_div_var_enable,
0498     .disable = ccu_div_gate_disable,
0499     .is_enabled = ccu_div_gate_is_enabled,
0500     .recalc_rate = ccu_div_var_recalc_rate,
0501     .round_rate = ccu_div_var_round_rate,
0502     .set_rate = ccu_div_var_set_rate_fast,
0503     .debug_init = ccu_div_var_debug_init
0504 };
0505 
0506 static const struct clk_ops ccu_div_var_nogate_ops = {
0507     .recalc_rate = ccu_div_var_recalc_rate,
0508     .round_rate = ccu_div_var_round_rate,
0509     .set_rate = ccu_div_var_set_rate_slow,
0510     .debug_init = ccu_div_var_debug_init
0511 };
0512 
0513 static const struct clk_ops ccu_div_gate_ops = {
0514     .enable = ccu_div_gate_enable,
0515     .disable = ccu_div_gate_disable,
0516     .is_enabled = ccu_div_gate_is_enabled,
0517     .recalc_rate = ccu_div_fixed_recalc_rate,
0518     .round_rate = ccu_div_fixed_round_rate,
0519     .set_rate = ccu_div_fixed_set_rate,
0520     .debug_init = ccu_div_gate_debug_init
0521 };
0522 
0523 static const struct clk_ops ccu_div_fixed_ops = {
0524     .recalc_rate = ccu_div_fixed_recalc_rate,
0525     .round_rate = ccu_div_fixed_round_rate,
0526     .set_rate = ccu_div_fixed_set_rate,
0527     .debug_init = ccu_div_fixed_debug_init
0528 };
0529 
0530 struct ccu_div *ccu_div_hw_register(const struct ccu_div_init_data *div_init)
0531 {
0532     struct clk_parent_data parent_data = { };
0533     struct clk_init_data hw_init = { };
0534     struct ccu_div *div;
0535     int ret;
0536 
0537     if (!div_init)
0538         return ERR_PTR(-EINVAL);
0539 
0540     div = kzalloc(sizeof(*div), GFP_KERNEL);
0541     if (!div)
0542         return ERR_PTR(-ENOMEM);
0543 
0544     /*
0545      * Note since Baikal-T1 System Controller registers are MMIO-backed
0546      * we won't check the regmap IO operations return status, because it
0547      * must be zero anyway.
0548      */
0549     div->hw.init = &hw_init;
0550     div->id = div_init->id;
0551     div->reg_ctl = div_init->base + CCU_DIV_CTL;
0552     div->sys_regs = div_init->sys_regs;
0553     div->flags = div_init->flags;
0554     div->features = div_init->features;
0555     spin_lock_init(&div->lock);
0556 
0557     hw_init.name = div_init->name;
0558     hw_init.flags = div_init->flags;
0559 
0560     if (div_init->type == CCU_DIV_VAR) {
0561         if (hw_init.flags & CLK_SET_RATE_GATE)
0562             hw_init.ops = &ccu_div_var_gate_to_set_ops;
0563         else
0564             hw_init.ops = &ccu_div_var_nogate_ops;
0565         div->mask = CCU_DIV_CTL_CLKDIV_MASK(div_init->width);
0566     } else if (div_init->type == CCU_DIV_GATE) {
0567         hw_init.ops = &ccu_div_gate_ops;
0568         div->divider = div_init->divider;
0569     } else if (div_init->type == CCU_DIV_FIXED) {
0570         hw_init.ops = &ccu_div_fixed_ops;
0571         div->divider = div_init->divider;
0572     } else {
0573         ret = -EINVAL;
0574         goto err_free_div;
0575     }
0576 
0577     if (!div_init->parent_name) {
0578         ret = -EINVAL;
0579         goto err_free_div;
0580     }
0581     parent_data.fw_name = div_init->parent_name;
0582     hw_init.parent_data = &parent_data;
0583     hw_init.num_parents = 1;
0584 
0585     ret = of_clk_hw_register(div_init->np, &div->hw);
0586     if (ret)
0587         goto err_free_div;
0588 
0589     return div;
0590 
0591 err_free_div:
0592     kfree(div);
0593 
0594     return ERR_PTR(ret);
0595 }
0596 
0597 void ccu_div_hw_unregister(struct ccu_div *div)
0598 {
0599     clk_hw_unregister(&div->hw);
0600 
0601     kfree(div);
0602 }
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!