0001 # SPDX-License-Identifier: GPL-2.0-only
0002 config CLK_BAIKAL_T1
0003 bool "Baikal-T1 Clocks Control Unit interface"
0004 depends on (MIPS_BAIKAL_T1 && OF) || COMPILE_TEST
0005 default MIPS_BAIKAL_T1
0006 help
0007 Clocks Control Unit is the core of Baikal-T1 SoC System Controller
0008 responsible for the chip subsystems clocking and resetting. It
0009 consists of multiple global clock domains, which can be reset by
0010 means of the CCU control registers. These domains and devices placed
0011 in them are fed with clocks generated by a hierarchy of PLLs,
0012 configurable and fixed clock dividers. Enable this option to be able
0013 to select Baikal-T1 CCU PLLs and Dividers drivers.
0014
0015 if CLK_BAIKAL_T1
0016
0017 config CLK_BT1_CCU_PLL
0018 bool "Baikal-T1 CCU PLLs support"
0019 select MFD_SYSCON
0020 default MIPS_BAIKAL_T1
0021 help
0022 Enable this to support the PLLs embedded into the Baikal-T1 SoC
0023 System Controller. These are five PLLs placed at the root of the
0024 clocks hierarchy, right after an external reference oscillator
0025 (normally of 25MHz). They are used to generate high frequency
0026 signals, which are either directly wired to the consumers (like
0027 CPUs, DDR, etc.) or passed over the clock dividers to be only
0028 then used as an individual reference clock of a target device.
0029
0030 config CLK_BT1_CCU_DIV
0031 bool "Baikal-T1 CCU Dividers support"
0032 select RESET_CONTROLLER
0033 select MFD_SYSCON
0034 default MIPS_BAIKAL_T1
0035 help
0036 Enable this to support the CCU dividers used to distribute clocks
0037 between AXI-bus and system devices coming from CCU PLLs of Baikal-T1
0038 SoC. CCU dividers can be either configurable or with fixed divider,
0039 either gateable or ungateable. Some of the CCU dividers can be as well
0040 used to reset the domains they're supplying clock to.
0041
0042 endif
