clk/axs10x/pll_clock.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Synopsys AXS10X SDP Generic PLL clock driver
0004  *
0005  * Copyright (C) 2017 Synopsys
0006  */
0007
0008 #include <linux/platform_device.h>
0009 #include <linux/module.h>
0010 #include <linux/clk-provider.h>
0011 #include <linux/delay.h>
0012 #include <linux/err.h>
0013 #include <linux/device.h>
0014 #include <linux/io.h>
0015 #include <linux/of_address.h>
0016 #include <linux/of_device.h>
0017 #include <linux/slab.h>
0018 #include <linux/of.h>
0019
0020 /* PLL registers addresses */
0021 #define PLL_REG_IDIV    0x0
0022 #define PLL_REG_FBDIV   0x4
0023 #define PLL_REG_ODIV    0x8
0024
0025 /*
0026  * Bit fields of the PLL IDIV/FBDIV/ODIV registers:
0027  *  ________________________________________________________________________
0028  * |31                15|    14    |   13   |  12  |11         6|5         0|
0029  * |-------RESRVED------|-NOUPDATE-|-BYPASS-|-EDGE-|--HIGHTIME--|--LOWTIME--|
0030  * |____________________|__________|________|______|____________|___________|
0031  *
0032  * Following macros determine the way of access to these registers
0033  * They should be set up only using the macros.
0034  * reg should be an u32 variable.
0035  */
0036
0037 #define PLL_REG_GET_LOW(reg)            \
0038     (((reg) & (0x3F << 0)) >> 0)
0039 #define PLL_REG_GET_HIGH(reg)           \
0040     (((reg) & (0x3F << 6)) >> 6)
0041 #define PLL_REG_GET_EDGE(reg)           \
0042     (((reg) & (BIT(12))) ? 1 : 0)
0043 #define PLL_REG_GET_BYPASS(reg)         \
0044     (((reg) & (BIT(13))) ? 1 : 0)
0045 #define PLL_REG_GET_NOUPD(reg)          \
0046     (((reg) & (BIT(14))) ? 1 : 0)
0047 #define PLL_REG_GET_PAD(reg)            \
0048     (((reg) & (0x1FFFF << 15)) >> 15)
0049
0050 #define PLL_REG_SET_LOW(reg, value)     \
0051     { reg |= (((value) & 0x3F) << 0); }
0052 #define PLL_REG_SET_HIGH(reg, value)        \
0053     { reg |= (((value) & 0x3F) << 6); }
0054 #define PLL_REG_SET_EDGE(reg, value)        \
0055     { reg |= (((value) & 0x01) << 12); }
0056 #define PLL_REG_SET_BYPASS(reg, value)      \
0057     { reg |= (((value) & 0x01) << 13); }
0058 #define PLL_REG_SET_NOUPD(reg, value)       \
0059     { reg |= (((value) & 0x01) << 14); }
0060 #define PLL_REG_SET_PAD(reg, value)     \
0061     { reg |= (((value) & 0x1FFFF) << 15); }
0062
0063 #define PLL_LOCK    BIT(0)
0064 #define PLL_ERROR   BIT(1)
0065 #define PLL_MAX_LOCK_TIME 100 /* 100 us */
0066
0067 struct axs10x_pll_cfg {
0068     u32 rate;
0069     u32 idiv;
0070     u32 fbdiv;
0071     u32 odiv;
0072 };
0073
0074 static const struct axs10x_pll_cfg arc_pll_cfg[] = {
0075     { 33333333,  1, 1,  1 },
0076     { 50000000,  1, 30, 20 },
0077     { 75000000,  2, 45, 10 },
0078     { 90000000,  2, 54, 10 },
0079     { 100000000, 1, 30, 10 },
0080     { 125000000, 2, 45, 6 },
0081     {}
0082 };
0083
0084 static const struct axs10x_pll_cfg pgu_pll_cfg[] = {
0085     { 25200000, 1, 84, 90 },
0086     { 50000000, 1, 100, 54 },
0087     { 74250000, 1, 44, 16 },
0088     {}
0089 };
0090
0091 struct axs10x_pll_clk {
0092     struct clk_hw hw;
0093     void __iomem *base;
0094     void __iomem *lock;
0095     const struct axs10x_pll_cfg *pll_cfg;
0096     struct device *dev;
0097 };
0098
0099 static inline void axs10x_pll_write(struct axs10x_pll_clk *clk, u32 reg,
0100                     u32 val)
0101 {
0102     iowrite32(val, clk->base + reg);
0103 }
0104
0105 static inline u32 axs10x_pll_read(struct axs10x_pll_clk *clk, u32 reg)
0106 {
0107     return ioread32(clk->base + reg);
0108 }
0109
0110 static inline struct axs10x_pll_clk *to_axs10x_pll_clk(struct clk_hw *hw)
0111 {
0112     return container_of(hw, struct axs10x_pll_clk, hw);
0113 }
0114
0115 static inline u32 axs10x_div_get_value(u32 reg)
0116 {
0117     if (PLL_REG_GET_BYPASS(reg))
0118         return 1;
0119
0120     return PLL_REG_GET_HIGH(reg) + PLL_REG_GET_LOW(reg);
0121 }
0122
0123 static inline u32 axs10x_encode_div(unsigned int id, int upd)
0124 {
0125     u32 div = 0;
0126
0127     PLL_REG_SET_LOW(div, (id % 2 == 0) ? id >> 1 : (id >> 1) + 1);
0128     PLL_REG_SET_HIGH(div, id >> 1);
0129     PLL_REG_SET_EDGE(div, id % 2);
0130     PLL_REG_SET_BYPASS(div, id == 1 ? 1 : 0);
0131     PLL_REG_SET_NOUPD(div, upd == 0 ? 1 : 0);
0132
0133     return div;
0134 }
0135
0136 static unsigned long axs10x_pll_recalc_rate(struct clk_hw *hw,
0137                         unsigned long parent_rate)
0138 {
0139     u64 rate;
0140     u32 idiv, fbdiv, odiv;
0141     struct axs10x_pll_clk *clk = to_axs10x_pll_clk(hw);
0142
0143     idiv = axs10x_div_get_value(axs10x_pll_read(clk, PLL_REG_IDIV));
0144     fbdiv = axs10x_div_get_value(axs10x_pll_read(clk, PLL_REG_FBDIV));
0145     odiv = axs10x_div_get_value(axs10x_pll_read(clk, PLL_REG_ODIV));
0146
0147     rate = (u64)parent_rate * fbdiv;
0148     do_div(rate, idiv * odiv);
0149
0150     return rate;
0151 }
0152
0153 static long axs10x_pll_round_rate(struct clk_hw *hw, unsigned long rate,
0154                   unsigned long *prate)
0155 {
0156     int i;
0157     long best_rate;
0158     struct axs10x_pll_clk *clk = to_axs10x_pll_clk(hw);
0159     const struct axs10x_pll_cfg *pll_cfg = clk->pll_cfg;
0160
0161     if (pll_cfg[0].rate == 0)
0162         return -EINVAL;
0163
0164     best_rate = pll_cfg[0].rate;
0165
0166     for (i = 1; pll_cfg[i].rate != 0; i++) {
0167         if (abs(rate - pll_cfg[i].rate) < abs(rate - best_rate))
0168             best_rate = pll_cfg[i].rate;
0169     }
0170
0171     return best_rate;
0172 }
0173
0174 static int axs10x_pll_set_rate(struct clk_hw *hw, unsigned long rate,
0175                    unsigned long parent_rate)
0176 {
0177     int i;
0178     struct axs10x_pll_clk *clk = to_axs10x_pll_clk(hw);
0179     const struct axs10x_pll_cfg *pll_cfg = clk->pll_cfg;
0180
0181     for (i = 0; pll_cfg[i].rate != 0; i++) {
0182         if (pll_cfg[i].rate == rate) {
0183             axs10x_pll_write(clk, PLL_REG_IDIV,
0184                      axs10x_encode_div(pll_cfg[i].idiv, 0));
0185             axs10x_pll_write(clk, PLL_REG_FBDIV,
0186                      axs10x_encode_div(pll_cfg[i].fbdiv, 0));
0187             axs10x_pll_write(clk, PLL_REG_ODIV,
0188                      axs10x_encode_div(pll_cfg[i].odiv, 1));
0189
0190             /*
0191              * Wait until CGU relocks and check error status.
0192              * If after timeout CGU is unlocked yet return error
0193              */
0194             udelay(PLL_MAX_LOCK_TIME);
0195             if (!(ioread32(clk->lock) & PLL_LOCK))
0196                 return -ETIMEDOUT;
0197
0198             if (ioread32(clk->lock) & PLL_ERROR)
0199                 return -EINVAL;
0200
0201             return 0;
0202         }
0203     }
0204
0205     dev_err(clk->dev, "invalid rate=%ld, parent_rate=%ld\n", rate,
0206             parent_rate);
0207     return -EINVAL;
0208 }
0209
0210 static const struct clk_ops axs10x_pll_ops = {
0211     .recalc_rate = axs10x_pll_recalc_rate,
0212     .round_rate = axs10x_pll_round_rate,
0213     .set_rate = axs10x_pll_set_rate,
0214 };
0215
0216 static int axs10x_pll_clk_probe(struct platform_device *pdev)
0217 {
0218     struct device *dev = &pdev->dev;
0219     const char *parent_name;
0220     struct axs10x_pll_clk *pll_clk;
0221     struct clk_init_data init = { };
0222     int ret;
0223
0224     pll_clk = devm_kzalloc(dev, sizeof(*pll_clk), GFP_KERNEL);
0225     if (!pll_clk)
0226         return -ENOMEM;
0227
0228     pll_clk->base = devm_platform_ioremap_resource(pdev, 0);
0229     if (IS_ERR(pll_clk->base))
0230         return PTR_ERR(pll_clk->base);
0231
0232     pll_clk->lock = devm_platform_ioremap_resource(pdev, 1);
0233     if (IS_ERR(pll_clk->lock))
0234         return PTR_ERR(pll_clk->lock);
0235
0236     init.name = dev->of_node->name;
0237     init.ops = &axs10x_pll_ops;
0238     parent_name = of_clk_get_parent_name(dev->of_node, 0);
0239     init.parent_names = &parent_name;
0240     init.num_parents = 1;
0241     pll_clk->hw.init = &init;
0242     pll_clk->dev = dev;
0243     pll_clk->pll_cfg = of_device_get_match_data(dev);
0244
0245     if (!pll_clk->pll_cfg) {
0246         dev_err(dev, "No OF match data provided\n");
0247         return -EINVAL;
0248     }
0249
0250     ret = devm_clk_hw_register(dev, &pll_clk->hw);
0251     if (ret) {
0252         dev_err(dev, "failed to register %s clock\n", init.name);
0253         return ret;
0254     }
0255
0256     return of_clk_add_hw_provider(dev->of_node, of_clk_hw_simple_get,
0257             &pll_clk->hw);
0258 }
0259
0260 static int axs10x_pll_clk_remove(struct platform_device *pdev)
0261 {
0262     of_clk_del_provider(pdev->dev.of_node);
0263     return 0;
0264 }
0265
0266 static void __init of_axs10x_pll_clk_setup(struct device_node *node)
0267 {
0268     const char *parent_name;
0269     struct axs10x_pll_clk *pll_clk;
0270     struct clk_init_data init = { };
0271     int ret;
0272
0273     pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
0274     if (!pll_clk)
0275         return;
0276
0277     pll_clk->base = of_iomap(node, 0);
0278     if (!pll_clk->base) {
0279         pr_err("failed to map pll div registers\n");
0280         goto err_free_pll_clk;
0281     }
0282
0283     pll_clk->lock = of_iomap(node, 1);
0284     if (!pll_clk->lock) {
0285         pr_err("failed to map pll lock register\n");
0286         goto err_unmap_base;
0287     }
0288
0289     init.name = node->name;
0290     init.ops = &axs10x_pll_ops;
0291     parent_name = of_clk_get_parent_name(node, 0);
0292     init.parent_names = &parent_name;
0293     init.num_parents = parent_name ? 1 : 0;
0294     pll_clk->hw.init = &init;
0295     pll_clk->pll_cfg = arc_pll_cfg;
0296
0297     ret = clk_hw_register(NULL, &pll_clk->hw);
0298     if (ret) {
0299         pr_err("failed to register %pOFn clock\n", node);
0300         goto err_unmap_lock;
0301     }
0302
0303     ret = of_clk_add_hw_provider(node, of_clk_hw_simple_get, &pll_clk->hw);
0304     if (ret) {
0305         pr_err("failed to add hw provider for %pOFn clock\n", node);
0306         goto err_unregister_clk;
0307     }
0308
0309     return;
0310
0311 err_unregister_clk:
0312     clk_hw_unregister(&pll_clk->hw);
0313 err_unmap_lock:
0314     iounmap(pll_clk->lock);
0315 err_unmap_base:
0316     iounmap(pll_clk->base);
0317 err_free_pll_clk:
0318     kfree(pll_clk);
0319 }
0320 CLK_OF_DECLARE(axs10x_pll_clock, "snps,axs10x-arc-pll-clock",
0321            of_axs10x_pll_clk_setup);
0322
0323 static const struct of_device_id axs10x_pll_clk_id[] = {
0324     { .compatible = "snps,axs10x-pgu-pll-clock", .data = &pgu_pll_cfg},
0325     { }
0326 };
0327 MODULE_DEVICE_TABLE(of, axs10x_pll_clk_id);
0328
0329 static struct platform_driver axs10x_pll_clk_driver = {
0330     .driver = {
0331         .name = "axs10x-pll-clock",
0332         .of_match_table = axs10x_pll_clk_id,
0333     },
0334     .probe = axs10x_pll_clk_probe,
0335     .remove = axs10x_pll_clk_remove,
0336 };
0337 builtin_platform_driver(axs10x_pll_clk_driver);
0338
0339 MODULE_AUTHOR("Vlad Zakharov <vzakhar@synopsys.com>");
0340 MODULE_DESCRIPTION("Synopsys AXS10X SDP Generic PLL Clock Driver");
0341 MODULE_LICENSE("GPL v2");