clk/axs10x/i2s_pll_clock.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Synopsys AXS10X SDP I2S PLL clock driver
0004  *
0005  * Copyright (C) 2016 Synopsys
0006  */
0007
0008 #include <linux/platform_device.h>
0009 #include <linux/module.h>
0010 #include <linux/clk-provider.h>
0011 #include <linux/err.h>
0012 #include <linux/device.h>
0013 #include <linux/io.h>
0014 #include <linux/of_address.h>
0015 #include <linux/slab.h>
0016 #include <linux/of.h>
0017
0018 /* PLL registers addresses */
0019 #define PLL_IDIV_REG    0x0
0020 #define PLL_FBDIV_REG   0x4
0021 #define PLL_ODIV0_REG   0x8
0022 #define PLL_ODIV1_REG   0xC
0023
0024 struct i2s_pll_cfg {
0025     unsigned int rate;
0026     unsigned int idiv;
0027     unsigned int fbdiv;
0028     unsigned int odiv0;
0029     unsigned int odiv1;
0030 };
0031
0032 static const struct i2s_pll_cfg i2s_pll_cfg_27m[] = {
0033     /* 27 Mhz */
0034     { 1024000, 0x104, 0x451, 0x10E38, 0x2000 },
0035     { 1411200, 0x104, 0x596, 0x10D35, 0x2000 },
0036     { 1536000, 0x208, 0xA28, 0x10B2C, 0x2000 },
0037     { 2048000, 0x82, 0x451, 0x10E38, 0x2000 },
0038     { 2822400, 0x82, 0x596, 0x10D35, 0x2000 },
0039     { 3072000, 0x104, 0xA28, 0x10B2C, 0x2000 },
0040     { 2116800, 0x82, 0x3CF, 0x10C30, 0x2000 },
0041     { 2304000, 0x104, 0x79E, 0x10B2C, 0x2000 },
0042     { 0, 0, 0, 0, 0 },
0043 };
0044
0045 static const struct i2s_pll_cfg i2s_pll_cfg_28m[] = {
0046     /* 28.224 Mhz */
0047     { 1024000, 0x82, 0x105, 0x107DF, 0x2000 },
0048     { 1411200, 0x28A, 0x1, 0x10001, 0x2000 },
0049     { 1536000, 0xA28, 0x187, 0x10042, 0x2000 },
0050     { 2048000, 0x41, 0x105, 0x107DF, 0x2000 },
0051     { 2822400, 0x145, 0x1, 0x10001, 0x2000 },
0052     { 3072000, 0x514, 0x187, 0x10042, 0x2000 },
0053     { 2116800, 0x514, 0x42, 0x10001, 0x2000 },
0054     { 2304000, 0x619, 0x82, 0x10001, 0x2000 },
0055     { 0, 0, 0, 0, 0 },
0056 };
0057
0058 struct i2s_pll_clk {
0059     void __iomem *base;
0060     struct clk_hw hw;
0061     struct device *dev;
0062 };
0063
0064 static inline void i2s_pll_write(struct i2s_pll_clk *clk, unsigned int reg,
0065         unsigned int val)
0066 {
0067     writel_relaxed(val, clk->base + reg);
0068 }
0069
0070 static inline unsigned int i2s_pll_read(struct i2s_pll_clk *clk,
0071         unsigned int reg)
0072 {
0073     return readl_relaxed(clk->base + reg);
0074 }
0075
0076 static inline struct i2s_pll_clk *to_i2s_pll_clk(struct clk_hw *hw)
0077 {
0078     return container_of(hw, struct i2s_pll_clk, hw);
0079 }
0080
0081 static inline unsigned int i2s_pll_get_value(unsigned int val)
0082 {
0083     return (val & 0x3F) + ((val >> 6) & 0x3F);
0084 }
0085
0086 static const struct i2s_pll_cfg *i2s_pll_get_cfg(unsigned long prate)
0087 {
0088     switch (prate) {
0089     case 27000000:
0090         return i2s_pll_cfg_27m;
0091     case 28224000:
0092         return i2s_pll_cfg_28m;
0093     default:
0094         return NULL;
0095     }
0096 }
0097
0098 static unsigned long i2s_pll_recalc_rate(struct clk_hw *hw,
0099             unsigned long parent_rate)
0100 {
0101     struct i2s_pll_clk *clk = to_i2s_pll_clk(hw);
0102     unsigned int idiv, fbdiv, odiv;
0103
0104     idiv = i2s_pll_get_value(i2s_pll_read(clk, PLL_IDIV_REG));
0105     fbdiv = i2s_pll_get_value(i2s_pll_read(clk, PLL_FBDIV_REG));
0106     odiv = i2s_pll_get_value(i2s_pll_read(clk, PLL_ODIV0_REG));
0107
0108     return ((parent_rate / idiv) * fbdiv) / odiv;
0109 }
0110
0111 static long i2s_pll_round_rate(struct clk_hw *hw, unsigned long rate,
0112             unsigned long *prate)
0113 {
0114     struct i2s_pll_clk *clk = to_i2s_pll_clk(hw);
0115     const struct i2s_pll_cfg *pll_cfg = i2s_pll_get_cfg(*prate);
0116     int i;
0117
0118     if (!pll_cfg) {
0119         dev_err(clk->dev, "invalid parent rate=%ld\n", *prate);
0120         return -EINVAL;
0121     }
0122
0123     for (i = 0; pll_cfg[i].rate != 0; i++)
0124         if (pll_cfg[i].rate == rate)
0125             return rate;
0126
0127     return -EINVAL;
0128 }
0129
0130 static int i2s_pll_set_rate(struct clk_hw *hw, unsigned long rate,
0131             unsigned long parent_rate)
0132 {
0133     struct i2s_pll_clk *clk = to_i2s_pll_clk(hw);
0134     const struct i2s_pll_cfg *pll_cfg = i2s_pll_get_cfg(parent_rate);
0135     int i;
0136
0137     if (!pll_cfg) {
0138         dev_err(clk->dev, "invalid parent rate=%ld\n", parent_rate);
0139         return -EINVAL;
0140     }
0141
0142     for (i = 0; pll_cfg[i].rate != 0; i++) {
0143         if (pll_cfg[i].rate == rate) {
0144             i2s_pll_write(clk, PLL_IDIV_REG, pll_cfg[i].idiv);
0145             i2s_pll_write(clk, PLL_FBDIV_REG, pll_cfg[i].fbdiv);
0146             i2s_pll_write(clk, PLL_ODIV0_REG, pll_cfg[i].odiv0);
0147             i2s_pll_write(clk, PLL_ODIV1_REG, pll_cfg[i].odiv1);
0148             return 0;
0149         }
0150     }
0151
0152     dev_err(clk->dev, "invalid rate=%ld, parent_rate=%ld\n", rate,
0153             parent_rate);
0154     return -EINVAL;
0155 }
0156
0157 static const struct clk_ops i2s_pll_ops = {
0158     .recalc_rate = i2s_pll_recalc_rate,
0159     .round_rate = i2s_pll_round_rate,
0160     .set_rate = i2s_pll_set_rate,
0161 };
0162
0163 static int i2s_pll_clk_probe(struct platform_device *pdev)
0164 {
0165     struct device *dev = &pdev->dev;
0166     struct device_node *node = dev->of_node;
0167     const char *clk_name;
0168     const char *parent_name;
0169     struct clk *clk;
0170     struct i2s_pll_clk *pll_clk;
0171     struct clk_init_data init;
0172
0173     pll_clk = devm_kzalloc(dev, sizeof(*pll_clk), GFP_KERNEL);
0174     if (!pll_clk)
0175         return -ENOMEM;
0176
0177     pll_clk->base = devm_platform_ioremap_resource(pdev, 0);
0178     if (IS_ERR(pll_clk->base))
0179         return PTR_ERR(pll_clk->base);
0180
0181     memset(&init, 0, sizeof(init));
0182     clk_name = node->name;
0183     init.name = clk_name;
0184     init.ops = &i2s_pll_ops;
0185     parent_name = of_clk_get_parent_name(node, 0);
0186     init.parent_names = &parent_name;
0187     init.num_parents = 1;
0188     pll_clk->hw.init = &init;
0189     pll_clk->dev = dev;
0190
0191     clk = devm_clk_register(dev, &pll_clk->hw);
0192     if (IS_ERR(clk)) {
0193         dev_err(dev, "failed to register %s clock (%ld)\n",
0194                 clk_name, PTR_ERR(clk));
0195         return PTR_ERR(clk);
0196     }
0197
0198     return of_clk_add_provider(node, of_clk_src_simple_get, clk);
0199 }
0200
0201 static int i2s_pll_clk_remove(struct platform_device *pdev)
0202 {
0203     of_clk_del_provider(pdev->dev.of_node);
0204     return 0;
0205 }
0206
0207 static const struct of_device_id i2s_pll_clk_id[] = {
0208     { .compatible = "snps,axs10x-i2s-pll-clock", },
0209     { },
0210 };
0211 MODULE_DEVICE_TABLE(of, i2s_pll_clk_id);
0212
0213 static struct platform_driver i2s_pll_clk_driver = {
0214     .driver = {
0215         .name = "axs10x-i2s-pll-clock",
0216         .of_match_table = i2s_pll_clk_id,
0217     },
0218     .probe = i2s_pll_clk_probe,
0219     .remove = i2s_pll_clk_remove,
0220 };
0221 module_platform_driver(i2s_pll_clk_driver);
0222
0223 MODULE_AUTHOR("Jose Abreu <joabreu@synopsys.com>");
0224 MODULE_DESCRIPTION("Synopsys AXS10X SDP I2S PLL Clock Driver");
0225 MODULE_LICENSE("GPL v2");