0001
0002 #include <linux/clk-provider.h>
0003 #include <linux/mfd/syscon.h>
0004 #include <linux/slab.h>
0005
0006 #include <dt-bindings/clock/at91.h>
0007
0008 #include "pmc.h"
0009
0010 static DEFINE_SPINLOCK(mck_lock);
0011
0012 static const struct clk_master_characteristics mck_characteristics = {
0013 .output = { .min = 125000000, .max = 200000000 },
0014 .divisors = { 1, 2, 4, 3 },
0015 };
0016
0017 static u8 plla_out[] = { 0 };
0018
0019 static u16 plla_icpll[] = { 0 };
0020
0021 static const struct clk_range plla_outputs[] = {
0022 { .min = 600000000, .max = 1200000000 },
0023 };
0024
0025 static const struct clk_pll_characteristics plla_characteristics = {
0026 .input = { .min = 12000000, .max = 12000000 },
0027 .num_output = ARRAY_SIZE(plla_outputs),
0028 .output = plla_outputs,
0029 .icpll = plla_icpll,
0030 .out = plla_out,
0031 };
0032
0033 static const struct clk_pcr_layout sama5d4_pcr_layout = {
0034 .offset = 0x10c,
0035 .cmd = BIT(12),
0036 .pid_mask = GENMASK(6, 0),
0037 };
0038
0039 static const struct {
0040 char *n;
0041 char *p;
0042 u8 id;
0043 } sama5d4_systemck[] = {
0044 { .n = "ddrck", .p = "masterck_div", .id = 2 },
0045 { .n = "lcdck", .p = "masterck_div", .id = 3 },
0046 { .n = "smdck", .p = "smdclk", .id = 4 },
0047 { .n = "uhpck", .p = "usbck", .id = 6 },
0048 { .n = "udpck", .p = "usbck", .id = 7 },
0049 { .n = "pck0", .p = "prog0", .id = 8 },
0050 { .n = "pck1", .p = "prog1", .id = 9 },
0051 { .n = "pck2", .p = "prog2", .id = 10 },
0052 };
0053
0054 static const struct {
0055 char *n;
0056 u8 id;
0057 } sama5d4_periph32ck[] = {
0058 { .n = "pioD_clk", .id = 5 },
0059 { .n = "usart0_clk", .id = 6 },
0060 { .n = "usart1_clk", .id = 7 },
0061 { .n = "icm_clk", .id = 9 },
0062 { .n = "aes_clk", .id = 12 },
0063 { .n = "tdes_clk", .id = 14 },
0064 { .n = "sha_clk", .id = 15 },
0065 { .n = "matrix1_clk", .id = 17 },
0066 { .n = "hsmc_clk", .id = 22 },
0067 { .n = "pioA_clk", .id = 23 },
0068 { .n = "pioB_clk", .id = 24 },
0069 { .n = "pioC_clk", .id = 25 },
0070 { .n = "pioE_clk", .id = 26 },
0071 { .n = "uart0_clk", .id = 27 },
0072 { .n = "uart1_clk", .id = 28 },
0073 { .n = "usart2_clk", .id = 29 },
0074 { .n = "usart3_clk", .id = 30 },
0075 { .n = "usart4_clk", .id = 31 },
0076 { .n = "twi0_clk", .id = 32 },
0077 { .n = "twi1_clk", .id = 33 },
0078 { .n = "twi2_clk", .id = 34 },
0079 { .n = "mci0_clk", .id = 35 },
0080 { .n = "mci1_clk", .id = 36 },
0081 { .n = "spi0_clk", .id = 37 },
0082 { .n = "spi1_clk", .id = 38 },
0083 { .n = "spi2_clk", .id = 39 },
0084 { .n = "tcb0_clk", .id = 40 },
0085 { .n = "tcb1_clk", .id = 41 },
0086 { .n = "tcb2_clk", .id = 42 },
0087 { .n = "pwm_clk", .id = 43 },
0088 { .n = "adc_clk", .id = 44 },
0089 { .n = "dbgu_clk", .id = 45 },
0090 { .n = "uhphs_clk", .id = 46 },
0091 { .n = "udphs_clk", .id = 47 },
0092 { .n = "ssc0_clk", .id = 48 },
0093 { .n = "ssc1_clk", .id = 49 },
0094 { .n = "trng_clk", .id = 53 },
0095 { .n = "macb0_clk", .id = 54 },
0096 { .n = "macb1_clk", .id = 55 },
0097 { .n = "fuse_clk", .id = 57 },
0098 { .n = "securam_clk", .id = 59 },
0099 { .n = "smd_clk", .id = 61 },
0100 { .n = "twi3_clk", .id = 62 },
0101 { .n = "catb_clk", .id = 63 },
0102 };
0103
0104 static const struct {
0105 char *n;
0106 u8 id;
0107 } sama5d4_periphck[] = {
0108 { .n = "dma0_clk", .id = 8 },
0109 { .n = "cpkcc_clk", .id = 10 },
0110 { .n = "aesb_clk", .id = 13 },
0111 { .n = "mpddr_clk", .id = 16 },
0112 { .n = "matrix0_clk", .id = 18 },
0113 { .n = "vdec_clk", .id = 19 },
0114 { .n = "dma1_clk", .id = 50 },
0115 { .n = "lcdc_clk", .id = 51 },
0116 { .n = "isi_clk", .id = 52 },
0117 };
0118
0119 static void __init sama5d4_pmc_setup(struct device_node *np)
0120 {
0121 struct clk_range range = CLK_RANGE(0, 0);
0122 const char *slck_name, *mainxtal_name;
0123 struct pmc_data *sama5d4_pmc;
0124 const char *parent_names[5];
0125 struct regmap *regmap;
0126 struct clk_hw *hw;
0127 int i;
0128 bool bypass;
0129
0130 i = of_property_match_string(np, "clock-names", "slow_clk");
0131 if (i < 0)
0132 return;
0133
0134 slck_name = of_clk_get_parent_name(np, i);
0135
0136 i = of_property_match_string(np, "clock-names", "main_xtal");
0137 if (i < 0)
0138 return;
0139 mainxtal_name = of_clk_get_parent_name(np, i);
0140
0141 regmap = device_node_to_regmap(np);
0142 if (IS_ERR(regmap))
0143 return;
0144
0145 sama5d4_pmc = pmc_data_allocate(PMC_PLLACK + 1,
0146 nck(sama5d4_systemck),
0147 nck(sama5d4_periph32ck), 0, 3);
0148 if (!sama5d4_pmc)
0149 return;
0150
0151 hw = at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000,
0152 100000000);
0153 if (IS_ERR(hw))
0154 goto err_free;
0155
0156 bypass = of_property_read_bool(np, "atmel,osc-bypass");
0157
0158 hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name,
0159 bypass);
0160 if (IS_ERR(hw))
0161 goto err_free;
0162
0163 parent_names[0] = "main_rc_osc";
0164 parent_names[1] = "main_osc";
0165 hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, 2);
0166 if (IS_ERR(hw))
0167 goto err_free;
0168
0169 hw = at91_clk_register_pll(regmap, "pllack", "mainck", 0,
0170 &sama5d3_pll_layout, &plla_characteristics);
0171 if (IS_ERR(hw))
0172 goto err_free;
0173
0174 hw = at91_clk_register_plldiv(regmap, "plladivck", "pllack");
0175 if (IS_ERR(hw))
0176 goto err_free;
0177
0178 sama5d4_pmc->chws[PMC_PLLACK] = hw;
0179
0180 hw = at91_clk_register_utmi(regmap, NULL, "utmick", "mainck");
0181 if (IS_ERR(hw))
0182 goto err_free;
0183
0184 sama5d4_pmc->chws[PMC_UTMI] = hw;
0185
0186 parent_names[0] = slck_name;
0187 parent_names[1] = "mainck";
0188 parent_names[2] = "plladivck";
0189 parent_names[3] = "utmick";
0190 hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4,
0191 parent_names,
0192 &at91sam9x5_master_layout,
0193 &mck_characteristics, &mck_lock);
0194 if (IS_ERR(hw))
0195 goto err_free;
0196
0197 hw = at91_clk_register_master_div(regmap, "masterck_div",
0198 "masterck_pres",
0199 &at91sam9x5_master_layout,
0200 &mck_characteristics, &mck_lock,
0201 CLK_SET_RATE_GATE, 0);
0202 if (IS_ERR(hw))
0203 goto err_free;
0204
0205 sama5d4_pmc->chws[PMC_MCK] = hw;
0206
0207 hw = at91_clk_register_h32mx(regmap, "h32mxck", "masterck_div");
0208 if (IS_ERR(hw))
0209 goto err_free;
0210
0211 sama5d4_pmc->chws[PMC_MCK2] = hw;
0212
0213 parent_names[0] = "plladivck";
0214 parent_names[1] = "utmick";
0215 hw = at91sam9x5_clk_register_usb(regmap, "usbck", parent_names, 2);
0216 if (IS_ERR(hw))
0217 goto err_free;
0218
0219 parent_names[0] = "plladivck";
0220 parent_names[1] = "utmick";
0221 hw = at91sam9x5_clk_register_smd(regmap, "smdclk", parent_names, 2);
0222 if (IS_ERR(hw))
0223 goto err_free;
0224
0225 parent_names[0] = slck_name;
0226 parent_names[1] = "mainck";
0227 parent_names[2] = "plladivck";
0228 parent_names[3] = "utmick";
0229 parent_names[4] = "masterck_div";
0230 for (i = 0; i < 3; i++) {
0231 char name[6];
0232
0233 snprintf(name, sizeof(name), "prog%d", i);
0234
0235 hw = at91_clk_register_programmable(regmap, name,
0236 parent_names, 5, i,
0237 &at91sam9x5_programmable_layout,
0238 NULL);
0239 if (IS_ERR(hw))
0240 goto err_free;
0241
0242 sama5d4_pmc->pchws[i] = hw;
0243 }
0244
0245 for (i = 0; i < ARRAY_SIZE(sama5d4_systemck); i++) {
0246 hw = at91_clk_register_system(regmap, sama5d4_systemck[i].n,
0247 sama5d4_systemck[i].p,
0248 sama5d4_systemck[i].id);
0249 if (IS_ERR(hw))
0250 goto err_free;
0251
0252 sama5d4_pmc->shws[sama5d4_systemck[i].id] = hw;
0253 }
0254
0255 for (i = 0; i < ARRAY_SIZE(sama5d4_periphck); i++) {
0256 hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
0257 &sama5d4_pcr_layout,
0258 sama5d4_periphck[i].n,
0259 "masterck_div",
0260 sama5d4_periphck[i].id,
0261 &range, INT_MIN);
0262 if (IS_ERR(hw))
0263 goto err_free;
0264
0265 sama5d4_pmc->phws[sama5d4_periphck[i].id] = hw;
0266 }
0267
0268 for (i = 0; i < ARRAY_SIZE(sama5d4_periph32ck); i++) {
0269 hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
0270 &sama5d4_pcr_layout,
0271 sama5d4_periph32ck[i].n,
0272 "h32mxck",
0273 sama5d4_periph32ck[i].id,
0274 &range, INT_MIN);
0275 if (IS_ERR(hw))
0276 goto err_free;
0277
0278 sama5d4_pmc->phws[sama5d4_periph32ck[i].id] = hw;
0279 }
0280
0281 of_clk_add_hw_provider(np, of_clk_hw_pmc_get, sama5d4_pmc);
0282
0283 return;
0284
0285 err_free:
0286 kfree(sama5d4_pmc);
0287 }
0288
0289 CLK_OF_DECLARE(sama5d4_pmc, "atmel,sama5d4-pmc", sama5d4_pmc_setup);
