0001
0002 #include <linux/clk-provider.h>
0003 #include <linux/mfd/syscon.h>
0004 #include <linux/slab.h>
0005
0006 #include <dt-bindings/clock/at91.h>
0007
0008 #include "pmc.h"
0009
0010 static DEFINE_SPINLOCK(mck_lock);
0011
0012 static const struct clk_master_characteristics mck_characteristics = {
0013 .output = { .min = 0, .max = 166000000 },
0014 .divisors = { 1, 2, 4, 3 },
0015 };
0016
0017 static u8 plla_out[] = { 0 };
0018
0019 static u16 plla_icpll[] = { 0 };
0020
0021 static const struct clk_range plla_outputs[] = {
0022 { .min = 400000000, .max = 1000000000 },
0023 };
0024
0025 static const struct clk_pll_characteristics plla_characteristics = {
0026 .input = { .min = 8000000, .max = 50000000 },
0027 .num_output = ARRAY_SIZE(plla_outputs),
0028 .output = plla_outputs,
0029 .icpll = plla_icpll,
0030 .out = plla_out,
0031 };
0032
0033 static const struct clk_pcr_layout sama5d3_pcr_layout = {
0034 .offset = 0x10c,
0035 .cmd = BIT(12),
0036 .pid_mask = GENMASK(6, 0),
0037 .div_mask = GENMASK(17, 16),
0038 };
0039
0040 static const struct {
0041 char *n;
0042 char *p;
0043 u8 id;
0044 } sama5d3_systemck[] = {
0045 { .n = "ddrck", .p = "masterck_div", .id = 2 },
0046 { .n = "lcdck", .p = "masterck_div", .id = 3 },
0047 { .n = "smdck", .p = "smdclk", .id = 4 },
0048 { .n = "uhpck", .p = "usbck", .id = 6 },
0049 { .n = "udpck", .p = "usbck", .id = 7 },
0050 { .n = "pck0", .p = "prog0", .id = 8 },
0051 { .n = "pck1", .p = "prog1", .id = 9 },
0052 { .n = "pck2", .p = "prog2", .id = 10 },
0053 };
0054
0055 static const struct {
0056 char *n;
0057 u8 id;
0058 struct clk_range r;
0059 } sama5d3_periphck[] = {
0060 { .n = "dbgu_clk", .id = 2, },
0061 { .n = "hsmc_clk", .id = 5, },
0062 { .n = "pioA_clk", .id = 6, },
0063 { .n = "pioB_clk", .id = 7, },
0064 { .n = "pioC_clk", .id = 8, },
0065 { .n = "pioD_clk", .id = 9, },
0066 { .n = "pioE_clk", .id = 10, },
0067 { .n = "usart0_clk", .id = 12, .r = { .min = 0, .max = 83000000 }, },
0068 { .n = "usart1_clk", .id = 13, .r = { .min = 0, .max = 83000000 }, },
0069 { .n = "usart2_clk", .id = 14, .r = { .min = 0, .max = 83000000 }, },
0070 { .n = "usart3_clk", .id = 15, .r = { .min = 0, .max = 83000000 }, },
0071 { .n = "uart0_clk", .id = 16, .r = { .min = 0, .max = 83000000 }, },
0072 { .n = "uart1_clk", .id = 17, .r = { .min = 0, .max = 83000000 }, },
0073 { .n = "twi0_clk", .id = 18, .r = { .min = 0, .max = 41500000 }, },
0074 { .n = "twi1_clk", .id = 19, .r = { .min = 0, .max = 41500000 }, },
0075 { .n = "twi2_clk", .id = 20, .r = { .min = 0, .max = 41500000 }, },
0076 { .n = "mci0_clk", .id = 21, },
0077 { .n = "mci1_clk", .id = 22, },
0078 { .n = "mci2_clk", .id = 23, },
0079 { .n = "spi0_clk", .id = 24, .r = { .min = 0, .max = 166000000 }, },
0080 { .n = "spi1_clk", .id = 25, .r = { .min = 0, .max = 166000000 }, },
0081 { .n = "tcb0_clk", .id = 26, .r = { .min = 0, .max = 166000000 }, },
0082 { .n = "tcb1_clk", .id = 27, .r = { .min = 0, .max = 166000000 }, },
0083 { .n = "pwm_clk", .id = 28, },
0084 { .n = "adc_clk", .id = 29, .r = { .min = 0, .max = 83000000 }, },
0085 { .n = "dma0_clk", .id = 30, },
0086 { .n = "dma1_clk", .id = 31, },
0087 { .n = "uhphs_clk", .id = 32, },
0088 { .n = "udphs_clk", .id = 33, },
0089 { .n = "macb0_clk", .id = 34, },
0090 { .n = "macb1_clk", .id = 35, },
0091 { .n = "lcdc_clk", .id = 36, },
0092 { .n = "isi_clk", .id = 37, },
0093 { .n = "ssc0_clk", .id = 38, .r = { .min = 0, .max = 83000000 }, },
0094 { .n = "ssc1_clk", .id = 39, .r = { .min = 0, .max = 83000000 }, },
0095 { .n = "can0_clk", .id = 40, .r = { .min = 0, .max = 83000000 }, },
0096 { .n = "can1_clk", .id = 41, .r = { .min = 0, .max = 83000000 }, },
0097 { .n = "sha_clk", .id = 42, },
0098 { .n = "aes_clk", .id = 43, },
0099 { .n = "tdes_clk", .id = 44, },
0100 { .n = "trng_clk", .id = 45, },
0101 { .n = "fuse_clk", .id = 48, },
0102 { .n = "mpddr_clk", .id = 49, },
0103 };
0104
0105 static void __init sama5d3_pmc_setup(struct device_node *np)
0106 {
0107 const char *slck_name, *mainxtal_name;
0108 struct pmc_data *sama5d3_pmc;
0109 const char *parent_names[5];
0110 struct regmap *regmap;
0111 struct clk_hw *hw;
0112 int i;
0113 bool bypass;
0114
0115 i = of_property_match_string(np, "clock-names", "slow_clk");
0116 if (i < 0)
0117 return;
0118
0119 slck_name = of_clk_get_parent_name(np, i);
0120
0121 i = of_property_match_string(np, "clock-names", "main_xtal");
0122 if (i < 0)
0123 return;
0124 mainxtal_name = of_clk_get_parent_name(np, i);
0125
0126 regmap = device_node_to_regmap(np);
0127 if (IS_ERR(regmap))
0128 return;
0129
0130 sama5d3_pmc = pmc_data_allocate(PMC_PLLACK + 1,
0131 nck(sama5d3_systemck),
0132 nck(sama5d3_periphck), 0, 3);
0133 if (!sama5d3_pmc)
0134 return;
0135
0136 hw = at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000,
0137 50000000);
0138 if (IS_ERR(hw))
0139 goto err_free;
0140
0141 bypass = of_property_read_bool(np, "atmel,osc-bypass");
0142
0143 hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name,
0144 bypass);
0145 if (IS_ERR(hw))
0146 goto err_free;
0147
0148 parent_names[0] = "main_rc_osc";
0149 parent_names[1] = "main_osc";
0150 hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, 2);
0151 if (IS_ERR(hw))
0152 goto err_free;
0153
0154 hw = at91_clk_register_pll(regmap, "pllack", "mainck", 0,
0155 &sama5d3_pll_layout, &plla_characteristics);
0156 if (IS_ERR(hw))
0157 goto err_free;
0158
0159 hw = at91_clk_register_plldiv(regmap, "plladivck", "pllack");
0160 if (IS_ERR(hw))
0161 goto err_free;
0162
0163 sama5d3_pmc->chws[PMC_PLLACK] = hw;
0164
0165 hw = at91_clk_register_utmi(regmap, NULL, "utmick", "mainck");
0166 if (IS_ERR(hw))
0167 goto err_free;
0168
0169 sama5d3_pmc->chws[PMC_UTMI] = hw;
0170
0171 parent_names[0] = slck_name;
0172 parent_names[1] = "mainck";
0173 parent_names[2] = "plladivck";
0174 parent_names[3] = "utmick";
0175 hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4,
0176 parent_names,
0177 &at91sam9x5_master_layout,
0178 &mck_characteristics, &mck_lock);
0179 if (IS_ERR(hw))
0180 goto err_free;
0181
0182 hw = at91_clk_register_master_div(regmap, "masterck_div",
0183 "masterck_pres",
0184 &at91sam9x5_master_layout,
0185 &mck_characteristics, &mck_lock,
0186 CLK_SET_RATE_GATE, 0);
0187 if (IS_ERR(hw))
0188 goto err_free;
0189
0190 sama5d3_pmc->chws[PMC_MCK] = hw;
0191
0192 parent_names[0] = "plladivck";
0193 parent_names[1] = "utmick";
0194 hw = at91sam9x5_clk_register_usb(regmap, "usbck", parent_names, 2);
0195 if (IS_ERR(hw))
0196 goto err_free;
0197
0198 hw = at91sam9x5_clk_register_smd(regmap, "smdclk", parent_names, 2);
0199 if (IS_ERR(hw))
0200 goto err_free;
0201
0202 parent_names[0] = slck_name;
0203 parent_names[1] = "mainck";
0204 parent_names[2] = "plladivck";
0205 parent_names[3] = "utmick";
0206 parent_names[4] = "masterck_div";
0207 for (i = 0; i < 3; i++) {
0208 char name[6];
0209
0210 snprintf(name, sizeof(name), "prog%d", i);
0211
0212 hw = at91_clk_register_programmable(regmap, name,
0213 parent_names, 5, i,
0214 &at91sam9x5_programmable_layout,
0215 NULL);
0216 if (IS_ERR(hw))
0217 goto err_free;
0218
0219 sama5d3_pmc->pchws[i] = hw;
0220 }
0221
0222 for (i = 0; i < ARRAY_SIZE(sama5d3_systemck); i++) {
0223 hw = at91_clk_register_system(regmap, sama5d3_systemck[i].n,
0224 sama5d3_systemck[i].p,
0225 sama5d3_systemck[i].id);
0226 if (IS_ERR(hw))
0227 goto err_free;
0228
0229 sama5d3_pmc->shws[sama5d3_systemck[i].id] = hw;
0230 }
0231
0232 for (i = 0; i < ARRAY_SIZE(sama5d3_periphck); i++) {
0233 hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
0234 &sama5d3_pcr_layout,
0235 sama5d3_periphck[i].n,
0236 "masterck_div",
0237 sama5d3_periphck[i].id,
0238 &sama5d3_periphck[i].r,
0239 INT_MIN);
0240 if (IS_ERR(hw))
0241 goto err_free;
0242
0243 sama5d3_pmc->phws[sama5d3_periphck[i].id] = hw;
0244 }
0245
0246 of_clk_add_hw_provider(np, of_clk_hw_pmc_get, sama5d3_pmc);
0247
0248 return;
0249
0250 err_free:
0251 kfree(sama5d3_pmc);
0252 }
0253
0254
0255
0256
0257 CLK_OF_DECLARE(sama5d3_pmc, "atmel,sama5d3-pmc", sama5d3_pmc_setup);
