0001
0002 #include <linux/clk-provider.h>
0003 #include <linux/mfd/syscon.h>
0004 #include <linux/slab.h>
0005
0006 #include <dt-bindings/clock/at91.h>
0007
0008 #include "pmc.h"
0009
0010 static DEFINE_SPINLOCK(mck_lock);
0011
0012 static const struct clk_master_characteristics mck_characteristics = {
0013 .output = { .min = 124000000, .max = 166000000 },
0014 .divisors = { 1, 2, 4, 3 },
0015 };
0016
0017 static u8 plla_out[] = { 0 };
0018
0019 static u16 plla_icpll[] = { 0 };
0020
0021 static const struct clk_range plla_outputs[] = {
0022 { .min = 600000000, .max = 1200000000 },
0023 };
0024
0025 static const struct clk_pll_characteristics plla_characteristics = {
0026 .input = { .min = 12000000, .max = 24000000 },
0027 .num_output = ARRAY_SIZE(plla_outputs),
0028 .output = plla_outputs,
0029 .icpll = plla_icpll,
0030 .out = plla_out,
0031 };
0032
0033 static const struct clk_pcr_layout sama5d2_pcr_layout = {
0034 .offset = 0x10c,
0035 .cmd = BIT(12),
0036 .gckcss_mask = GENMASK(10, 8),
0037 .pid_mask = GENMASK(6, 0),
0038 };
0039
0040 static const struct {
0041 char *n;
0042 char *p;
0043 u8 id;
0044 } sama5d2_systemck[] = {
0045 { .n = "ddrck", .p = "masterck_div", .id = 2 },
0046 { .n = "lcdck", .p = "masterck_div", .id = 3 },
0047 { .n = "uhpck", .p = "usbck", .id = 6 },
0048 { .n = "udpck", .p = "usbck", .id = 7 },
0049 { .n = "pck0", .p = "prog0", .id = 8 },
0050 { .n = "pck1", .p = "prog1", .id = 9 },
0051 { .n = "pck2", .p = "prog2", .id = 10 },
0052 { .n = "iscck", .p = "masterck_div", .id = 18 },
0053 };
0054
0055 static const struct {
0056 char *n;
0057 u8 id;
0058 struct clk_range r;
0059 } sama5d2_periph32ck[] = {
0060 { .n = "macb0_clk", .id = 5, .r = { .min = 0, .max = 83000000 }, },
0061 { .n = "tdes_clk", .id = 11, .r = { .min = 0, .max = 83000000 }, },
0062 { .n = "matrix1_clk", .id = 14, },
0063 { .n = "hsmc_clk", .id = 17, },
0064 { .n = "pioA_clk", .id = 18, .r = { .min = 0, .max = 83000000 }, },
0065 { .n = "flx0_clk", .id = 19, .r = { .min = 0, .max = 83000000 }, },
0066 { .n = "flx1_clk", .id = 20, .r = { .min = 0, .max = 83000000 }, },
0067 { .n = "flx2_clk", .id = 21, .r = { .min = 0, .max = 83000000 }, },
0068 { .n = "flx3_clk", .id = 22, .r = { .min = 0, .max = 83000000 }, },
0069 { .n = "flx4_clk", .id = 23, .r = { .min = 0, .max = 83000000 }, },
0070 { .n = "uart0_clk", .id = 24, .r = { .min = 0, .max = 83000000 }, },
0071 { .n = "uart1_clk", .id = 25, .r = { .min = 0, .max = 83000000 }, },
0072 { .n = "uart2_clk", .id = 26, .r = { .min = 0, .max = 83000000 }, },
0073 { .n = "uart3_clk", .id = 27, .r = { .min = 0, .max = 83000000 }, },
0074 { .n = "uart4_clk", .id = 28, .r = { .min = 0, .max = 83000000 }, },
0075 { .n = "twi0_clk", .id = 29, .r = { .min = 0, .max = 83000000 }, },
0076 { .n = "twi1_clk", .id = 30, .r = { .min = 0, .max = 83000000 }, },
0077 { .n = "spi0_clk", .id = 33, .r = { .min = 0, .max = 83000000 }, },
0078 { .n = "spi1_clk", .id = 34, .r = { .min = 0, .max = 83000000 }, },
0079 { .n = "tcb0_clk", .id = 35, .r = { .min = 0, .max = 83000000 }, },
0080 { .n = "tcb1_clk", .id = 36, .r = { .min = 0, .max = 83000000 }, },
0081 { .n = "pwm_clk", .id = 38, .r = { .min = 0, .max = 83000000 }, },
0082 { .n = "adc_clk", .id = 40, .r = { .min = 0, .max = 83000000 }, },
0083 { .n = "uhphs_clk", .id = 41, .r = { .min = 0, .max = 83000000 }, },
0084 { .n = "udphs_clk", .id = 42, .r = { .min = 0, .max = 83000000 }, },
0085 { .n = "ssc0_clk", .id = 43, .r = { .min = 0, .max = 83000000 }, },
0086 { .n = "ssc1_clk", .id = 44, .r = { .min = 0, .max = 83000000 }, },
0087 { .n = "trng_clk", .id = 47, .r = { .min = 0, .max = 83000000 }, },
0088 { .n = "pdmic_clk", .id = 48, .r = { .min = 0, .max = 83000000 }, },
0089 { .n = "securam_clk", .id = 51, },
0090 { .n = "i2s0_clk", .id = 54, .r = { .min = 0, .max = 83000000 }, },
0091 { .n = "i2s1_clk", .id = 55, .r = { .min = 0, .max = 83000000 }, },
0092 { .n = "can0_clk", .id = 56, .r = { .min = 0, .max = 83000000 }, },
0093 { .n = "can1_clk", .id = 57, .r = { .min = 0, .max = 83000000 }, },
0094 { .n = "ptc_clk", .id = 58, .r = { .min = 0, .max = 83000000 }, },
0095 { .n = "classd_clk", .id = 59, .r = { .min = 0, .max = 83000000 }, },
0096 };
0097
0098 static const struct {
0099 char *n;
0100 u8 id;
0101 } sama5d2_periphck[] = {
0102 { .n = "dma0_clk", .id = 6, },
0103 { .n = "dma1_clk", .id = 7, },
0104 { .n = "aes_clk", .id = 9, },
0105 { .n = "aesb_clk", .id = 10, },
0106 { .n = "sha_clk", .id = 12, },
0107 { .n = "mpddr_clk", .id = 13, },
0108 { .n = "matrix0_clk", .id = 15, },
0109 { .n = "sdmmc0_hclk", .id = 31, },
0110 { .n = "sdmmc1_hclk", .id = 32, },
0111 { .n = "lcdc_clk", .id = 45, },
0112 { .n = "isc_clk", .id = 46, },
0113 { .n = "qspi0_clk", .id = 52, },
0114 { .n = "qspi1_clk", .id = 53, },
0115 };
0116
0117 static const struct {
0118 char *n;
0119 u8 id;
0120 struct clk_range r;
0121 int chg_pid;
0122 } sama5d2_gck[] = {
0123 { .n = "sdmmc0_gclk", .id = 31, .chg_pid = INT_MIN, },
0124 { .n = "sdmmc1_gclk", .id = 32, .chg_pid = INT_MIN, },
0125 { .n = "tcb0_gclk", .id = 35, .chg_pid = INT_MIN, .r = { .min = 0, .max = 83000000 }, },
0126 { .n = "tcb1_gclk", .id = 36, .chg_pid = INT_MIN, .r = { .min = 0, .max = 83000000 }, },
0127 { .n = "pwm_gclk", .id = 38, .chg_pid = INT_MIN, .r = { .min = 0, .max = 83000000 }, },
0128 { .n = "isc_gclk", .id = 46, .chg_pid = INT_MIN, },
0129 { .n = "pdmic_gclk", .id = 48, .chg_pid = INT_MIN, },
0130 { .n = "i2s0_gclk", .id = 54, .chg_pid = 5, },
0131 { .n = "i2s1_gclk", .id = 55, .chg_pid = 5, },
0132 { .n = "can0_gclk", .id = 56, .chg_pid = INT_MIN, .r = { .min = 0, .max = 80000000 }, },
0133 { .n = "can1_gclk", .id = 57, .chg_pid = INT_MIN, .r = { .min = 0, .max = 80000000 }, },
0134 { .n = "classd_gclk", .id = 59, .chg_pid = 5, .r = { .min = 0, .max = 100000000 }, },
0135 };
0136
0137 static const struct clk_programmable_layout sama5d2_programmable_layout = {
0138 .pres_mask = 0xff,
0139 .pres_shift = 4,
0140 .css_mask = 0x7,
0141 .have_slck_mck = 0,
0142 .is_pres_direct = 1,
0143 };
0144
0145 static void __init sama5d2_pmc_setup(struct device_node *np)
0146 {
0147 struct clk_range range = CLK_RANGE(0, 0);
0148 const char *slck_name, *mainxtal_name;
0149 struct pmc_data *sama5d2_pmc;
0150 const char *parent_names[6];
0151 struct regmap *regmap, *regmap_sfr;
0152 struct clk_hw *hw;
0153 int i;
0154 bool bypass;
0155
0156 i = of_property_match_string(np, "clock-names", "slow_clk");
0157 if (i < 0)
0158 return;
0159
0160 slck_name = of_clk_get_parent_name(np, i);
0161
0162 i = of_property_match_string(np, "clock-names", "main_xtal");
0163 if (i < 0)
0164 return;
0165 mainxtal_name = of_clk_get_parent_name(np, i);
0166
0167 regmap = device_node_to_regmap(np);
0168 if (IS_ERR(regmap))
0169 return;
0170
0171 sama5d2_pmc = pmc_data_allocate(PMC_AUDIOPINCK + 1,
0172 nck(sama5d2_systemck),
0173 nck(sama5d2_periph32ck),
0174 nck(sama5d2_gck), 3);
0175 if (!sama5d2_pmc)
0176 return;
0177
0178 hw = at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000,
0179 100000000);
0180 if (IS_ERR(hw))
0181 goto err_free;
0182
0183 bypass = of_property_read_bool(np, "atmel,osc-bypass");
0184
0185 hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name,
0186 bypass);
0187 if (IS_ERR(hw))
0188 goto err_free;
0189
0190 parent_names[0] = "main_rc_osc";
0191 parent_names[1] = "main_osc";
0192 hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, 2);
0193 if (IS_ERR(hw))
0194 goto err_free;
0195
0196 sama5d2_pmc->chws[PMC_MAIN] = hw;
0197
0198 hw = at91_clk_register_pll(regmap, "pllack", "mainck", 0,
0199 &sama5d3_pll_layout, &plla_characteristics);
0200 if (IS_ERR(hw))
0201 goto err_free;
0202
0203 hw = at91_clk_register_plldiv(regmap, "plladivck", "pllack");
0204 if (IS_ERR(hw))
0205 goto err_free;
0206
0207 sama5d2_pmc->chws[PMC_PLLACK] = hw;
0208
0209 hw = at91_clk_register_audio_pll_frac(regmap, "audiopll_fracck",
0210 "mainck");
0211 if (IS_ERR(hw))
0212 goto err_free;
0213
0214 hw = at91_clk_register_audio_pll_pad(regmap, "audiopll_padck",
0215 "audiopll_fracck");
0216 if (IS_ERR(hw))
0217 goto err_free;
0218
0219 sama5d2_pmc->chws[PMC_AUDIOPINCK] = hw;
0220
0221 hw = at91_clk_register_audio_pll_pmc(regmap, "audiopll_pmcck",
0222 "audiopll_fracck");
0223 if (IS_ERR(hw))
0224 goto err_free;
0225
0226 sama5d2_pmc->chws[PMC_AUDIOPLLCK] = hw;
0227
0228 regmap_sfr = syscon_regmap_lookup_by_compatible("atmel,sama5d2-sfr");
0229 if (IS_ERR(regmap_sfr))
0230 regmap_sfr = NULL;
0231
0232 hw = at91_clk_register_utmi(regmap, regmap_sfr, "utmick", "mainck");
0233 if (IS_ERR(hw))
0234 goto err_free;
0235
0236 sama5d2_pmc->chws[PMC_UTMI] = hw;
0237
0238 parent_names[0] = slck_name;
0239 parent_names[1] = "mainck";
0240 parent_names[2] = "plladivck";
0241 parent_names[3] = "utmick";
0242 hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4,
0243 parent_names,
0244 &at91sam9x5_master_layout,
0245 &mck_characteristics, &mck_lock);
0246 if (IS_ERR(hw))
0247 goto err_free;
0248
0249 hw = at91_clk_register_master_div(regmap, "masterck_div",
0250 "masterck_pres",
0251 &at91sam9x5_master_layout,
0252 &mck_characteristics, &mck_lock,
0253 CLK_SET_RATE_GATE, 0);
0254 if (IS_ERR(hw))
0255 goto err_free;
0256
0257 sama5d2_pmc->chws[PMC_MCK] = hw;
0258
0259 hw = at91_clk_register_h32mx(regmap, "h32mxck", "masterck_div");
0260 if (IS_ERR(hw))
0261 goto err_free;
0262
0263 sama5d2_pmc->chws[PMC_MCK2] = hw;
0264
0265 parent_names[0] = "plladivck";
0266 parent_names[1] = "utmick";
0267 hw = at91sam9x5_clk_register_usb(regmap, "usbck", parent_names, 2);
0268 if (IS_ERR(hw))
0269 goto err_free;
0270
0271 parent_names[0] = slck_name;
0272 parent_names[1] = "mainck";
0273 parent_names[2] = "plladivck";
0274 parent_names[3] = "utmick";
0275 parent_names[4] = "masterck_div";
0276 parent_names[5] = "audiopll_pmcck";
0277 for (i = 0; i < 3; i++) {
0278 char name[6];
0279
0280 snprintf(name, sizeof(name), "prog%d", i);
0281
0282 hw = at91_clk_register_programmable(regmap, name,
0283 parent_names, 6, i,
0284 &sama5d2_programmable_layout,
0285 NULL);
0286 if (IS_ERR(hw))
0287 goto err_free;
0288
0289 sama5d2_pmc->pchws[i] = hw;
0290 }
0291
0292 for (i = 0; i < ARRAY_SIZE(sama5d2_systemck); i++) {
0293 hw = at91_clk_register_system(regmap, sama5d2_systemck[i].n,
0294 sama5d2_systemck[i].p,
0295 sama5d2_systemck[i].id);
0296 if (IS_ERR(hw))
0297 goto err_free;
0298
0299 sama5d2_pmc->shws[sama5d2_systemck[i].id] = hw;
0300 }
0301
0302 for (i = 0; i < ARRAY_SIZE(sama5d2_periphck); i++) {
0303 hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
0304 &sama5d2_pcr_layout,
0305 sama5d2_periphck[i].n,
0306 "masterck_div",
0307 sama5d2_periphck[i].id,
0308 &range, INT_MIN);
0309 if (IS_ERR(hw))
0310 goto err_free;
0311
0312 sama5d2_pmc->phws[sama5d2_periphck[i].id] = hw;
0313 }
0314
0315 for (i = 0; i < ARRAY_SIZE(sama5d2_periph32ck); i++) {
0316 hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
0317 &sama5d2_pcr_layout,
0318 sama5d2_periph32ck[i].n,
0319 "h32mxck",
0320 sama5d2_periph32ck[i].id,
0321 &sama5d2_periph32ck[i].r,
0322 INT_MIN);
0323 if (IS_ERR(hw))
0324 goto err_free;
0325
0326 sama5d2_pmc->phws[sama5d2_periph32ck[i].id] = hw;
0327 }
0328
0329 parent_names[0] = slck_name;
0330 parent_names[1] = "mainck";
0331 parent_names[2] = "plladivck";
0332 parent_names[3] = "utmick";
0333 parent_names[4] = "masterck_div";
0334 parent_names[5] = "audiopll_pmcck";
0335 for (i = 0; i < ARRAY_SIZE(sama5d2_gck); i++) {
0336 hw = at91_clk_register_generated(regmap, &pmc_pcr_lock,
0337 &sama5d2_pcr_layout,
0338 sama5d2_gck[i].n,
0339 parent_names, NULL, 6,
0340 sama5d2_gck[i].id,
0341 &sama5d2_gck[i].r,
0342 sama5d2_gck[i].chg_pid);
0343 if (IS_ERR(hw))
0344 goto err_free;
0345
0346 sama5d2_pmc->ghws[sama5d2_gck[i].id] = hw;
0347 }
0348
0349 if (regmap_sfr) {
0350 parent_names[0] = "i2s0_clk";
0351 parent_names[1] = "i2s0_gclk";
0352 hw = at91_clk_i2s_mux_register(regmap_sfr, "i2s0_muxclk",
0353 parent_names, 2, 0);
0354 if (IS_ERR(hw))
0355 goto err_free;
0356
0357 sama5d2_pmc->chws[PMC_I2S0_MUX] = hw;
0358
0359 parent_names[0] = "i2s1_clk";
0360 parent_names[1] = "i2s1_gclk";
0361 hw = at91_clk_i2s_mux_register(regmap_sfr, "i2s1_muxclk",
0362 parent_names, 2, 1);
0363 if (IS_ERR(hw))
0364 goto err_free;
0365
0366 sama5d2_pmc->chws[PMC_I2S1_MUX] = hw;
0367 }
0368
0369 of_clk_add_hw_provider(np, of_clk_hw_pmc_get, sama5d2_pmc);
0370
0371 return;
0372
0373 err_free:
0374 kfree(sama5d2_pmc);
0375 }
0376
0377 CLK_OF_DECLARE(sama5d2_pmc, "atmel,sama5d2-pmc", sama5d2_pmc_setup);
