clk/at91/pmc.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * drivers/clk/at91/pmc.h
0004  *
0005  *  Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
0006  */
0007
0008 #ifndef __PMC_H_
0009 #define __PMC_H_
0010
0011 #include <linux/io.h>
0012 #include <linux/irqdomain.h>
0013 #include <linux/regmap.h>
0014 #include <linux/spinlock.h>
0015
0016 #include <dt-bindings/clock/at91.h>
0017
0018 extern spinlock_t pmc_pcr_lock;
0019
0020 struct pmc_data {
0021     unsigned int ncore;
0022     struct clk_hw **chws;
0023     unsigned int nsystem;
0024     struct clk_hw **shws;
0025     unsigned int nperiph;
0026     struct clk_hw **phws;
0027     unsigned int ngck;
0028     struct clk_hw **ghws;
0029     unsigned int npck;
0030     struct clk_hw **pchws;
0031
0032     struct clk_hw *hwtable[];
0033 };
0034
0035 struct clk_range {
0036     unsigned long min;
0037     unsigned long max;
0038 };
0039
0040 #define CLK_RANGE(MIN, MAX) {.min = MIN, .max = MAX,}
0041
0042 struct clk_master_layout {
0043     u32 offset;
0044     u32 mask;
0045     u8 pres_shift;
0046 };
0047
0048 extern const struct clk_master_layout at91rm9200_master_layout;
0049 extern const struct clk_master_layout at91sam9x5_master_layout;
0050
0051 struct clk_master_characteristics {
0052     struct clk_range output;
0053     u32 divisors[5];
0054     u8 have_div3_pres;
0055 };
0056
0057 struct clk_pll_layout {
0058     u32 pllr_mask;
0059     u32 mul_mask;
0060     u32 frac_mask;
0061     u32 div_mask;
0062     u32 endiv_mask;
0063     u8 mul_shift;
0064     u8 frac_shift;
0065     u8 div_shift;
0066     u8 endiv_shift;
0067 };
0068
0069 extern const struct clk_pll_layout at91rm9200_pll_layout;
0070 extern const struct clk_pll_layout at91sam9g45_pll_layout;
0071 extern const struct clk_pll_layout at91sam9g20_pllb_layout;
0072 extern const struct clk_pll_layout sama5d3_pll_layout;
0073
0074 struct clk_pll_characteristics {
0075     struct clk_range input;
0076     int num_output;
0077     const struct clk_range *output;
0078     u16 *icpll;
0079     u8 *out;
0080     u8 upll : 1;
0081 };
0082
0083 struct clk_programmable_layout {
0084     u8 pres_mask;
0085     u8 pres_shift;
0086     u8 css_mask;
0087     u8 have_slck_mck;
0088     u8 is_pres_direct;
0089 };
0090
0091 extern const struct clk_programmable_layout at91rm9200_programmable_layout;
0092 extern const struct clk_programmable_layout at91sam9g45_programmable_layout;
0093 extern const struct clk_programmable_layout at91sam9x5_programmable_layout;
0094
0095 struct clk_pcr_layout {
0096     u32 offset;
0097     u32 cmd;
0098     u32 div_mask;
0099     u32 gckcss_mask;
0100     u32 pid_mask;
0101 };
0102
0103 /**
0104  * struct at91_clk_pms - Power management state for AT91 clock
0105  * @rate: clock rate
0106  * @parent_rate: clock parent rate
0107  * @status: clock status (enabled or disabled)
0108  * @parent: clock parent index
0109  */
0110 struct at91_clk_pms {
0111     unsigned long rate;
0112     unsigned long parent_rate;
0113     unsigned int status;
0114     unsigned int parent;
0115 };
0116
0117 #define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1))
0118 #define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask))
0119
0120 #define ndck(a, s) (a[s - 1].id + 1)
0121 #define nck(a) (a[ARRAY_SIZE(a) - 1].id + 1)
0122 struct pmc_data *pmc_data_allocate(unsigned int ncore, unsigned int nsystem,
0123                    unsigned int nperiph, unsigned int ngck,
0124                    unsigned int npck);
0125
0126 int of_at91_get_clk_range(struct device_node *np, const char *propname,
0127               struct clk_range *range);
0128
0129 struct clk_hw *of_clk_hw_pmc_get(struct of_phandle_args *clkspec, void *data);
0130
0131 struct clk_hw * __init
0132 at91_clk_register_audio_pll_frac(struct regmap *regmap, const char *name,
0133                  const char *parent_name);
0134
0135 struct clk_hw * __init
0136 at91_clk_register_audio_pll_pad(struct regmap *regmap, const char *name,
0137                 const char *parent_name);
0138
0139 struct clk_hw * __init
0140 at91_clk_register_audio_pll_pmc(struct regmap *regmap, const char *name,
0141                 const char *parent_name);
0142
0143 struct clk_hw * __init
0144 at91_clk_register_generated(struct regmap *regmap, spinlock_t *lock,
0145                 const struct clk_pcr_layout *layout,
0146                 const char *name, const char **parent_names,
0147                 u32 *mux_table, u8 num_parents, u8 id,
0148                 const struct clk_range *range, int chg_pid);
0149
0150 struct clk_hw * __init
0151 at91_clk_register_h32mx(struct regmap *regmap, const char *name,
0152             const char *parent_name);
0153
0154 struct clk_hw * __init
0155 at91_clk_i2s_mux_register(struct regmap *regmap, const char *name,
0156               const char * const *parent_names,
0157               unsigned int num_parents, u8 bus_id);
0158
0159 struct clk_hw * __init
0160 at91_clk_register_main_rc_osc(struct regmap *regmap, const char *name,
0161                   u32 frequency, u32 accuracy);
0162 struct clk_hw * __init
0163 at91_clk_register_main_osc(struct regmap *regmap, const char *name,
0164                const char *parent_name, bool bypass);
0165 struct clk_hw * __init
0166 at91_clk_register_rm9200_main(struct regmap *regmap,
0167                   const char *name,
0168                   const char *parent_name);
0169 struct clk_hw * __init
0170 at91_clk_register_sam9x5_main(struct regmap *regmap, const char *name,
0171                   const char **parent_names, int num_parents);
0172
0173 struct clk_hw * __init
0174 at91_clk_register_master_pres(struct regmap *regmap, const char *name,
0175                   int num_parents, const char **parent_names,
0176                   const struct clk_master_layout *layout,
0177                   const struct clk_master_characteristics *characteristics,
0178                   spinlock_t *lock);
0179
0180 struct clk_hw * __init
0181 at91_clk_register_master_div(struct regmap *regmap, const char *name,
0182                  const char *parent_names,
0183                  const struct clk_master_layout *layout,
0184                  const struct clk_master_characteristics *characteristics,
0185                  spinlock_t *lock, u32 flags, u32 safe_div);
0186
0187 struct clk_hw * __init
0188 at91_clk_sama7g5_register_master(struct regmap *regmap,
0189                  const char *name, int num_parents,
0190                  const char **parent_names, u32 *mux_table,
0191                  spinlock_t *lock, u8 id, bool critical,
0192                  int chg_pid);
0193
0194 struct clk_hw * __init
0195 at91_clk_register_peripheral(struct regmap *regmap, const char *name,
0196                  const char *parent_name, u32 id);
0197 struct clk_hw * __init
0198 at91_clk_register_sam9x5_peripheral(struct regmap *regmap, spinlock_t *lock,
0199                     const struct clk_pcr_layout *layout,
0200                     const char *name, const char *parent_name,
0201                     u32 id, const struct clk_range *range,
0202                     int chg_pid);
0203
0204 struct clk_hw * __init
0205 at91_clk_register_pll(struct regmap *regmap, const char *name,
0206               const char *parent_name, u8 id,
0207               const struct clk_pll_layout *layout,
0208               const struct clk_pll_characteristics *characteristics);
0209 struct clk_hw * __init
0210 at91_clk_register_plldiv(struct regmap *regmap, const char *name,
0211              const char *parent_name);
0212
0213 struct clk_hw * __init
0214 sam9x60_clk_register_div_pll(struct regmap *regmap, spinlock_t *lock,
0215                  const char *name, const char *parent_name, u8 id,
0216                  const struct clk_pll_characteristics *characteristics,
0217                  const struct clk_pll_layout *layout, u32 flags,
0218                  u32 safe_div);
0219
0220 struct clk_hw * __init
0221 sam9x60_clk_register_frac_pll(struct regmap *regmap, spinlock_t *lock,
0222                   const char *name, const char *parent_name,
0223                   struct clk_hw *parent_hw, u8 id,
0224                   const struct clk_pll_characteristics *characteristics,
0225                   const struct clk_pll_layout *layout, u32 flags);
0226
0227 struct clk_hw * __init
0228 at91_clk_register_programmable(struct regmap *regmap, const char *name,
0229                    const char **parent_names, u8 num_parents, u8 id,
0230                    const struct clk_programmable_layout *layout,
0231                    u32 *mux_table);
0232
0233 struct clk_hw * __init
0234 at91_clk_register_sam9260_slow(struct regmap *regmap,
0235                    const char *name,
0236                    const char **parent_names,
0237                    int num_parents);
0238
0239 struct clk_hw * __init
0240 at91sam9x5_clk_register_smd(struct regmap *regmap, const char *name,
0241                 const char **parent_names, u8 num_parents);
0242
0243 struct clk_hw * __init
0244 at91_clk_register_system(struct regmap *regmap, const char *name,
0245              const char *parent_name, u8 id);
0246
0247 struct clk_hw * __init
0248 at91sam9x5_clk_register_usb(struct regmap *regmap, const char *name,
0249                 const char **parent_names, u8 num_parents);
0250 struct clk_hw * __init
0251 at91sam9n12_clk_register_usb(struct regmap *regmap, const char *name,
0252                  const char *parent_name);
0253 struct clk_hw * __init
0254 sam9x60_clk_register_usb(struct regmap *regmap, const char *name,
0255              const char **parent_names, u8 num_parents);
0256 struct clk_hw * __init
0257 at91rm9200_clk_register_usb(struct regmap *regmap, const char *name,
0258                 const char *parent_name, const u32 *divisors);
0259
0260 struct clk_hw * __init
0261 at91_clk_register_utmi(struct regmap *regmap_pmc, struct regmap *regmap_sfr,
0262                const char *name, const char *parent_name);
0263
0264 struct clk_hw * __init
0265 at91_clk_sama7g5_register_utmi(struct regmap *regmap, const char *name,
0266                    const char *parent_name);
0267
0268 #endif /* __PMC_H_ */