clk/at91/clk-plldiv.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  *  Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
0004  */
0005
0006 #include <linux/clk-provider.h>
0007 #include <linux/clkdev.h>
0008 #include <linux/clk/at91_pmc.h>
0009 #include <linux/of.h>
0010 #include <linux/mfd/syscon.h>
0011 #include <linux/regmap.h>
0012
0013 #include "pmc.h"
0014
0015 #define to_clk_plldiv(hw) container_of(hw, struct clk_plldiv, hw)
0016
0017 struct clk_plldiv {
0018     struct clk_hw hw;
0019     struct regmap *regmap;
0020 };
0021
0022 static unsigned long clk_plldiv_recalc_rate(struct clk_hw *hw,
0023                         unsigned long parent_rate)
0024 {
0025     struct clk_plldiv *plldiv = to_clk_plldiv(hw);
0026     unsigned int mckr;
0027
0028     regmap_read(plldiv->regmap, AT91_PMC_MCKR, &mckr);
0029
0030     if (mckr & AT91_PMC_PLLADIV2)
0031         return parent_rate / 2;
0032
0033     return parent_rate;
0034 }
0035
0036 static long clk_plldiv_round_rate(struct clk_hw *hw, unsigned long rate,
0037                     unsigned long *parent_rate)
0038 {
0039     unsigned long div;
0040
0041     if (rate > *parent_rate)
0042         return *parent_rate;
0043     div = *parent_rate / 2;
0044     if (rate < div)
0045         return div;
0046
0047     if (rate - div < *parent_rate - rate)
0048         return div;
0049
0050     return *parent_rate;
0051 }
0052
0053 static int clk_plldiv_set_rate(struct clk_hw *hw, unsigned long rate,
0054                    unsigned long parent_rate)
0055 {
0056     struct clk_plldiv *plldiv = to_clk_plldiv(hw);
0057
0058     if ((parent_rate != rate) && (parent_rate / 2 != rate))
0059         return -EINVAL;
0060
0061     regmap_update_bits(plldiv->regmap, AT91_PMC_MCKR, AT91_PMC_PLLADIV2,
0062                parent_rate != rate ? AT91_PMC_PLLADIV2 : 0);
0063
0064     return 0;
0065 }
0066
0067 static const struct clk_ops plldiv_ops = {
0068     .recalc_rate = clk_plldiv_recalc_rate,
0069     .round_rate = clk_plldiv_round_rate,
0070     .set_rate = clk_plldiv_set_rate,
0071 };
0072
0073 struct clk_hw * __init
0074 at91_clk_register_plldiv(struct regmap *regmap, const char *name,
0075              const char *parent_name)
0076 {
0077     struct clk_plldiv *plldiv;
0078     struct clk_hw *hw;
0079     struct clk_init_data init;
0080     int ret;
0081
0082     plldiv = kzalloc(sizeof(*plldiv), GFP_KERNEL);
0083     if (!plldiv)
0084         return ERR_PTR(-ENOMEM);
0085
0086     init.name = name;
0087     init.ops = &plldiv_ops;
0088     init.parent_names = parent_name ? &parent_name : NULL;
0089     init.num_parents = parent_name ? 1 : 0;
0090     init.flags = CLK_SET_RATE_GATE;
0091
0092     plldiv->hw.init = &init;
0093     plldiv->regmap = regmap;
0094
0095     hw = &plldiv->hw;
0096     ret = clk_hw_register(NULL, &plldiv->hw);
0097     if (ret) {
0098         kfree(plldiv);
0099         hw = ERR_PTR(ret);
0100     }
0101
0102     return hw;
0103 }