clk/at91/clk-main.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  *  Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
0004  */
0005
0006 #include <linux/clk-provider.h>
0007 #include <linux/clkdev.h>
0008 #include <linux/clk/at91_pmc.h>
0009 #include <linux/delay.h>
0010 #include <linux/mfd/syscon.h>
0011 #include <linux/regmap.h>
0012
0013 #include "pmc.h"
0014
0015 #define SLOW_CLOCK_FREQ     32768
0016 #define MAINF_DIV       16
0017 #define MAINFRDY_TIMEOUT    (((MAINF_DIV + 1) * USEC_PER_SEC) / \
0018                  SLOW_CLOCK_FREQ)
0019 #define MAINF_LOOP_MIN_WAIT (USEC_PER_SEC / SLOW_CLOCK_FREQ)
0020 #define MAINF_LOOP_MAX_WAIT MAINFRDY_TIMEOUT
0021
0022 #define MOR_KEY_MASK        (0xff << 16)
0023
0024 #define clk_main_parent_select(s)   (((s) & \
0025                     (AT91_PMC_MOSCEN | \
0026                     AT91_PMC_OSCBYPASS)) ? 1 : 0)
0027
0028 struct clk_main_osc {
0029     struct clk_hw hw;
0030     struct regmap *regmap;
0031     struct at91_clk_pms pms;
0032 };
0033
0034 #define to_clk_main_osc(hw) container_of(hw, struct clk_main_osc, hw)
0035
0036 struct clk_main_rc_osc {
0037     struct clk_hw hw;
0038     struct regmap *regmap;
0039     unsigned long frequency;
0040     unsigned long accuracy;
0041     struct at91_clk_pms pms;
0042 };
0043
0044 #define to_clk_main_rc_osc(hw) container_of(hw, struct clk_main_rc_osc, hw)
0045
0046 struct clk_rm9200_main {
0047     struct clk_hw hw;
0048     struct regmap *regmap;
0049 };
0050
0051 #define to_clk_rm9200_main(hw) container_of(hw, struct clk_rm9200_main, hw)
0052
0053 struct clk_sam9x5_main {
0054     struct clk_hw hw;
0055     struct regmap *regmap;
0056     struct at91_clk_pms pms;
0057     u8 parent;
0058 };
0059
0060 #define to_clk_sam9x5_main(hw) container_of(hw, struct clk_sam9x5_main, hw)
0061
0062 static inline bool clk_main_osc_ready(struct regmap *regmap)
0063 {
0064     unsigned int status;
0065
0066     regmap_read(regmap, AT91_PMC_SR, &status);
0067
0068     return status & AT91_PMC_MOSCS;
0069 }
0070
0071 static int clk_main_osc_prepare(struct clk_hw *hw)
0072 {
0073     struct clk_main_osc *osc = to_clk_main_osc(hw);
0074     struct regmap *regmap = osc->regmap;
0075     u32 tmp;
0076
0077     regmap_read(regmap, AT91_CKGR_MOR, &tmp);
0078     tmp &= ~MOR_KEY_MASK;
0079
0080     if (tmp & AT91_PMC_OSCBYPASS)
0081         return 0;
0082
0083     if (!(tmp & AT91_PMC_MOSCEN)) {
0084         tmp |= AT91_PMC_MOSCEN | AT91_PMC_KEY;
0085         regmap_write(regmap, AT91_CKGR_MOR, tmp);
0086     }
0087
0088     while (!clk_main_osc_ready(regmap))
0089         cpu_relax();
0090
0091     return 0;
0092 }
0093
0094 static void clk_main_osc_unprepare(struct clk_hw *hw)
0095 {
0096     struct clk_main_osc *osc = to_clk_main_osc(hw);
0097     struct regmap *regmap = osc->regmap;
0098     u32 tmp;
0099
0100     regmap_read(regmap, AT91_CKGR_MOR, &tmp);
0101     if (tmp & AT91_PMC_OSCBYPASS)
0102         return;
0103
0104     if (!(tmp & AT91_PMC_MOSCEN))
0105         return;
0106
0107     tmp &= ~(AT91_PMC_KEY | AT91_PMC_MOSCEN);
0108     regmap_write(regmap, AT91_CKGR_MOR, tmp | AT91_PMC_KEY);
0109 }
0110
0111 static int clk_main_osc_is_prepared(struct clk_hw *hw)
0112 {
0113     struct clk_main_osc *osc = to_clk_main_osc(hw);
0114     struct regmap *regmap = osc->regmap;
0115     u32 tmp, status;
0116
0117     regmap_read(regmap, AT91_CKGR_MOR, &tmp);
0118     if (tmp & AT91_PMC_OSCBYPASS)
0119         return 1;
0120
0121     regmap_read(regmap, AT91_PMC_SR, &status);
0122
0123     return (status & AT91_PMC_MOSCS) && clk_main_parent_select(tmp);
0124 }
0125
0126 static int clk_main_osc_save_context(struct clk_hw *hw)
0127 {
0128     struct clk_main_osc *osc = to_clk_main_osc(hw);
0129
0130     osc->pms.status = clk_main_osc_is_prepared(hw);
0131
0132     return 0;
0133 }
0134
0135 static void clk_main_osc_restore_context(struct clk_hw *hw)
0136 {
0137     struct clk_main_osc *osc = to_clk_main_osc(hw);
0138
0139     if (osc->pms.status)
0140         clk_main_osc_prepare(hw);
0141 }
0142
0143 static const struct clk_ops main_osc_ops = {
0144     .prepare = clk_main_osc_prepare,
0145     .unprepare = clk_main_osc_unprepare,
0146     .is_prepared = clk_main_osc_is_prepared,
0147     .save_context = clk_main_osc_save_context,
0148     .restore_context = clk_main_osc_restore_context,
0149 };
0150
0151 struct clk_hw * __init
0152 at91_clk_register_main_osc(struct regmap *regmap,
0153                const char *name,
0154                const char *parent_name,
0155                bool bypass)
0156 {
0157     struct clk_main_osc *osc;
0158     struct clk_init_data init;
0159     struct clk_hw *hw;
0160     int ret;
0161
0162     if (!name || !parent_name)
0163         return ERR_PTR(-EINVAL);
0164
0165     osc = kzalloc(sizeof(*osc), GFP_KERNEL);
0166     if (!osc)
0167         return ERR_PTR(-ENOMEM);
0168
0169     init.name = name;
0170     init.ops = &main_osc_ops;
0171     init.parent_names = &parent_name;
0172     init.num_parents = 1;
0173     init.flags = CLK_IGNORE_UNUSED;
0174
0175     osc->hw.init = &init;
0176     osc->regmap = regmap;
0177
0178     if (bypass)
0179         regmap_update_bits(regmap,
0180                    AT91_CKGR_MOR, MOR_KEY_MASK |
0181                    AT91_PMC_OSCBYPASS,
0182                    AT91_PMC_OSCBYPASS | AT91_PMC_KEY);
0183
0184     hw = &osc->hw;
0185     ret = clk_hw_register(NULL, &osc->hw);
0186     if (ret) {
0187         kfree(osc);
0188         hw = ERR_PTR(ret);
0189     }
0190
0191     return hw;
0192 }
0193
0194 static bool clk_main_rc_osc_ready(struct regmap *regmap)
0195 {
0196     unsigned int status;
0197
0198     regmap_read(regmap, AT91_PMC_SR, &status);
0199
0200     return !!(status & AT91_PMC_MOSCRCS);
0201 }
0202
0203 static int clk_main_rc_osc_prepare(struct clk_hw *hw)
0204 {
0205     struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw);
0206     struct regmap *regmap = osc->regmap;
0207     unsigned int mor;
0208
0209     regmap_read(regmap, AT91_CKGR_MOR, &mor);
0210
0211     if (!(mor & AT91_PMC_MOSCRCEN))
0212         regmap_update_bits(regmap, AT91_CKGR_MOR,
0213                    MOR_KEY_MASK | AT91_PMC_MOSCRCEN,
0214                    AT91_PMC_MOSCRCEN | AT91_PMC_KEY);
0215
0216     while (!clk_main_rc_osc_ready(regmap))
0217         cpu_relax();
0218
0219     return 0;
0220 }
0221
0222 static void clk_main_rc_osc_unprepare(struct clk_hw *hw)
0223 {
0224     struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw);
0225     struct regmap *regmap = osc->regmap;
0226     unsigned int mor;
0227
0228     regmap_read(regmap, AT91_CKGR_MOR, &mor);
0229
0230     if (!(mor & AT91_PMC_MOSCRCEN))
0231         return;
0232
0233     regmap_update_bits(regmap, AT91_CKGR_MOR,
0234                MOR_KEY_MASK | AT91_PMC_MOSCRCEN, AT91_PMC_KEY);
0235 }
0236
0237 static int clk_main_rc_osc_is_prepared(struct clk_hw *hw)
0238 {
0239     struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw);
0240     struct regmap *regmap = osc->regmap;
0241     unsigned int mor, status;
0242
0243     regmap_read(regmap, AT91_CKGR_MOR, &mor);
0244     regmap_read(regmap, AT91_PMC_SR, &status);
0245
0246     return (mor & AT91_PMC_MOSCRCEN) && (status & AT91_PMC_MOSCRCS);
0247 }
0248
0249 static unsigned long clk_main_rc_osc_recalc_rate(struct clk_hw *hw,
0250                          unsigned long parent_rate)
0251 {
0252     struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw);
0253
0254     return osc->frequency;
0255 }
0256
0257 static unsigned long clk_main_rc_osc_recalc_accuracy(struct clk_hw *hw,
0258                              unsigned long parent_acc)
0259 {
0260     struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw);
0261
0262     return osc->accuracy;
0263 }
0264
0265 static int clk_main_rc_osc_save_context(struct clk_hw *hw)
0266 {
0267     struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw);
0268
0269     osc->pms.status = clk_main_rc_osc_is_prepared(hw);
0270
0271     return 0;
0272 }
0273
0274 static void clk_main_rc_osc_restore_context(struct clk_hw *hw)
0275 {
0276     struct clk_main_rc_osc *osc = to_clk_main_rc_osc(hw);
0277
0278     if (osc->pms.status)
0279         clk_main_rc_osc_prepare(hw);
0280 }
0281
0282 static const struct clk_ops main_rc_osc_ops = {
0283     .prepare = clk_main_rc_osc_prepare,
0284     .unprepare = clk_main_rc_osc_unprepare,
0285     .is_prepared = clk_main_rc_osc_is_prepared,
0286     .recalc_rate = clk_main_rc_osc_recalc_rate,
0287     .recalc_accuracy = clk_main_rc_osc_recalc_accuracy,
0288     .save_context = clk_main_rc_osc_save_context,
0289     .restore_context = clk_main_rc_osc_restore_context,
0290 };
0291
0292 struct clk_hw * __init
0293 at91_clk_register_main_rc_osc(struct regmap *regmap,
0294                   const char *name,
0295                   u32 frequency, u32 accuracy)
0296 {
0297     struct clk_main_rc_osc *osc;
0298     struct clk_init_data init;
0299     struct clk_hw *hw;
0300     int ret;
0301
0302     if (!name || !frequency)
0303         return ERR_PTR(-EINVAL);
0304
0305     osc = kzalloc(sizeof(*osc), GFP_KERNEL);
0306     if (!osc)
0307         return ERR_PTR(-ENOMEM);
0308
0309     init.name = name;
0310     init.ops = &main_rc_osc_ops;
0311     init.parent_names = NULL;
0312     init.num_parents = 0;
0313     init.flags = CLK_IGNORE_UNUSED;
0314
0315     osc->hw.init = &init;
0316     osc->regmap = regmap;
0317     osc->frequency = frequency;
0318     osc->accuracy = accuracy;
0319
0320     hw = &osc->hw;
0321     ret = clk_hw_register(NULL, hw);
0322     if (ret) {
0323         kfree(osc);
0324         hw = ERR_PTR(ret);
0325     }
0326
0327     return hw;
0328 }
0329
0330 static int clk_main_probe_frequency(struct regmap *regmap)
0331 {
0332     unsigned long prep_time, timeout;
0333     unsigned int mcfr;
0334
0335     timeout = jiffies + usecs_to_jiffies(MAINFRDY_TIMEOUT);
0336     do {
0337         prep_time = jiffies;
0338         regmap_read(regmap, AT91_CKGR_MCFR, &mcfr);
0339         if (mcfr & AT91_PMC_MAINRDY)
0340             return 0;
0341         if (system_state < SYSTEM_RUNNING)
0342             udelay(MAINF_LOOP_MIN_WAIT);
0343         else
0344             usleep_range(MAINF_LOOP_MIN_WAIT, MAINF_LOOP_MAX_WAIT);
0345     } while (time_before(prep_time, timeout));
0346
0347     return -ETIMEDOUT;
0348 }
0349
0350 static unsigned long clk_main_recalc_rate(struct regmap *regmap,
0351                       unsigned long parent_rate)
0352 {
0353     unsigned int mcfr;
0354
0355     if (parent_rate)
0356         return parent_rate;
0357
0358     pr_warn("Main crystal frequency not set, using approximate value\n");
0359     regmap_read(regmap, AT91_CKGR_MCFR, &mcfr);
0360     if (!(mcfr & AT91_PMC_MAINRDY))
0361         return 0;
0362
0363     return ((mcfr & AT91_PMC_MAINF) * SLOW_CLOCK_FREQ) / MAINF_DIV;
0364 }
0365
0366 static int clk_rm9200_main_prepare(struct clk_hw *hw)
0367 {
0368     struct clk_rm9200_main *clkmain = to_clk_rm9200_main(hw);
0369
0370     return clk_main_probe_frequency(clkmain->regmap);
0371 }
0372
0373 static int clk_rm9200_main_is_prepared(struct clk_hw *hw)
0374 {
0375     struct clk_rm9200_main *clkmain = to_clk_rm9200_main(hw);
0376     unsigned int status;
0377
0378     regmap_read(clkmain->regmap, AT91_CKGR_MCFR, &status);
0379
0380     return !!(status & AT91_PMC_MAINRDY);
0381 }
0382
0383 static unsigned long clk_rm9200_main_recalc_rate(struct clk_hw *hw,
0384                          unsigned long parent_rate)
0385 {
0386     struct clk_rm9200_main *clkmain = to_clk_rm9200_main(hw);
0387
0388     return clk_main_recalc_rate(clkmain->regmap, parent_rate);
0389 }
0390
0391 static const struct clk_ops rm9200_main_ops = {
0392     .prepare = clk_rm9200_main_prepare,
0393     .is_prepared = clk_rm9200_main_is_prepared,
0394     .recalc_rate = clk_rm9200_main_recalc_rate,
0395 };
0396
0397 struct clk_hw * __init
0398 at91_clk_register_rm9200_main(struct regmap *regmap,
0399                   const char *name,
0400                   const char *parent_name)
0401 {
0402     struct clk_rm9200_main *clkmain;
0403     struct clk_init_data init;
0404     struct clk_hw *hw;
0405     int ret;
0406
0407     if (!name)
0408         return ERR_PTR(-EINVAL);
0409
0410     if (!parent_name)
0411         return ERR_PTR(-EINVAL);
0412
0413     clkmain = kzalloc(sizeof(*clkmain), GFP_KERNEL);
0414     if (!clkmain)
0415         return ERR_PTR(-ENOMEM);
0416
0417     init.name = name;
0418     init.ops = &rm9200_main_ops;
0419     init.parent_names = &parent_name;
0420     init.num_parents = 1;
0421     init.flags = 0;
0422
0423     clkmain->hw.init = &init;
0424     clkmain->regmap = regmap;
0425
0426     hw = &clkmain->hw;
0427     ret = clk_hw_register(NULL, &clkmain->hw);
0428     if (ret) {
0429         kfree(clkmain);
0430         hw = ERR_PTR(ret);
0431     }
0432
0433     return hw;
0434 }
0435
0436 static inline bool clk_sam9x5_main_ready(struct regmap *regmap)
0437 {
0438     unsigned int status;
0439
0440     regmap_read(regmap, AT91_PMC_SR, &status);
0441
0442     return !!(status & AT91_PMC_MOSCSELS);
0443 }
0444
0445 static int clk_sam9x5_main_prepare(struct clk_hw *hw)
0446 {
0447     struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw);
0448     struct regmap *regmap = clkmain->regmap;
0449
0450     while (!clk_sam9x5_main_ready(regmap))
0451         cpu_relax();
0452
0453     return clk_main_probe_frequency(regmap);
0454 }
0455
0456 static int clk_sam9x5_main_is_prepared(struct clk_hw *hw)
0457 {
0458     struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw);
0459
0460     return clk_sam9x5_main_ready(clkmain->regmap);
0461 }
0462
0463 static unsigned long clk_sam9x5_main_recalc_rate(struct clk_hw *hw,
0464                          unsigned long parent_rate)
0465 {
0466     struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw);
0467
0468     return clk_main_recalc_rate(clkmain->regmap, parent_rate);
0469 }
0470
0471 static int clk_sam9x5_main_set_parent(struct clk_hw *hw, u8 index)
0472 {
0473     struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw);
0474     struct regmap *regmap = clkmain->regmap;
0475     unsigned int tmp;
0476
0477     if (index > 1)
0478         return -EINVAL;
0479
0480     regmap_read(regmap, AT91_CKGR_MOR, &tmp);
0481
0482     if (index && !(tmp & AT91_PMC_MOSCSEL))
0483         tmp = AT91_PMC_MOSCSEL;
0484     else if (!index && (tmp & AT91_PMC_MOSCSEL))
0485         tmp = 0;
0486     else
0487         return 0;
0488
0489     regmap_update_bits(regmap, AT91_CKGR_MOR,
0490                AT91_PMC_MOSCSEL | MOR_KEY_MASK,
0491                tmp | AT91_PMC_KEY);
0492
0493     while (!clk_sam9x5_main_ready(regmap))
0494         cpu_relax();
0495
0496     return 0;
0497 }
0498
0499 static u8 clk_sam9x5_main_get_parent(struct clk_hw *hw)
0500 {
0501     struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw);
0502     unsigned int status;
0503
0504     regmap_read(clkmain->regmap, AT91_CKGR_MOR, &status);
0505
0506     return clk_main_parent_select(status);
0507 }
0508
0509 static int clk_sam9x5_main_save_context(struct clk_hw *hw)
0510 {
0511     struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw);
0512
0513     clkmain->pms.status = clk_main_rc_osc_is_prepared(&clkmain->hw);
0514     clkmain->pms.parent = clk_sam9x5_main_get_parent(&clkmain->hw);
0515
0516     return 0;
0517 }
0518
0519 static void clk_sam9x5_main_restore_context(struct clk_hw *hw)
0520 {
0521     struct clk_sam9x5_main *clkmain = to_clk_sam9x5_main(hw);
0522     int ret;
0523
0524     ret = clk_sam9x5_main_set_parent(hw, clkmain->pms.parent);
0525     if (ret)
0526         return;
0527
0528     if (clkmain->pms.status)
0529         clk_sam9x5_main_prepare(hw);
0530 }
0531
0532 static const struct clk_ops sam9x5_main_ops = {
0533     .prepare = clk_sam9x5_main_prepare,
0534     .is_prepared = clk_sam9x5_main_is_prepared,
0535     .recalc_rate = clk_sam9x5_main_recalc_rate,
0536     .set_parent = clk_sam9x5_main_set_parent,
0537     .get_parent = clk_sam9x5_main_get_parent,
0538     .save_context = clk_sam9x5_main_save_context,
0539     .restore_context = clk_sam9x5_main_restore_context,
0540 };
0541
0542 struct clk_hw * __init
0543 at91_clk_register_sam9x5_main(struct regmap *regmap,
0544                   const char *name,
0545                   const char **parent_names,
0546                   int num_parents)
0547 {
0548     struct clk_sam9x5_main *clkmain;
0549     struct clk_init_data init;
0550     unsigned int status;
0551     struct clk_hw *hw;
0552     int ret;
0553
0554     if (!name)
0555         return ERR_PTR(-EINVAL);
0556
0557     if (!parent_names || !num_parents)
0558         return ERR_PTR(-EINVAL);
0559
0560     clkmain = kzalloc(sizeof(*clkmain), GFP_KERNEL);
0561     if (!clkmain)
0562         return ERR_PTR(-ENOMEM);
0563
0564     init.name = name;
0565     init.ops = &sam9x5_main_ops;
0566     init.parent_names = parent_names;
0567     init.num_parents = num_parents;
0568     init.flags = CLK_SET_PARENT_GATE;
0569
0570     clkmain->hw.init = &init;
0571     clkmain->regmap = regmap;
0572     regmap_read(clkmain->regmap, AT91_CKGR_MOR, &status);
0573     clkmain->parent = clk_main_parent_select(status);
0574
0575     hw = &clkmain->hw;
0576     ret = clk_hw_register(NULL, &clkmain->hw);
0577     if (ret) {
0578         kfree(clkmain);
0579         hw = ERR_PTR(ret);
0580     }
0581
0582     return hw;
0583 }