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0009 #include <linux/clk-provider.h>
0010 #include <linux/of.h>
0011 #include <linux/mfd/syscon.h>
0012 #include <linux/regmap.h>
0013 #include <linux/slab.h>
0014
0015 #include <soc/at91/atmel-sfr.h>
0016
0017 #include "pmc.h"
0018
0019 struct clk_i2s_mux {
0020 struct clk_hw hw;
0021 struct regmap *regmap;
0022 u8 bus_id;
0023 };
0024
0025 #define to_clk_i2s_mux(hw) container_of(hw, struct clk_i2s_mux, hw)
0026
0027 static u8 clk_i2s_mux_get_parent(struct clk_hw *hw)
0028 {
0029 struct clk_i2s_mux *mux = to_clk_i2s_mux(hw);
0030 u32 val;
0031
0032 regmap_read(mux->regmap, AT91_SFR_I2SCLKSEL, &val);
0033
0034 return (val & BIT(mux->bus_id)) >> mux->bus_id;
0035 }
0036
0037 static int clk_i2s_mux_set_parent(struct clk_hw *hw, u8 index)
0038 {
0039 struct clk_i2s_mux *mux = to_clk_i2s_mux(hw);
0040
0041 return regmap_update_bits(mux->regmap, AT91_SFR_I2SCLKSEL,
0042 BIT(mux->bus_id), index << mux->bus_id);
0043 }
0044
0045 static const struct clk_ops clk_i2s_mux_ops = {
0046 .get_parent = clk_i2s_mux_get_parent,
0047 .set_parent = clk_i2s_mux_set_parent,
0048 .determine_rate = __clk_mux_determine_rate,
0049 };
0050
0051 struct clk_hw * __init
0052 at91_clk_i2s_mux_register(struct regmap *regmap, const char *name,
0053 const char * const *parent_names,
0054 unsigned int num_parents, u8 bus_id)
0055 {
0056 struct clk_init_data init = {};
0057 struct clk_i2s_mux *i2s_ck;
0058 int ret;
0059
0060 i2s_ck = kzalloc(sizeof(*i2s_ck), GFP_KERNEL);
0061 if (!i2s_ck)
0062 return ERR_PTR(-ENOMEM);
0063
0064 init.name = name;
0065 init.ops = &clk_i2s_mux_ops;
0066 init.parent_names = parent_names;
0067 init.num_parents = num_parents;
0068
0069 i2s_ck->hw.init = &init;
0070 i2s_ck->bus_id = bus_id;
0071 i2s_ck->regmap = regmap;
0072
0073 ret = clk_hw_register(NULL, &i2s_ck->hw);
0074 if (ret) {
0075 kfree(i2s_ck);
0076 return ERR_PTR(ret);
0077 }
0078
0079 return &i2s_ck->hw;
0080 }