clk/at91/at91sam9x5.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 #include <linux/clk-provider.h>
0003 #include <linux/mfd/syscon.h>
0004 #include <linux/slab.h>
0005
0006 #include <dt-bindings/clock/at91.h>
0007
0008 #include "pmc.h"
0009
0010 static DEFINE_SPINLOCK(mck_lock);
0011
0012 static const struct clk_master_characteristics mck_characteristics = {
0013     .output = { .min = 0, .max = 133333333 },
0014     .divisors = { 1, 2, 4, 3 },
0015     .have_div3_pres = 1,
0016 };
0017
0018 static u8 plla_out[] = { 0, 1, 2, 3, 0, 1, 2, 3 };
0019
0020 static u16 plla_icpll[] = { 0, 0, 0, 0, 1, 1, 1, 1 };
0021
0022 static const struct clk_range plla_outputs[] = {
0023     { .min = 745000000, .max = 800000000 },
0024     { .min = 695000000, .max = 750000000 },
0025     { .min = 645000000, .max = 700000000 },
0026     { .min = 595000000, .max = 650000000 },
0027     { .min = 545000000, .max = 600000000 },
0028     { .min = 495000000, .max = 555000000 },
0029     { .min = 445000000, .max = 500000000 },
0030     { .min = 400000000, .max = 450000000 },
0031 };
0032
0033 static const struct clk_pll_characteristics plla_characteristics = {
0034     .input = { .min = 2000000, .max = 32000000 },
0035     .num_output = ARRAY_SIZE(plla_outputs),
0036     .output = plla_outputs,
0037     .icpll = plla_icpll,
0038     .out = plla_out,
0039 };
0040
0041 static const struct {
0042     char *n;
0043     char *p;
0044     u8 id;
0045 } at91sam9x5_systemck[] = {
0046     { .n = "ddrck", .p = "masterck_div", .id = 2 },
0047     { .n = "smdck", .p = "smdclk",   .id = 4 },
0048     { .n = "uhpck", .p = "usbck",    .id = 6 },
0049     { .n = "udpck", .p = "usbck",    .id = 7 },
0050     { .n = "pck0",  .p = "prog0",    .id = 8 },
0051     { .n = "pck1",  .p = "prog1",    .id = 9 },
0052 };
0053
0054 static const struct clk_pcr_layout at91sam9x5_pcr_layout = {
0055     .offset = 0x10c,
0056     .cmd = BIT(12),
0057     .pid_mask = GENMASK(5, 0),
0058     .div_mask = GENMASK(17, 16),
0059 };
0060
0061 struct pck {
0062     char *n;
0063     u8 id;
0064 };
0065
0066 static const struct pck at91sam9x5_periphck[] = {
0067     { .n = "pioAB_clk",  .id = 2, },
0068     { .n = "pioCD_clk",  .id = 3, },
0069     { .n = "smd_clk",    .id = 4, },
0070     { .n = "usart0_clk", .id = 5, },
0071     { .n = "usart1_clk", .id = 6, },
0072     { .n = "usart2_clk", .id = 7, },
0073     { .n = "twi0_clk",   .id = 9, },
0074     { .n = "twi1_clk",   .id = 10, },
0075     { .n = "twi2_clk",   .id = 11, },
0076     { .n = "mci0_clk",   .id = 12, },
0077     { .n = "spi0_clk",   .id = 13, },
0078     { .n = "spi1_clk",   .id = 14, },
0079     { .n = "uart0_clk",  .id = 15, },
0080     { .n = "uart1_clk",  .id = 16, },
0081     { .n = "tcb0_clk",   .id = 17, },
0082     { .n = "pwm_clk",    .id = 18, },
0083     { .n = "adc_clk",    .id = 19, },
0084     { .n = "dma0_clk",   .id = 20, },
0085     { .n = "dma1_clk",   .id = 21, },
0086     { .n = "uhphs_clk",  .id = 22, },
0087     { .n = "udphs_clk",  .id = 23, },
0088     { .n = "mci1_clk",   .id = 26, },
0089     { .n = "ssc0_clk",   .id = 28, },
0090 };
0091
0092 static const struct pck at91sam9g15_periphck[] = {
0093     { .n = "lcdc_clk", .id = 25, },
0094     { /* sentinel */}
0095 };
0096
0097 static const struct pck at91sam9g25_periphck[] = {
0098     { .n = "usart3_clk", .id = 8, },
0099     { .n = "macb0_clk", .id = 24, },
0100     { .n = "isi_clk", .id = 25, },
0101     { /* sentinel */}
0102 };
0103
0104 static const struct pck at91sam9g35_periphck[] = {
0105     { .n = "macb0_clk", .id = 24, },
0106     { .n = "lcdc_clk", .id = 25, },
0107     { /* sentinel */}
0108 };
0109
0110 static const struct pck at91sam9x25_periphck[] = {
0111     { .n = "usart3_clk", .id = 8, },
0112     { .n = "macb0_clk", .id = 24, },
0113     { .n = "macb1_clk", .id = 27, },
0114     { .n = "can0_clk", .id = 29, },
0115     { .n = "can1_clk", .id = 30, },
0116     { /* sentinel */}
0117 };
0118
0119 static const struct pck at91sam9x35_periphck[] = {
0120     { .n = "macb0_clk", .id = 24, },
0121     { .n = "lcdc_clk", .id = 25, },
0122     { .n = "can0_clk", .id = 29, },
0123     { .n = "can1_clk", .id = 30, },
0124     { /* sentinel */}
0125 };
0126
0127 static void __init at91sam9x5_pmc_setup(struct device_node *np,
0128                     const struct pck *extra_pcks,
0129                     bool has_lcdck)
0130 {
0131     struct clk_range range = CLK_RANGE(0, 0);
0132     const char *slck_name, *mainxtal_name;
0133     struct pmc_data *at91sam9x5_pmc;
0134     const char *parent_names[6];
0135     struct regmap *regmap;
0136     struct clk_hw *hw;
0137     int i;
0138     bool bypass;
0139
0140     i = of_property_match_string(np, "clock-names", "slow_clk");
0141     if (i < 0)
0142         return;
0143
0144     slck_name = of_clk_get_parent_name(np, i);
0145
0146     i = of_property_match_string(np, "clock-names", "main_xtal");
0147     if (i < 0)
0148         return;
0149     mainxtal_name = of_clk_get_parent_name(np, i);
0150
0151     regmap = device_node_to_regmap(np);
0152     if (IS_ERR(regmap))
0153         return;
0154
0155     at91sam9x5_pmc = pmc_data_allocate(PMC_PLLACK + 1,
0156                        nck(at91sam9x5_systemck), 31, 0, 2);
0157     if (!at91sam9x5_pmc)
0158         return;
0159
0160     hw = at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000,
0161                        50000000);
0162     if (IS_ERR(hw))
0163         goto err_free;
0164
0165     bypass = of_property_read_bool(np, "atmel,osc-bypass");
0166
0167     hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name,
0168                     bypass);
0169     if (IS_ERR(hw))
0170         goto err_free;
0171
0172     parent_names[0] = "main_rc_osc";
0173     parent_names[1] = "main_osc";
0174     hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, 2);
0175     if (IS_ERR(hw))
0176         goto err_free;
0177
0178     at91sam9x5_pmc->chws[PMC_MAIN] = hw;
0179
0180     hw = at91_clk_register_pll(regmap, "pllack", "mainck", 0,
0181                    &at91rm9200_pll_layout, &plla_characteristics);
0182     if (IS_ERR(hw))
0183         goto err_free;
0184
0185     hw = at91_clk_register_plldiv(regmap, "plladivck", "pllack");
0186     if (IS_ERR(hw))
0187         goto err_free;
0188
0189     at91sam9x5_pmc->chws[PMC_PLLACK] = hw;
0190
0191     hw = at91_clk_register_utmi(regmap, NULL, "utmick", "mainck");
0192     if (IS_ERR(hw))
0193         goto err_free;
0194
0195     at91sam9x5_pmc->chws[PMC_UTMI] = hw;
0196
0197     parent_names[0] = slck_name;
0198     parent_names[1] = "mainck";
0199     parent_names[2] = "plladivck";
0200     parent_names[3] = "utmick";
0201     hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4,
0202                        parent_names,
0203                        &at91sam9x5_master_layout,
0204                        &mck_characteristics, &mck_lock);
0205     if (IS_ERR(hw))
0206         goto err_free;
0207
0208     hw = at91_clk_register_master_div(regmap, "masterck_div",
0209                       "masterck_pres",
0210                       &at91sam9x5_master_layout,
0211                       &mck_characteristics, &mck_lock,
0212                       CLK_SET_RATE_GATE, 0);
0213     if (IS_ERR(hw))
0214         goto err_free;
0215
0216     at91sam9x5_pmc->chws[PMC_MCK] = hw;
0217
0218     parent_names[0] = "plladivck";
0219     parent_names[1] = "utmick";
0220     hw = at91sam9x5_clk_register_usb(regmap, "usbck", parent_names, 2);
0221     if (IS_ERR(hw))
0222         goto err_free;
0223
0224     hw = at91sam9x5_clk_register_smd(regmap, "smdclk", parent_names, 2);
0225     if (IS_ERR(hw))
0226         goto err_free;
0227
0228     parent_names[0] = slck_name;
0229     parent_names[1] = "mainck";
0230     parent_names[2] = "plladivck";
0231     parent_names[3] = "utmick";
0232     parent_names[4] = "masterck_div";
0233     for (i = 0; i < 2; i++) {
0234         char name[6];
0235
0236         snprintf(name, sizeof(name), "prog%d", i);
0237
0238         hw = at91_clk_register_programmable(regmap, name,
0239                             parent_names, 5, i,
0240                             &at91sam9x5_programmable_layout,
0241                             NULL);
0242         if (IS_ERR(hw))
0243             goto err_free;
0244
0245         at91sam9x5_pmc->pchws[i] = hw;
0246     }
0247
0248     for (i = 0; i < ARRAY_SIZE(at91sam9x5_systemck); i++) {
0249         hw = at91_clk_register_system(regmap, at91sam9x5_systemck[i].n,
0250                           at91sam9x5_systemck[i].p,
0251                           at91sam9x5_systemck[i].id);
0252         if (IS_ERR(hw))
0253             goto err_free;
0254
0255         at91sam9x5_pmc->shws[at91sam9x5_systemck[i].id] = hw;
0256     }
0257
0258     if (has_lcdck) {
0259         hw = at91_clk_register_system(regmap, "lcdck", "masterck_div", 3);
0260         if (IS_ERR(hw))
0261             goto err_free;
0262
0263         at91sam9x5_pmc->shws[3] = hw;
0264     }
0265
0266     for (i = 0; i < ARRAY_SIZE(at91sam9x5_periphck); i++) {
0267         hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
0268                              &at91sam9x5_pcr_layout,
0269                              at91sam9x5_periphck[i].n,
0270                              "masterck_div",
0271                              at91sam9x5_periphck[i].id,
0272                              &range, INT_MIN);
0273         if (IS_ERR(hw))
0274             goto err_free;
0275
0276         at91sam9x5_pmc->phws[at91sam9x5_periphck[i].id] = hw;
0277     }
0278
0279     for (i = 0; extra_pcks[i].id; i++) {
0280         hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
0281                              &at91sam9x5_pcr_layout,
0282                              extra_pcks[i].n,
0283                              "masterck_div",
0284                              extra_pcks[i].id,
0285                              &range, INT_MIN);
0286         if (IS_ERR(hw))
0287             goto err_free;
0288
0289         at91sam9x5_pmc->phws[extra_pcks[i].id] = hw;
0290     }
0291
0292     of_clk_add_hw_provider(np, of_clk_hw_pmc_get, at91sam9x5_pmc);
0293
0294     return;
0295
0296 err_free:
0297     kfree(at91sam9x5_pmc);
0298 }
0299
0300 static void __init at91sam9g15_pmc_setup(struct device_node *np)
0301 {
0302     at91sam9x5_pmc_setup(np, at91sam9g15_periphck, true);
0303 }
0304
0305 CLK_OF_DECLARE(at91sam9g15_pmc, "atmel,at91sam9g15-pmc", at91sam9g15_pmc_setup);
0306
0307 static void __init at91sam9g25_pmc_setup(struct device_node *np)
0308 {
0309     at91sam9x5_pmc_setup(np, at91sam9g25_periphck, false);
0310 }
0311
0312 CLK_OF_DECLARE(at91sam9g25_pmc, "atmel,at91sam9g25-pmc", at91sam9g25_pmc_setup);
0313
0314 static void __init at91sam9g35_pmc_setup(struct device_node *np)
0315 {
0316     at91sam9x5_pmc_setup(np, at91sam9g35_periphck, true);
0317 }
0318
0319 CLK_OF_DECLARE(at91sam9g35_pmc, "atmel,at91sam9g35-pmc", at91sam9g35_pmc_setup);
0320
0321 static void __init at91sam9x25_pmc_setup(struct device_node *np)
0322 {
0323     at91sam9x5_pmc_setup(np, at91sam9x25_periphck, false);
0324 }
0325
0326 CLK_OF_DECLARE(at91sam9x25_pmc, "atmel,at91sam9x25-pmc", at91sam9x25_pmc_setup);
0327
0328 static void __init at91sam9x35_pmc_setup(struct device_node *np)
0329 {
0330     at91sam9x5_pmc_setup(np, at91sam9x35_periphck, true);
0331 }
0332
0333 CLK_OF_DECLARE(at91sam9x35_pmc, "atmel,at91sam9x35-pmc", at91sam9x35_pmc_setup);