0001
0002 #include <linux/clk-provider.h>
0003 #include <linux/mfd/syscon.h>
0004 #include <linux/slab.h>
0005
0006 #include <dt-bindings/clock/at91.h>
0007
0008 #include "pmc.h"
0009
0010 static DEFINE_SPINLOCK(sam9rl_mck_lock);
0011
0012 static const struct clk_master_characteristics sam9rl_mck_characteristics = {
0013 .output = { .min = 0, .max = 94000000 },
0014 .divisors = { 1, 2, 4, 0 },
0015 };
0016
0017 static u8 sam9rl_plla_out[] = { 0, 2 };
0018
0019 static const struct clk_range sam9rl_plla_outputs[] = {
0020 { .min = 80000000, .max = 200000000 },
0021 { .min = 190000000, .max = 240000000 },
0022 };
0023
0024 static const struct clk_pll_characteristics sam9rl_plla_characteristics = {
0025 .input = { .min = 1000000, .max = 32000000 },
0026 .num_output = ARRAY_SIZE(sam9rl_plla_outputs),
0027 .output = sam9rl_plla_outputs,
0028 .out = sam9rl_plla_out,
0029 };
0030
0031 static const struct {
0032 char *n;
0033 char *p;
0034 u8 id;
0035 } at91sam9rl_systemck[] = {
0036 { .n = "pck0", .p = "prog0", .id = 8 },
0037 { .n = "pck1", .p = "prog1", .id = 9 },
0038 };
0039
0040 static const struct {
0041 char *n;
0042 u8 id;
0043 } at91sam9rl_periphck[] = {
0044 { .n = "pioA_clk", .id = 2, },
0045 { .n = "pioB_clk", .id = 3, },
0046 { .n = "pioC_clk", .id = 4, },
0047 { .n = "pioD_clk", .id = 5, },
0048 { .n = "usart0_clk", .id = 6, },
0049 { .n = "usart1_clk", .id = 7, },
0050 { .n = "usart2_clk", .id = 8, },
0051 { .n = "usart3_clk", .id = 9, },
0052 { .n = "mci0_clk", .id = 10, },
0053 { .n = "twi0_clk", .id = 11, },
0054 { .n = "twi1_clk", .id = 12, },
0055 { .n = "spi0_clk", .id = 13, },
0056 { .n = "ssc0_clk", .id = 14, },
0057 { .n = "ssc1_clk", .id = 15, },
0058 { .n = "tc0_clk", .id = 16, },
0059 { .n = "tc1_clk", .id = 17, },
0060 { .n = "tc2_clk", .id = 18, },
0061 { .n = "pwm_clk", .id = 19, },
0062 { .n = "adc_clk", .id = 20, },
0063 { .n = "dma0_clk", .id = 21, },
0064 { .n = "udphs_clk", .id = 22, },
0065 { .n = "lcd_clk", .id = 23, },
0066 };
0067
0068 static void __init at91sam9rl_pmc_setup(struct device_node *np)
0069 {
0070 const char *slck_name, *mainxtal_name;
0071 struct pmc_data *at91sam9rl_pmc;
0072 const char *parent_names[6];
0073 struct regmap *regmap;
0074 struct clk_hw *hw;
0075 int i;
0076
0077 i = of_property_match_string(np, "clock-names", "slow_clk");
0078 if (i < 0)
0079 return;
0080
0081 slck_name = of_clk_get_parent_name(np, i);
0082
0083 i = of_property_match_string(np, "clock-names", "main_xtal");
0084 if (i < 0)
0085 return;
0086 mainxtal_name = of_clk_get_parent_name(np, i);
0087
0088 regmap = device_node_to_regmap(np);
0089 if (IS_ERR(regmap))
0090 return;
0091
0092 at91sam9rl_pmc = pmc_data_allocate(PMC_PLLACK + 1,
0093 nck(at91sam9rl_systemck),
0094 nck(at91sam9rl_periphck), 0, 2);
0095 if (!at91sam9rl_pmc)
0096 return;
0097
0098 hw = at91_clk_register_rm9200_main(regmap, "mainck", mainxtal_name);
0099 if (IS_ERR(hw))
0100 goto err_free;
0101
0102 at91sam9rl_pmc->chws[PMC_MAIN] = hw;
0103
0104 hw = at91_clk_register_pll(regmap, "pllack", "mainck", 0,
0105 &at91rm9200_pll_layout,
0106 &sam9rl_plla_characteristics);
0107 if (IS_ERR(hw))
0108 goto err_free;
0109
0110 at91sam9rl_pmc->chws[PMC_PLLACK] = hw;
0111
0112 hw = at91_clk_register_utmi(regmap, NULL, "utmick", "mainck");
0113 if (IS_ERR(hw))
0114 goto err_free;
0115
0116 at91sam9rl_pmc->chws[PMC_UTMI] = hw;
0117
0118 parent_names[0] = slck_name;
0119 parent_names[1] = "mainck";
0120 parent_names[2] = "pllack";
0121 parent_names[3] = "utmick";
0122 hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4,
0123 parent_names,
0124 &at91rm9200_master_layout,
0125 &sam9rl_mck_characteristics,
0126 &sam9rl_mck_lock);
0127 if (IS_ERR(hw))
0128 goto err_free;
0129
0130 hw = at91_clk_register_master_div(regmap, "masterck_div",
0131 "masterck_pres",
0132 &at91rm9200_master_layout,
0133 &sam9rl_mck_characteristics,
0134 &sam9rl_mck_lock, CLK_SET_RATE_GATE, 0);
0135 if (IS_ERR(hw))
0136 goto err_free;
0137
0138 at91sam9rl_pmc->chws[PMC_MCK] = hw;
0139
0140 parent_names[0] = slck_name;
0141 parent_names[1] = "mainck";
0142 parent_names[2] = "pllack";
0143 parent_names[3] = "utmick";
0144 parent_names[4] = "masterck_div";
0145 for (i = 0; i < 2; i++) {
0146 char name[6];
0147
0148 snprintf(name, sizeof(name), "prog%d", i);
0149
0150 hw = at91_clk_register_programmable(regmap, name,
0151 parent_names, 5, i,
0152 &at91rm9200_programmable_layout,
0153 NULL);
0154 if (IS_ERR(hw))
0155 goto err_free;
0156
0157 at91sam9rl_pmc->pchws[i] = hw;
0158 }
0159
0160 for (i = 0; i < ARRAY_SIZE(at91sam9rl_systemck); i++) {
0161 hw = at91_clk_register_system(regmap, at91sam9rl_systemck[i].n,
0162 at91sam9rl_systemck[i].p,
0163 at91sam9rl_systemck[i].id);
0164 if (IS_ERR(hw))
0165 goto err_free;
0166
0167 at91sam9rl_pmc->shws[at91sam9rl_systemck[i].id] = hw;
0168 }
0169
0170 for (i = 0; i < ARRAY_SIZE(at91sam9rl_periphck); i++) {
0171 hw = at91_clk_register_peripheral(regmap,
0172 at91sam9rl_periphck[i].n,
0173 "masterck_div",
0174 at91sam9rl_periphck[i].id);
0175 if (IS_ERR(hw))
0176 goto err_free;
0177
0178 at91sam9rl_pmc->phws[at91sam9rl_periphck[i].id] = hw;
0179 }
0180
0181 of_clk_add_hw_provider(np, of_clk_hw_pmc_get, at91sam9rl_pmc);
0182
0183 return;
0184
0185 err_free:
0186 kfree(at91sam9rl_pmc);
0187 }
0188
0189 CLK_OF_DECLARE(at91sam9rl_pmc, "atmel,at91sam9rl-pmc", at91sam9rl_pmc_setup);
