0001
0002 #include <linux/clk-provider.h>
0003 #include <linux/mfd/syscon.h>
0004 #include <linux/slab.h>
0005
0006 #include <dt-bindings/clock/at91.h>
0007
0008 #include "pmc.h"
0009
0010 static DEFINE_SPINLOCK(at91sam9n12_mck_lock);
0011
0012 static const struct clk_master_characteristics mck_characteristics = {
0013 .output = { .min = 0, .max = 133333333 },
0014 .divisors = { 1, 2, 4, 3 },
0015 .have_div3_pres = 1,
0016 };
0017
0018 static u8 plla_out[] = { 0, 1, 2, 3, 0, 1, 2, 3 };
0019
0020 static u16 plla_icpll[] = { 0, 0, 0, 0, 1, 1, 1, 1 };
0021
0022 static const struct clk_range plla_outputs[] = {
0023 { .min = 745000000, .max = 800000000 },
0024 { .min = 695000000, .max = 750000000 },
0025 { .min = 645000000, .max = 700000000 },
0026 { .min = 595000000, .max = 650000000 },
0027 { .min = 545000000, .max = 600000000 },
0028 { .min = 495000000, .max = 555000000 },
0029 { .min = 445000000, .max = 500000000 },
0030 { .min = 400000000, .max = 450000000 },
0031 };
0032
0033 static const struct clk_pll_characteristics plla_characteristics = {
0034 .input = { .min = 2000000, .max = 32000000 },
0035 .num_output = ARRAY_SIZE(plla_outputs),
0036 .output = plla_outputs,
0037 .icpll = plla_icpll,
0038 .out = plla_out,
0039 };
0040
0041 static u8 pllb_out[] = { 0 };
0042
0043 static const struct clk_range pllb_outputs[] = {
0044 { .min = 30000000, .max = 100000000 },
0045 };
0046
0047 static const struct clk_pll_characteristics pllb_characteristics = {
0048 .input = { .min = 2000000, .max = 32000000 },
0049 .num_output = ARRAY_SIZE(pllb_outputs),
0050 .output = pllb_outputs,
0051 .out = pllb_out,
0052 };
0053
0054 static const struct {
0055 char *n;
0056 char *p;
0057 u8 id;
0058 } at91sam9n12_systemck[] = {
0059 { .n = "ddrck", .p = "masterck_div", .id = 2 },
0060 { .n = "lcdck", .p = "masterck_div", .id = 3 },
0061 { .n = "uhpck", .p = "usbck", .id = 6 },
0062 { .n = "udpck", .p = "usbck", .id = 7 },
0063 { .n = "pck0", .p = "prog0", .id = 8 },
0064 { .n = "pck1", .p = "prog1", .id = 9 },
0065 };
0066
0067 static const struct clk_pcr_layout at91sam9n12_pcr_layout = {
0068 .offset = 0x10c,
0069 .cmd = BIT(12),
0070 .pid_mask = GENMASK(5, 0),
0071 .div_mask = GENMASK(17, 16),
0072 };
0073
0074 struct pck {
0075 char *n;
0076 u8 id;
0077 };
0078
0079 static const struct pck at91sam9n12_periphck[] = {
0080 { .n = "pioAB_clk", .id = 2, },
0081 { .n = "pioCD_clk", .id = 3, },
0082 { .n = "fuse_clk", .id = 4, },
0083 { .n = "usart0_clk", .id = 5, },
0084 { .n = "usart1_clk", .id = 6, },
0085 { .n = "usart2_clk", .id = 7, },
0086 { .n = "usart3_clk", .id = 8, },
0087 { .n = "twi0_clk", .id = 9, },
0088 { .n = "twi1_clk", .id = 10, },
0089 { .n = "mci0_clk", .id = 12, },
0090 { .n = "spi0_clk", .id = 13, },
0091 { .n = "spi1_clk", .id = 14, },
0092 { .n = "uart0_clk", .id = 15, },
0093 { .n = "uart1_clk", .id = 16, },
0094 { .n = "tcb_clk", .id = 17, },
0095 { .n = "pwm_clk", .id = 18, },
0096 { .n = "adc_clk", .id = 19, },
0097 { .n = "dma0_clk", .id = 20, },
0098 { .n = "uhphs_clk", .id = 22, },
0099 { .n = "udphs_clk", .id = 23, },
0100 { .n = "lcdc_clk", .id = 25, },
0101 { .n = "sha_clk", .id = 27, },
0102 { .n = "ssc0_clk", .id = 28, },
0103 { .n = "aes_clk", .id = 29, },
0104 { .n = "trng_clk", .id = 30, },
0105 };
0106
0107 static void __init at91sam9n12_pmc_setup(struct device_node *np)
0108 {
0109 struct clk_range range = CLK_RANGE(0, 0);
0110 const char *slck_name, *mainxtal_name;
0111 struct pmc_data *at91sam9n12_pmc;
0112 const char *parent_names[6];
0113 struct regmap *regmap;
0114 struct clk_hw *hw;
0115 int i;
0116 bool bypass;
0117
0118 i = of_property_match_string(np, "clock-names", "slow_clk");
0119 if (i < 0)
0120 return;
0121
0122 slck_name = of_clk_get_parent_name(np, i);
0123
0124 i = of_property_match_string(np, "clock-names", "main_xtal");
0125 if (i < 0)
0126 return;
0127 mainxtal_name = of_clk_get_parent_name(np, i);
0128
0129 regmap = device_node_to_regmap(np);
0130 if (IS_ERR(regmap))
0131 return;
0132
0133 at91sam9n12_pmc = pmc_data_allocate(PMC_PLLBCK + 1,
0134 nck(at91sam9n12_systemck), 31, 0, 2);
0135 if (!at91sam9n12_pmc)
0136 return;
0137
0138 hw = at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 12000000,
0139 50000000);
0140 if (IS_ERR(hw))
0141 goto err_free;
0142
0143 bypass = of_property_read_bool(np, "atmel,osc-bypass");
0144
0145 hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name,
0146 bypass);
0147 if (IS_ERR(hw))
0148 goto err_free;
0149
0150 parent_names[0] = "main_rc_osc";
0151 parent_names[1] = "main_osc";
0152 hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, 2);
0153 if (IS_ERR(hw))
0154 goto err_free;
0155
0156 at91sam9n12_pmc->chws[PMC_MAIN] = hw;
0157
0158 hw = at91_clk_register_pll(regmap, "pllack", "mainck", 0,
0159 &at91rm9200_pll_layout, &plla_characteristics);
0160 if (IS_ERR(hw))
0161 goto err_free;
0162
0163 hw = at91_clk_register_plldiv(regmap, "plladivck", "pllack");
0164 if (IS_ERR(hw))
0165 goto err_free;
0166
0167 at91sam9n12_pmc->chws[PMC_PLLACK] = hw;
0168
0169 hw = at91_clk_register_pll(regmap, "pllbck", "mainck", 1,
0170 &at91rm9200_pll_layout, &pllb_characteristics);
0171 if (IS_ERR(hw))
0172 goto err_free;
0173
0174 at91sam9n12_pmc->chws[PMC_PLLBCK] = hw;
0175
0176 parent_names[0] = slck_name;
0177 parent_names[1] = "mainck";
0178 parent_names[2] = "plladivck";
0179 parent_names[3] = "pllbck";
0180 hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4,
0181 parent_names,
0182 &at91sam9x5_master_layout,
0183 &mck_characteristics,
0184 &at91sam9n12_mck_lock);
0185 if (IS_ERR(hw))
0186 goto err_free;
0187
0188 hw = at91_clk_register_master_div(regmap, "masterck_div",
0189 "masterck_pres",
0190 &at91sam9x5_master_layout,
0191 &mck_characteristics,
0192 &at91sam9n12_mck_lock,
0193 CLK_SET_RATE_GATE, 0);
0194 if (IS_ERR(hw))
0195 goto err_free;
0196
0197 at91sam9n12_pmc->chws[PMC_MCK] = hw;
0198
0199 hw = at91sam9n12_clk_register_usb(regmap, "usbck", "pllbck");
0200 if (IS_ERR(hw))
0201 goto err_free;
0202
0203 parent_names[0] = slck_name;
0204 parent_names[1] = "mainck";
0205 parent_names[2] = "plladivck";
0206 parent_names[3] = "pllbck";
0207 parent_names[4] = "masterck_div";
0208 for (i = 0; i < 2; i++) {
0209 char name[6];
0210
0211 snprintf(name, sizeof(name), "prog%d", i);
0212
0213 hw = at91_clk_register_programmable(regmap, name,
0214 parent_names, 5, i,
0215 &at91sam9x5_programmable_layout,
0216 NULL);
0217 if (IS_ERR(hw))
0218 goto err_free;
0219
0220 at91sam9n12_pmc->pchws[i] = hw;
0221 }
0222
0223 for (i = 0; i < ARRAY_SIZE(at91sam9n12_systemck); i++) {
0224 hw = at91_clk_register_system(regmap, at91sam9n12_systemck[i].n,
0225 at91sam9n12_systemck[i].p,
0226 at91sam9n12_systemck[i].id);
0227 if (IS_ERR(hw))
0228 goto err_free;
0229
0230 at91sam9n12_pmc->shws[at91sam9n12_systemck[i].id] = hw;
0231 }
0232
0233 for (i = 0; i < ARRAY_SIZE(at91sam9n12_periphck); i++) {
0234 hw = at91_clk_register_sam9x5_peripheral(regmap, &pmc_pcr_lock,
0235 &at91sam9n12_pcr_layout,
0236 at91sam9n12_periphck[i].n,
0237 "masterck_div",
0238 at91sam9n12_periphck[i].id,
0239 &range, INT_MIN);
0240 if (IS_ERR(hw))
0241 goto err_free;
0242
0243 at91sam9n12_pmc->phws[at91sam9n12_periphck[i].id] = hw;
0244 }
0245
0246 of_clk_add_hw_provider(np, of_clk_hw_pmc_get, at91sam9n12_pmc);
0247
0248 return;
0249
0250 err_free:
0251 kfree(at91sam9n12_pmc);
0252 }
0253
0254
0255
0256
0257 CLK_OF_DECLARE(at91sam9n12_pmc, "atmel,at91sam9n12-pmc", at91sam9n12_pmc_setup);
