0001
0002 #include <linux/clk-provider.h>
0003 #include <linux/mfd/syscon.h>
0004 #include <linux/slab.h>
0005
0006 #include <dt-bindings/clock/at91.h>
0007
0008 #include "pmc.h"
0009
0010 static DEFINE_SPINLOCK(at91sam9g45_mck_lock);
0011
0012 static const struct clk_master_characteristics mck_characteristics = {
0013 .output = { .min = 0, .max = 133333333 },
0014 .divisors = { 1, 2, 4, 3 },
0015 };
0016
0017 static u8 plla_out[] = { 0, 1, 2, 3, 0, 1, 2, 3 };
0018
0019 static u16 plla_icpll[] = { 0, 0, 0, 0, 1, 1, 1, 1 };
0020
0021 static const struct clk_range plla_outputs[] = {
0022 { .min = 745000000, .max = 800000000 },
0023 { .min = 695000000, .max = 750000000 },
0024 { .min = 645000000, .max = 700000000 },
0025 { .min = 595000000, .max = 650000000 },
0026 { .min = 545000000, .max = 600000000 },
0027 { .min = 495000000, .max = 555000000 },
0028 { .min = 445000000, .max = 500000000 },
0029 { .min = 400000000, .max = 450000000 },
0030 };
0031
0032 static const struct clk_pll_characteristics plla_characteristics = {
0033 .input = { .min = 2000000, .max = 32000000 },
0034 .num_output = ARRAY_SIZE(plla_outputs),
0035 .output = plla_outputs,
0036 .icpll = plla_icpll,
0037 .out = plla_out,
0038 };
0039
0040 static const struct {
0041 char *n;
0042 char *p;
0043 u8 id;
0044 } at91sam9g45_systemck[] = {
0045 { .n = "ddrck", .p = "masterck_div", .id = 2 },
0046 { .n = "uhpck", .p = "usbck", .id = 6 },
0047 { .n = "pck0", .p = "prog0", .id = 8 },
0048 { .n = "pck1", .p = "prog1", .id = 9 },
0049 };
0050
0051 struct pck {
0052 char *n;
0053 u8 id;
0054 };
0055
0056 static const struct pck at91sam9g45_periphck[] = {
0057 { .n = "pioA_clk", .id = 2, },
0058 { .n = "pioB_clk", .id = 3, },
0059 { .n = "pioC_clk", .id = 4, },
0060 { .n = "pioDE_clk", .id = 5, },
0061 { .n = "trng_clk", .id = 6, },
0062 { .n = "usart0_clk", .id = 7, },
0063 { .n = "usart1_clk", .id = 8, },
0064 { .n = "usart2_clk", .id = 9, },
0065 { .n = "usart3_clk", .id = 10, },
0066 { .n = "mci0_clk", .id = 11, },
0067 { .n = "twi0_clk", .id = 12, },
0068 { .n = "twi1_clk", .id = 13, },
0069 { .n = "spi0_clk", .id = 14, },
0070 { .n = "spi1_clk", .id = 15, },
0071 { .n = "ssc0_clk", .id = 16, },
0072 { .n = "ssc1_clk", .id = 17, },
0073 { .n = "tcb0_clk", .id = 18, },
0074 { .n = "pwm_clk", .id = 19, },
0075 { .n = "adc_clk", .id = 20, },
0076 { .n = "dma0_clk", .id = 21, },
0077 { .n = "uhphs_clk", .id = 22, },
0078 { .n = "lcd_clk", .id = 23, },
0079 { .n = "ac97_clk", .id = 24, },
0080 { .n = "macb0_clk", .id = 25, },
0081 { .n = "isi_clk", .id = 26, },
0082 { .n = "udphs_clk", .id = 27, },
0083 { .n = "aestdessha_clk", .id = 28, },
0084 { .n = "mci1_clk", .id = 29, },
0085 { .n = "vdec_clk", .id = 30, },
0086 };
0087
0088 static void __init at91sam9g45_pmc_setup(struct device_node *np)
0089 {
0090 const char *slck_name, *mainxtal_name;
0091 struct pmc_data *at91sam9g45_pmc;
0092 const char *parent_names[6];
0093 struct regmap *regmap;
0094 struct clk_hw *hw;
0095 int i;
0096 bool bypass;
0097
0098 i = of_property_match_string(np, "clock-names", "slow_clk");
0099 if (i < 0)
0100 return;
0101
0102 slck_name = of_clk_get_parent_name(np, i);
0103
0104 i = of_property_match_string(np, "clock-names", "main_xtal");
0105 if (i < 0)
0106 return;
0107 mainxtal_name = of_clk_get_parent_name(np, i);
0108
0109 regmap = device_node_to_regmap(np);
0110 if (IS_ERR(regmap))
0111 return;
0112
0113 at91sam9g45_pmc = pmc_data_allocate(PMC_PLLACK + 1,
0114 nck(at91sam9g45_systemck),
0115 nck(at91sam9g45_periphck), 0, 2);
0116 if (!at91sam9g45_pmc)
0117 return;
0118
0119 bypass = of_property_read_bool(np, "atmel,osc-bypass");
0120
0121 hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name,
0122 bypass);
0123 if (IS_ERR(hw))
0124 goto err_free;
0125
0126 hw = at91_clk_register_rm9200_main(regmap, "mainck", "main_osc");
0127 if (IS_ERR(hw))
0128 goto err_free;
0129
0130 at91sam9g45_pmc->chws[PMC_MAIN] = hw;
0131
0132 hw = at91_clk_register_pll(regmap, "pllack", "mainck", 0,
0133 &at91rm9200_pll_layout, &plla_characteristics);
0134 if (IS_ERR(hw))
0135 goto err_free;
0136
0137 hw = at91_clk_register_plldiv(regmap, "plladivck", "pllack");
0138 if (IS_ERR(hw))
0139 goto err_free;
0140
0141 at91sam9g45_pmc->chws[PMC_PLLACK] = hw;
0142
0143 hw = at91_clk_register_utmi(regmap, NULL, "utmick", "mainck");
0144 if (IS_ERR(hw))
0145 goto err_free;
0146
0147 at91sam9g45_pmc->chws[PMC_UTMI] = hw;
0148
0149 parent_names[0] = slck_name;
0150 parent_names[1] = "mainck";
0151 parent_names[2] = "plladivck";
0152 parent_names[3] = "utmick";
0153 hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4,
0154 parent_names,
0155 &at91rm9200_master_layout,
0156 &mck_characteristics,
0157 &at91sam9g45_mck_lock);
0158 if (IS_ERR(hw))
0159 goto err_free;
0160
0161 hw = at91_clk_register_master_div(regmap, "masterck_div",
0162 "masterck_pres",
0163 &at91rm9200_master_layout,
0164 &mck_characteristics,
0165 &at91sam9g45_mck_lock,
0166 CLK_SET_RATE_GATE, 0);
0167 if (IS_ERR(hw))
0168 goto err_free;
0169
0170 at91sam9g45_pmc->chws[PMC_MCK] = hw;
0171
0172 parent_names[0] = "plladivck";
0173 parent_names[1] = "utmick";
0174 hw = at91sam9x5_clk_register_usb(regmap, "usbck", parent_names, 2);
0175 if (IS_ERR(hw))
0176 goto err_free;
0177
0178 parent_names[0] = slck_name;
0179 parent_names[1] = "mainck";
0180 parent_names[2] = "plladivck";
0181 parent_names[3] = "utmick";
0182 parent_names[4] = "masterck_div";
0183 for (i = 0; i < 2; i++) {
0184 char name[6];
0185
0186 snprintf(name, sizeof(name), "prog%d", i);
0187
0188 hw = at91_clk_register_programmable(regmap, name,
0189 parent_names, 5, i,
0190 &at91sam9g45_programmable_layout,
0191 NULL);
0192 if (IS_ERR(hw))
0193 goto err_free;
0194
0195 at91sam9g45_pmc->pchws[i] = hw;
0196 }
0197
0198 for (i = 0; i < ARRAY_SIZE(at91sam9g45_systemck); i++) {
0199 hw = at91_clk_register_system(regmap, at91sam9g45_systemck[i].n,
0200 at91sam9g45_systemck[i].p,
0201 at91sam9g45_systemck[i].id);
0202 if (IS_ERR(hw))
0203 goto err_free;
0204
0205 at91sam9g45_pmc->shws[at91sam9g45_systemck[i].id] = hw;
0206 }
0207
0208 for (i = 0; i < ARRAY_SIZE(at91sam9g45_periphck); i++) {
0209 hw = at91_clk_register_peripheral(regmap,
0210 at91sam9g45_periphck[i].n,
0211 "masterck_div",
0212 at91sam9g45_periphck[i].id);
0213 if (IS_ERR(hw))
0214 goto err_free;
0215
0216 at91sam9g45_pmc->phws[at91sam9g45_periphck[i].id] = hw;
0217 }
0218
0219 of_clk_add_hw_provider(np, of_clk_hw_pmc_get, at91sam9g45_pmc);
0220
0221 return;
0222
0223 err_free:
0224 kfree(at91sam9g45_pmc);
0225 }
0226
0227
0228
0229
0230 CLK_OF_DECLARE(at91sam9g45_pmc, "atmel,at91sam9g45-pmc", at91sam9g45_pmc_setup);
