0001
0002 #include <linux/clk-provider.h>
0003 #include <linux/mfd/syscon.h>
0004 #include <linux/slab.h>
0005
0006 #include <dt-bindings/clock/at91.h>
0007
0008 #include "pmc.h"
0009
0010 struct sck {
0011 char *n;
0012 char *p;
0013 u8 id;
0014 };
0015
0016 struct pck {
0017 char *n;
0018 u8 id;
0019 };
0020
0021 struct at91sam926x_data {
0022 const struct clk_pll_layout *plla_layout;
0023 const struct clk_pll_characteristics *plla_characteristics;
0024 const struct clk_pll_layout *pllb_layout;
0025 const struct clk_pll_characteristics *pllb_characteristics;
0026 const struct clk_master_characteristics *mck_characteristics;
0027 const struct sck *sck;
0028 const struct pck *pck;
0029 u8 num_sck;
0030 u8 num_pck;
0031 u8 num_progck;
0032 bool has_slck;
0033 };
0034
0035 static DEFINE_SPINLOCK(at91sam9260_mck_lock);
0036
0037 static const struct clk_master_characteristics sam9260_mck_characteristics = {
0038 .output = { .min = 0, .max = 105000000 },
0039 .divisors = { 1, 2, 4, 0 },
0040 };
0041
0042 static u8 sam9260_plla_out[] = { 0, 2 };
0043
0044 static u16 sam9260_plla_icpll[] = { 1, 1 };
0045
0046 static const struct clk_range sam9260_plla_outputs[] = {
0047 { .min = 80000000, .max = 160000000 },
0048 { .min = 150000000, .max = 240000000 },
0049 };
0050
0051 static const struct clk_pll_characteristics sam9260_plla_characteristics = {
0052 .input = { .min = 1000000, .max = 32000000 },
0053 .num_output = ARRAY_SIZE(sam9260_plla_outputs),
0054 .output = sam9260_plla_outputs,
0055 .icpll = sam9260_plla_icpll,
0056 .out = sam9260_plla_out,
0057 };
0058
0059 static u8 sam9260_pllb_out[] = { 1 };
0060
0061 static u16 sam9260_pllb_icpll[] = { 1 };
0062
0063 static const struct clk_range sam9260_pllb_outputs[] = {
0064 { .min = 70000000, .max = 130000000 },
0065 };
0066
0067 static const struct clk_pll_characteristics sam9260_pllb_characteristics = {
0068 .input = { .min = 1000000, .max = 5000000 },
0069 .num_output = ARRAY_SIZE(sam9260_pllb_outputs),
0070 .output = sam9260_pllb_outputs,
0071 .icpll = sam9260_pllb_icpll,
0072 .out = sam9260_pllb_out,
0073 };
0074
0075 static const struct sck at91sam9260_systemck[] = {
0076 { .n = "uhpck", .p = "usbck", .id = 6 },
0077 { .n = "udpck", .p = "usbck", .id = 7 },
0078 { .n = "pck0", .p = "prog0", .id = 8 },
0079 { .n = "pck1", .p = "prog1", .id = 9 },
0080 };
0081
0082 static const struct pck at91sam9260_periphck[] = {
0083 { .n = "pioA_clk", .id = 2 },
0084 { .n = "pioB_clk", .id = 3 },
0085 { .n = "pioC_clk", .id = 4 },
0086 { .n = "adc_clk", .id = 5 },
0087 { .n = "usart0_clk", .id = 6 },
0088 { .n = "usart1_clk", .id = 7 },
0089 { .n = "usart2_clk", .id = 8 },
0090 { .n = "mci0_clk", .id = 9 },
0091 { .n = "udc_clk", .id = 10 },
0092 { .n = "twi0_clk", .id = 11 },
0093 { .n = "spi0_clk", .id = 12 },
0094 { .n = "spi1_clk", .id = 13 },
0095 { .n = "ssc0_clk", .id = 14 },
0096 { .n = "tc0_clk", .id = 17 },
0097 { .n = "tc1_clk", .id = 18 },
0098 { .n = "tc2_clk", .id = 19 },
0099 { .n = "ohci_clk", .id = 20 },
0100 { .n = "macb0_clk", .id = 21 },
0101 { .n = "isi_clk", .id = 22 },
0102 { .n = "usart3_clk", .id = 23 },
0103 { .n = "uart0_clk", .id = 24 },
0104 { .n = "uart1_clk", .id = 25 },
0105 { .n = "tc3_clk", .id = 26 },
0106 { .n = "tc4_clk", .id = 27 },
0107 { .n = "tc5_clk", .id = 28 },
0108 };
0109
0110 static struct at91sam926x_data at91sam9260_data = {
0111 .plla_layout = &at91rm9200_pll_layout,
0112 .plla_characteristics = &sam9260_plla_characteristics,
0113 .pllb_layout = &at91rm9200_pll_layout,
0114 .pllb_characteristics = &sam9260_pllb_characteristics,
0115 .mck_characteristics = &sam9260_mck_characteristics,
0116 .sck = at91sam9260_systemck,
0117 .num_sck = ARRAY_SIZE(at91sam9260_systemck),
0118 .pck = at91sam9260_periphck,
0119 .num_pck = ARRAY_SIZE(at91sam9260_periphck),
0120 .num_progck = 2,
0121 .has_slck = true,
0122 };
0123
0124 static const struct clk_master_characteristics sam9g20_mck_characteristics = {
0125 .output = { .min = 0, .max = 133000000 },
0126 .divisors = { 1, 2, 4, 6 },
0127 };
0128
0129 static u8 sam9g20_plla_out[] = { 0, 1, 2, 3, 0, 1, 2, 3 };
0130
0131 static u16 sam9g20_plla_icpll[] = { 0, 0, 0, 0, 1, 1, 1, 1 };
0132
0133 static const struct clk_range sam9g20_plla_outputs[] = {
0134 { .min = 745000000, .max = 800000000 },
0135 { .min = 695000000, .max = 750000000 },
0136 { .min = 645000000, .max = 700000000 },
0137 { .min = 595000000, .max = 650000000 },
0138 { .min = 545000000, .max = 600000000 },
0139 { .min = 495000000, .max = 550000000 },
0140 { .min = 445000000, .max = 500000000 },
0141 { .min = 400000000, .max = 450000000 },
0142 };
0143
0144 static const struct clk_pll_characteristics sam9g20_plla_characteristics = {
0145 .input = { .min = 2000000, .max = 32000000 },
0146 .num_output = ARRAY_SIZE(sam9g20_plla_outputs),
0147 .output = sam9g20_plla_outputs,
0148 .icpll = sam9g20_plla_icpll,
0149 .out = sam9g20_plla_out,
0150 };
0151
0152 static u8 sam9g20_pllb_out[] = { 0 };
0153
0154 static u16 sam9g20_pllb_icpll[] = { 0 };
0155
0156 static const struct clk_range sam9g20_pllb_outputs[] = {
0157 { .min = 30000000, .max = 100000000 },
0158 };
0159
0160 static const struct clk_pll_characteristics sam9g20_pllb_characteristics = {
0161 .input = { .min = 2000000, .max = 32000000 },
0162 .num_output = ARRAY_SIZE(sam9g20_pllb_outputs),
0163 .output = sam9g20_pllb_outputs,
0164 .icpll = sam9g20_pllb_icpll,
0165 .out = sam9g20_pllb_out,
0166 };
0167
0168 static struct at91sam926x_data at91sam9g20_data = {
0169 .plla_layout = &at91sam9g45_pll_layout,
0170 .plla_characteristics = &sam9g20_plla_characteristics,
0171 .pllb_layout = &at91sam9g20_pllb_layout,
0172 .pllb_characteristics = &sam9g20_pllb_characteristics,
0173 .mck_characteristics = &sam9g20_mck_characteristics,
0174 .sck = at91sam9260_systemck,
0175 .num_sck = ARRAY_SIZE(at91sam9260_systemck),
0176 .pck = at91sam9260_periphck,
0177 .num_pck = ARRAY_SIZE(at91sam9260_periphck),
0178 .num_progck = 2,
0179 .has_slck = true,
0180 };
0181
0182 static const struct clk_master_characteristics sam9261_mck_characteristics = {
0183 .output = { .min = 0, .max = 94000000 },
0184 .divisors = { 1, 2, 4, 0 },
0185 };
0186
0187 static const struct clk_range sam9261_plla_outputs[] = {
0188 { .min = 80000000, .max = 200000000 },
0189 { .min = 190000000, .max = 240000000 },
0190 };
0191
0192 static const struct clk_pll_characteristics sam9261_plla_characteristics = {
0193 .input = { .min = 1000000, .max = 32000000 },
0194 .num_output = ARRAY_SIZE(sam9261_plla_outputs),
0195 .output = sam9261_plla_outputs,
0196 .icpll = sam9260_plla_icpll,
0197 .out = sam9260_plla_out,
0198 };
0199
0200 static u8 sam9261_pllb_out[] = { 1 };
0201
0202 static u16 sam9261_pllb_icpll[] = { 1 };
0203
0204 static const struct clk_range sam9261_pllb_outputs[] = {
0205 { .min = 70000000, .max = 130000000 },
0206 };
0207
0208 static const struct clk_pll_characteristics sam9261_pllb_characteristics = {
0209 .input = { .min = 1000000, .max = 5000000 },
0210 .num_output = ARRAY_SIZE(sam9261_pllb_outputs),
0211 .output = sam9261_pllb_outputs,
0212 .icpll = sam9261_pllb_icpll,
0213 .out = sam9261_pllb_out,
0214 };
0215
0216 static const struct sck at91sam9261_systemck[] = {
0217 { .n = "uhpck", .p = "usbck", .id = 6 },
0218 { .n = "udpck", .p = "usbck", .id = 7 },
0219 { .n = "pck0", .p = "prog0", .id = 8 },
0220 { .n = "pck1", .p = "prog1", .id = 9 },
0221 { .n = "pck2", .p = "prog2", .id = 10 },
0222 { .n = "pck3", .p = "prog3", .id = 11 },
0223 { .n = "hclk0", .p = "masterck_div", .id = 16 },
0224 { .n = "hclk1", .p = "masterck_div", .id = 17 },
0225 };
0226
0227 static const struct pck at91sam9261_periphck[] = {
0228 { .n = "pioA_clk", .id = 2, },
0229 { .n = "pioB_clk", .id = 3, },
0230 { .n = "pioC_clk", .id = 4, },
0231 { .n = "usart0_clk", .id = 6, },
0232 { .n = "usart1_clk", .id = 7, },
0233 { .n = "usart2_clk", .id = 8, },
0234 { .n = "mci0_clk", .id = 9, },
0235 { .n = "udc_clk", .id = 10, },
0236 { .n = "twi0_clk", .id = 11, },
0237 { .n = "spi0_clk", .id = 12, },
0238 { .n = "spi1_clk", .id = 13, },
0239 { .n = "ssc0_clk", .id = 14, },
0240 { .n = "ssc1_clk", .id = 15, },
0241 { .n = "ssc2_clk", .id = 16, },
0242 { .n = "tc0_clk", .id = 17, },
0243 { .n = "tc1_clk", .id = 18, },
0244 { .n = "tc2_clk", .id = 19, },
0245 { .n = "ohci_clk", .id = 20, },
0246 { .n = "lcd_clk", .id = 21, },
0247 };
0248
0249 static struct at91sam926x_data at91sam9261_data = {
0250 .plla_layout = &at91rm9200_pll_layout,
0251 .plla_characteristics = &sam9261_plla_characteristics,
0252 .pllb_layout = &at91rm9200_pll_layout,
0253 .pllb_characteristics = &sam9261_pllb_characteristics,
0254 .mck_characteristics = &sam9261_mck_characteristics,
0255 .sck = at91sam9261_systemck,
0256 .num_sck = ARRAY_SIZE(at91sam9261_systemck),
0257 .pck = at91sam9261_periphck,
0258 .num_pck = ARRAY_SIZE(at91sam9261_periphck),
0259 .num_progck = 4,
0260 };
0261
0262 static const struct clk_master_characteristics sam9263_mck_characteristics = {
0263 .output = { .min = 0, .max = 120000000 },
0264 .divisors = { 1, 2, 4, 0 },
0265 };
0266
0267 static const struct clk_range sam9263_pll_outputs[] = {
0268 { .min = 80000000, .max = 200000000 },
0269 { .min = 190000000, .max = 240000000 },
0270 };
0271
0272 static const struct clk_pll_characteristics sam9263_pll_characteristics = {
0273 .input = { .min = 1000000, .max = 32000000 },
0274 .num_output = ARRAY_SIZE(sam9263_pll_outputs),
0275 .output = sam9263_pll_outputs,
0276 .icpll = sam9260_plla_icpll,
0277 .out = sam9260_plla_out,
0278 };
0279
0280 static const struct sck at91sam9263_systemck[] = {
0281 { .n = "uhpck", .p = "usbck", .id = 6 },
0282 { .n = "udpck", .p = "usbck", .id = 7 },
0283 { .n = "pck0", .p = "prog0", .id = 8 },
0284 { .n = "pck1", .p = "prog1", .id = 9 },
0285 { .n = "pck2", .p = "prog2", .id = 10 },
0286 { .n = "pck3", .p = "prog3", .id = 11 },
0287 };
0288
0289 static const struct pck at91sam9263_periphck[] = {
0290 { .n = "pioA_clk", .id = 2, },
0291 { .n = "pioB_clk", .id = 3, },
0292 { .n = "pioCDE_clk", .id = 4, },
0293 { .n = "usart0_clk", .id = 7, },
0294 { .n = "usart1_clk", .id = 8, },
0295 { .n = "usart2_clk", .id = 9, },
0296 { .n = "mci0_clk", .id = 10, },
0297 { .n = "mci1_clk", .id = 11, },
0298 { .n = "can_clk", .id = 12, },
0299 { .n = "twi0_clk", .id = 13, },
0300 { .n = "spi0_clk", .id = 14, },
0301 { .n = "spi1_clk", .id = 15, },
0302 { .n = "ssc0_clk", .id = 16, },
0303 { .n = "ssc1_clk", .id = 17, },
0304 { .n = "ac97_clk", .id = 18, },
0305 { .n = "tcb_clk", .id = 19, },
0306 { .n = "pwm_clk", .id = 20, },
0307 { .n = "macb0_clk", .id = 21, },
0308 { .n = "g2de_clk", .id = 23, },
0309 { .n = "udc_clk", .id = 24, },
0310 { .n = "isi_clk", .id = 25, },
0311 { .n = "lcd_clk", .id = 26, },
0312 { .n = "dma_clk", .id = 27, },
0313 { .n = "ohci_clk", .id = 29, },
0314 };
0315
0316 static struct at91sam926x_data at91sam9263_data = {
0317 .plla_layout = &at91rm9200_pll_layout,
0318 .plla_characteristics = &sam9263_pll_characteristics,
0319 .pllb_layout = &at91rm9200_pll_layout,
0320 .pllb_characteristics = &sam9263_pll_characteristics,
0321 .mck_characteristics = &sam9263_mck_characteristics,
0322 .sck = at91sam9263_systemck,
0323 .num_sck = ARRAY_SIZE(at91sam9263_systemck),
0324 .pck = at91sam9263_periphck,
0325 .num_pck = ARRAY_SIZE(at91sam9263_periphck),
0326 .num_progck = 4,
0327 };
0328
0329 static void __init at91sam926x_pmc_setup(struct device_node *np,
0330 struct at91sam926x_data *data)
0331 {
0332 const char *slowxtal_name, *mainxtal_name;
0333 struct pmc_data *at91sam9260_pmc;
0334 u32 usb_div[] = { 1, 2, 4, 0 };
0335 const char *parent_names[6];
0336 const char *slck_name;
0337 struct regmap *regmap;
0338 struct clk_hw *hw;
0339 int i;
0340 bool bypass;
0341
0342 i = of_property_match_string(np, "clock-names", "slow_xtal");
0343 if (i < 0)
0344 return;
0345
0346 slowxtal_name = of_clk_get_parent_name(np, i);
0347
0348 i = of_property_match_string(np, "clock-names", "main_xtal");
0349 if (i < 0)
0350 return;
0351 mainxtal_name = of_clk_get_parent_name(np, i);
0352
0353 regmap = device_node_to_regmap(np);
0354 if (IS_ERR(regmap))
0355 return;
0356
0357 at91sam9260_pmc = pmc_data_allocate(PMC_PLLBCK + 1,
0358 ndck(data->sck, data->num_sck),
0359 ndck(data->pck, data->num_pck),
0360 0, data->num_progck);
0361 if (!at91sam9260_pmc)
0362 return;
0363
0364 bypass = of_property_read_bool(np, "atmel,osc-bypass");
0365
0366 hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name,
0367 bypass);
0368 if (IS_ERR(hw))
0369 goto err_free;
0370
0371 hw = at91_clk_register_rm9200_main(regmap, "mainck", "main_osc");
0372 if (IS_ERR(hw))
0373 goto err_free;
0374
0375 at91sam9260_pmc->chws[PMC_MAIN] = hw;
0376
0377 if (data->has_slck) {
0378 hw = clk_hw_register_fixed_rate_with_accuracy(NULL,
0379 "slow_rc_osc",
0380 NULL, 0, 32768,
0381 50000000);
0382 if (IS_ERR(hw))
0383 goto err_free;
0384
0385 parent_names[0] = "slow_rc_osc";
0386 parent_names[1] = "slow_xtal";
0387 hw = at91_clk_register_sam9260_slow(regmap, "slck",
0388 parent_names, 2);
0389 if (IS_ERR(hw))
0390 goto err_free;
0391
0392 at91sam9260_pmc->chws[PMC_SLOW] = hw;
0393 slck_name = "slck";
0394 } else {
0395 slck_name = slowxtal_name;
0396 }
0397
0398 hw = at91_clk_register_pll(regmap, "pllack", "mainck", 0,
0399 data->plla_layout,
0400 data->plla_characteristics);
0401 if (IS_ERR(hw))
0402 goto err_free;
0403
0404 at91sam9260_pmc->chws[PMC_PLLACK] = hw;
0405
0406 hw = at91_clk_register_pll(regmap, "pllbck", "mainck", 1,
0407 data->pllb_layout,
0408 data->pllb_characteristics);
0409 if (IS_ERR(hw))
0410 goto err_free;
0411
0412 at91sam9260_pmc->chws[PMC_PLLBCK] = hw;
0413
0414 parent_names[0] = slck_name;
0415 parent_names[1] = "mainck";
0416 parent_names[2] = "pllack";
0417 parent_names[3] = "pllbck";
0418 hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4,
0419 parent_names,
0420 &at91rm9200_master_layout,
0421 data->mck_characteristics,
0422 &at91sam9260_mck_lock);
0423 if (IS_ERR(hw))
0424 goto err_free;
0425
0426 hw = at91_clk_register_master_div(regmap, "masterck_div",
0427 "masterck_pres",
0428 &at91rm9200_master_layout,
0429 data->mck_characteristics,
0430 &at91sam9260_mck_lock,
0431 CLK_SET_RATE_GATE, 0);
0432 if (IS_ERR(hw))
0433 goto err_free;
0434
0435 at91sam9260_pmc->chws[PMC_MCK] = hw;
0436
0437 hw = at91rm9200_clk_register_usb(regmap, "usbck", "pllbck", usb_div);
0438 if (IS_ERR(hw))
0439 goto err_free;
0440
0441 parent_names[0] = slck_name;
0442 parent_names[1] = "mainck";
0443 parent_names[2] = "pllack";
0444 parent_names[3] = "pllbck";
0445 for (i = 0; i < data->num_progck; i++) {
0446 char name[6];
0447
0448 snprintf(name, sizeof(name), "prog%d", i);
0449
0450 hw = at91_clk_register_programmable(regmap, name,
0451 parent_names, 4, i,
0452 &at91rm9200_programmable_layout,
0453 NULL);
0454 if (IS_ERR(hw))
0455 goto err_free;
0456
0457 at91sam9260_pmc->pchws[i] = hw;
0458 }
0459
0460 for (i = 0; i < data->num_sck; i++) {
0461 hw = at91_clk_register_system(regmap, data->sck[i].n,
0462 data->sck[i].p,
0463 data->sck[i].id);
0464 if (IS_ERR(hw))
0465 goto err_free;
0466
0467 at91sam9260_pmc->shws[data->sck[i].id] = hw;
0468 }
0469
0470 for (i = 0; i < data->num_pck; i++) {
0471 hw = at91_clk_register_peripheral(regmap,
0472 data->pck[i].n,
0473 "masterck_div",
0474 data->pck[i].id);
0475 if (IS_ERR(hw))
0476 goto err_free;
0477
0478 at91sam9260_pmc->phws[data->pck[i].id] = hw;
0479 }
0480
0481 of_clk_add_hw_provider(np, of_clk_hw_pmc_get, at91sam9260_pmc);
0482
0483 return;
0484
0485 err_free:
0486 kfree(at91sam9260_pmc);
0487 }
0488
0489 static void __init at91sam9260_pmc_setup(struct device_node *np)
0490 {
0491 at91sam926x_pmc_setup(np, &at91sam9260_data);
0492 }
0493
0494 CLK_OF_DECLARE(at91sam9260_pmc, "atmel,at91sam9260-pmc", at91sam9260_pmc_setup);
0495
0496 static void __init at91sam9261_pmc_setup(struct device_node *np)
0497 {
0498 at91sam926x_pmc_setup(np, &at91sam9261_data);
0499 }
0500
0501 CLK_OF_DECLARE(at91sam9261_pmc, "atmel,at91sam9261-pmc", at91sam9261_pmc_setup);
0502
0503 static void __init at91sam9263_pmc_setup(struct device_node *np)
0504 {
0505 at91sam926x_pmc_setup(np, &at91sam9263_data);
0506 }
0507
0508 CLK_OF_DECLARE(at91sam9263_pmc, "atmel,at91sam9263-pmc", at91sam9263_pmc_setup);
0509
0510 static void __init at91sam9g20_pmc_setup(struct device_node *np)
0511 {
0512 at91sam926x_pmc_setup(np, &at91sam9g20_data);
0513 }
0514
0515 CLK_OF_DECLARE(at91sam9g20_pmc, "atmel,at91sam9g20-pmc", at91sam9g20_pmc_setup);
