clk/at91/at91rm9200.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 #include <linux/clk-provider.h>
0003 #include <linux/mfd/syscon.h>
0004 #include <linux/slab.h>
0005
0006 #include <dt-bindings/clock/at91.h>
0007
0008 #include "pmc.h"
0009
0010 static DEFINE_SPINLOCK(rm9200_mck_lock);
0011
0012 struct sck {
0013     char *n;
0014     char *p;
0015     u8 id;
0016 };
0017
0018 struct pck {
0019     char *n;
0020     u8 id;
0021 };
0022
0023 static const struct clk_master_characteristics rm9200_mck_characteristics = {
0024     .output = { .min = 0, .max = 80000000 },
0025     .divisors = { 1, 2, 3, 4 },
0026 };
0027
0028 static u8 rm9200_pll_out[] = { 0, 2 };
0029
0030 static const struct clk_range rm9200_pll_outputs[] = {
0031     { .min = 80000000, .max = 160000000 },
0032     { .min = 150000000, .max = 180000000 },
0033 };
0034
0035 static const struct clk_pll_characteristics rm9200_pll_characteristics = {
0036     .input = { .min = 1000000, .max = 32000000 },
0037     .num_output = ARRAY_SIZE(rm9200_pll_outputs),
0038     .output = rm9200_pll_outputs,
0039     .out = rm9200_pll_out,
0040 };
0041
0042 static const struct sck at91rm9200_systemck[] = {
0043     { .n = "udpck", .p = "usbck",    .id = 2 },
0044     { .n = "uhpck", .p = "usbck",    .id = 4 },
0045     { .n = "pck0",  .p = "prog0",    .id = 8 },
0046     { .n = "pck1",  .p = "prog1",    .id = 9 },
0047     { .n = "pck2",  .p = "prog2",    .id = 10 },
0048     { .n = "pck3",  .p = "prog3",    .id = 11 },
0049 };
0050
0051 static const struct pck at91rm9200_periphck[] = {
0052     { .n = "pioA_clk",   .id = 2 },
0053     { .n = "pioB_clk",   .id = 3 },
0054     { .n = "pioC_clk",   .id = 4 },
0055     { .n = "pioD_clk",   .id = 5 },
0056     { .n = "usart0_clk", .id = 6 },
0057     { .n = "usart1_clk", .id = 7 },
0058     { .n = "usart2_clk", .id = 8 },
0059     { .n = "usart3_clk", .id = 9 },
0060     { .n = "mci0_clk",   .id = 10 },
0061     { .n = "udc_clk",    .id = 11 },
0062     { .n = "twi0_clk",   .id = 12 },
0063     { .n = "spi0_clk",   .id = 13 },
0064     { .n = "ssc0_clk",   .id = 14 },
0065     { .n = "ssc1_clk",   .id = 15 },
0066     { .n = "ssc2_clk",   .id = 16 },
0067     { .n = "tc0_clk",    .id = 17 },
0068     { .n = "tc1_clk",    .id = 18 },
0069     { .n = "tc2_clk",    .id = 19 },
0070     { .n = "tc3_clk",    .id = 20 },
0071     { .n = "tc4_clk",    .id = 21 },
0072     { .n = "tc5_clk",    .id = 22 },
0073     { .n = "ohci_clk",   .id = 23 },
0074     { .n = "macb0_clk",  .id = 24 },
0075 };
0076
0077 static void __init at91rm9200_pmc_setup(struct device_node *np)
0078 {
0079     const char *slowxtal_name, *mainxtal_name;
0080     struct pmc_data *at91rm9200_pmc;
0081     u32 usb_div[] = { 1, 2, 0, 0 };
0082     const char *parent_names[6];
0083     struct regmap *regmap;
0084     struct clk_hw *hw;
0085     int i;
0086     bool bypass;
0087
0088     i = of_property_match_string(np, "clock-names", "slow_xtal");
0089     if (i < 0)
0090         return;
0091
0092     slowxtal_name = of_clk_get_parent_name(np, i);
0093
0094     i = of_property_match_string(np, "clock-names", "main_xtal");
0095     if (i < 0)
0096         return;
0097     mainxtal_name = of_clk_get_parent_name(np, i);
0098
0099     regmap = device_node_to_regmap(np);
0100     if (IS_ERR(regmap))
0101         return;
0102
0103     at91rm9200_pmc = pmc_data_allocate(PMC_PLLBCK + 1,
0104                         nck(at91rm9200_systemck),
0105                         nck(at91rm9200_periphck), 0, 4);
0106     if (!at91rm9200_pmc)
0107         return;
0108
0109     bypass = of_property_read_bool(np, "atmel,osc-bypass");
0110
0111     hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name,
0112                     bypass);
0113     if (IS_ERR(hw))
0114         goto err_free;
0115
0116     hw = at91_clk_register_rm9200_main(regmap, "mainck", "main_osc");
0117     if (IS_ERR(hw))
0118         goto err_free;
0119
0120     at91rm9200_pmc->chws[PMC_MAIN] = hw;
0121
0122     hw = at91_clk_register_pll(regmap, "pllack", "mainck", 0,
0123                    &at91rm9200_pll_layout,
0124                    &rm9200_pll_characteristics);
0125     if (IS_ERR(hw))
0126         goto err_free;
0127
0128     at91rm9200_pmc->chws[PMC_PLLACK] = hw;
0129
0130     hw = at91_clk_register_pll(regmap, "pllbck", "mainck", 1,
0131                    &at91rm9200_pll_layout,
0132                    &rm9200_pll_characteristics);
0133     if (IS_ERR(hw))
0134         goto err_free;
0135
0136     at91rm9200_pmc->chws[PMC_PLLBCK] = hw;
0137
0138     parent_names[0] = slowxtal_name;
0139     parent_names[1] = "mainck";
0140     parent_names[2] = "pllack";
0141     parent_names[3] = "pllbck";
0142     hw = at91_clk_register_master_pres(regmap, "masterck_pres", 4,
0143                        parent_names,
0144                        &at91rm9200_master_layout,
0145                        &rm9200_mck_characteristics,
0146                        &rm9200_mck_lock);
0147     if (IS_ERR(hw))
0148         goto err_free;
0149
0150     hw = at91_clk_register_master_div(regmap, "masterck_div",
0151                       "masterck_pres",
0152                       &at91rm9200_master_layout,
0153                       &rm9200_mck_characteristics,
0154                       &rm9200_mck_lock, CLK_SET_RATE_GATE, 0);
0155     if (IS_ERR(hw))
0156         goto err_free;
0157
0158     at91rm9200_pmc->chws[PMC_MCK] = hw;
0159
0160     hw = at91rm9200_clk_register_usb(regmap, "usbck", "pllbck", usb_div);
0161     if (IS_ERR(hw))
0162         goto err_free;
0163
0164     parent_names[0] = slowxtal_name;
0165     parent_names[1] = "mainck";
0166     parent_names[2] = "pllack";
0167     parent_names[3] = "pllbck";
0168     for (i = 0; i < 4; i++) {
0169         char name[6];
0170
0171         snprintf(name, sizeof(name), "prog%d", i);
0172
0173         hw = at91_clk_register_programmable(regmap, name,
0174                             parent_names, 4, i,
0175                             &at91rm9200_programmable_layout,
0176                             NULL);
0177         if (IS_ERR(hw))
0178             goto err_free;
0179
0180         at91rm9200_pmc->pchws[i] = hw;
0181     }
0182
0183     for (i = 0; i < ARRAY_SIZE(at91rm9200_systemck); i++) {
0184         hw = at91_clk_register_system(regmap, at91rm9200_systemck[i].n,
0185                           at91rm9200_systemck[i].p,
0186                           at91rm9200_systemck[i].id);
0187         if (IS_ERR(hw))
0188             goto err_free;
0189
0190         at91rm9200_pmc->shws[at91rm9200_systemck[i].id] = hw;
0191     }
0192
0193     for (i = 0; i < ARRAY_SIZE(at91rm9200_periphck); i++) {
0194         hw = at91_clk_register_peripheral(regmap,
0195                           at91rm9200_periphck[i].n,
0196                           "masterck_div",
0197                           at91rm9200_periphck[i].id);
0198         if (IS_ERR(hw))
0199             goto err_free;
0200
0201         at91rm9200_pmc->phws[at91rm9200_periphck[i].id] = hw;
0202     }
0203
0204     of_clk_add_hw_provider(np, of_clk_hw_pmc_get, at91rm9200_pmc);
0205
0206     return;
0207
0208 err_free:
0209     kfree(at91rm9200_pmc);
0210 }
0211 /*
0212  * While the TCB can be used as the clocksource, the system timer is most likely
0213  * to be used instead. However, the pinctrl driver doesn't support probe
0214  * deferring properly. Once this is fixed, this can be switched to a platform
0215  * driver.
0216  */
0217 CLK_OF_DECLARE(at91rm9200_pmc, "atmel,at91rm9200-pmc", at91rm9200_pmc_setup);