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0011 #include <linux/clk-provider.h>
0012 #include <linux/platform_device.h>
0013
0014 #include "owl-common.h"
0015 #include "owl-composite.h"
0016 #include "owl-divider.h"
0017 #include "owl-factor.h"
0018 #include "owl-fixed-factor.h"
0019 #include "owl-gate.h"
0020 #include "owl-mux.h"
0021 #include "owl-pll.h"
0022 #include "owl-reset.h"
0023
0024 #include <dt-bindings/clock/actions,s900-cmu.h>
0025 #include <dt-bindings/reset/actions,s900-reset.h>
0026
0027 #define CMU_COREPLL (0x0000)
0028 #define CMU_DEVPLL (0x0004)
0029 #define CMU_DDRPLL (0x0008)
0030 #define CMU_NANDPLL (0x000C)
0031 #define CMU_DISPLAYPLL (0x0010)
0032 #define CMU_AUDIOPLL (0x0014)
0033 #define CMU_TVOUTPLL (0x0018)
0034 #define CMU_BUSCLK (0x001C)
0035 #define CMU_SENSORCLK (0x0020)
0036 #define CMU_LCDCLK (0x0024)
0037 #define CMU_DSICLK (0x0028)
0038 #define CMU_CSICLK (0x002C)
0039 #define CMU_DECLK (0x0030)
0040 #define CMU_BISPCLK (0x0034)
0041 #define CMU_IMXCLK (0x0038)
0042 #define CMU_HDECLK (0x003C)
0043 #define CMU_VDECLK (0x0040)
0044 #define CMU_VCECLK (0x0044)
0045 #define CMU_NANDCCLK (0x004C)
0046 #define CMU_SD0CLK (0x0050)
0047 #define CMU_SD1CLK (0x0054)
0048 #define CMU_SD2CLK (0x0058)
0049 #define CMU_UART0CLK (0x005C)
0050 #define CMU_UART1CLK (0x0060)
0051 #define CMU_UART2CLK (0x0064)
0052 #define CMU_PWM0CLK (0x0070)
0053 #define CMU_PWM1CLK (0x0074)
0054 #define CMU_PWM2CLK (0x0078)
0055 #define CMU_PWM3CLK (0x007C)
0056 #define CMU_USBPLL (0x0080)
0057 #define CMU_ASSISTPLL (0x0084)
0058 #define CMU_EDPCLK (0x0088)
0059 #define CMU_GPU3DCLK (0x0090)
0060 #define CMU_CORECTL (0x009C)
0061 #define CMU_DEVCLKEN0 (0x00A0)
0062 #define CMU_DEVCLKEN1 (0x00A4)
0063 #define CMU_DEVRST0 (0x00A8)
0064 #define CMU_DEVRST1 (0x00AC)
0065 #define CMU_UART3CLK (0x00B0)
0066 #define CMU_UART4CLK (0x00B4)
0067 #define CMU_UART5CLK (0x00B8)
0068 #define CMU_UART6CLK (0x00BC)
0069 #define CMU_TLSCLK (0x00C0)
0070 #define CMU_SD3CLK (0x00C4)
0071 #define CMU_PWM4CLK (0x00C8)
0072 #define CMU_PWM5CLK (0x00CC)
0073
0074 static struct clk_pll_table clk_audio_pll_table[] = {
0075 { 0, 45158400 }, { 1, 49152000 },
0076 { }
0077 };
0078
0079 static struct clk_pll_table clk_edp_pll_table[] = {
0080 { 0, 810000000 }, { 1, 135000000 }, { 2, 270000000 },
0081 { }
0082 };
0083
0084
0085 static OWL_PLL_NO_PARENT(core_pll_clk, "core_pll_clk", CMU_COREPLL, 24000000, 9, 0, 8, 5, 107, NULL, CLK_IGNORE_UNUSED);
0086 static OWL_PLL_NO_PARENT(dev_pll_clk, "dev_pll_clk", CMU_DEVPLL, 6000000, 8, 0, 8, 20, 180, NULL, CLK_IGNORE_UNUSED);
0087 static OWL_PLL_NO_PARENT(ddr_pll_clk, "ddr_pll_clk", CMU_DDRPLL, 24000000, 8, 0, 8, 5, 45, NULL, CLK_IGNORE_UNUSED);
0088 static OWL_PLL_NO_PARENT(nand_pll_clk, "nand_pll_clk", CMU_NANDPLL, 6000000, 8, 0, 8, 4, 100, NULL, CLK_IGNORE_UNUSED);
0089 static OWL_PLL_NO_PARENT(display_pll_clk, "display_pll_clk", CMU_DISPLAYPLL, 6000000, 8, 0, 8, 20, 180, NULL, CLK_IGNORE_UNUSED);
0090 static OWL_PLL_NO_PARENT(assist_pll_clk, "assist_pll_clk", CMU_ASSISTPLL, 500000000, 0, 0, 0, 0, 0, NULL, CLK_IGNORE_UNUSED);
0091 static OWL_PLL_NO_PARENT(audio_pll_clk, "audio_pll_clk", CMU_AUDIOPLL, 0, 4, 0, 1, 0, 0, clk_audio_pll_table, CLK_IGNORE_UNUSED);
0092 static OWL_PLL(edp_pll_clk, "edp_pll_clk", "edp24M_clk", CMU_EDPCLK, 0, 9, 0, 2, 0, 0, clk_edp_pll_table, CLK_IGNORE_UNUSED);
0093
0094 static const char *cpu_clk_mux_p[] = { "losc", "hosc", "core_pll_clk", };
0095 static const char *dev_clk_p[] = { "hosc", "dev_pll_clk", };
0096 static const char *noc_clk_mux_p[] = { "dev_clk", "assist_pll_clk", };
0097 static const char *dmm_clk_mux_p[] = { "dev_clk", "nand_pll_clk", "assist_pll_clk", "ddr_clk_src", };
0098 static const char *bisp_clk_mux_p[] = { "assist_pll_clk", "dev_clk", };
0099 static const char *csi_clk_mux_p[] = { "display_pll_clk", "dev_clk", };
0100 static const char *de_clk_mux_p[] = { "assist_pll_clk", "dev_clk", };
0101 static const char *gpu_clk_mux_p[] = { "dev_clk", "display_pll_clk", "ddr_clk_src", };
0102 static const char *hde_clk_mux_p[] = { "dev_clk", "display_pll_clk", "ddr_clk_src", };
0103 static const char *imx_clk_mux_p[] = { "assist_pll_clk", "dev_clk", };
0104 static const char *lcd_clk_mux_p[] = { "display_pll_clk", "nand_pll_clk", };
0105 static const char *nand_clk_mux_p[] = { "dev_clk", "nand_pll_clk", };
0106 static const char *sd_clk_mux_p[] = { "dev_clk", "nand_pll_clk", };
0107 static const char *sensor_clk_mux_p[] = { "hosc", "bisp_clk", };
0108 static const char *uart_clk_mux_p[] = { "hosc", "dev_pll_clk", };
0109 static const char *vce_clk_mux_p[] = { "dev_clk", "display_pll_clk", "assist_pll_clk", "ddr_clk_src", };
0110 static const char *i2s_clk_mux_p[] = { "audio_pll_clk", };
0111 static const char *edp_clk_mux_p[] = { "assist_pll_clk", "display_pll_clk", };
0112
0113
0114 static OWL_MUX(cpu_clk, "cpu_clk", cpu_clk_mux_p, CMU_BUSCLK, 0, 2, CLK_SET_RATE_PARENT);
0115 static OWL_MUX(dev_clk, "dev_clk", dev_clk_p, CMU_DEVPLL, 12, 1, CLK_SET_RATE_PARENT);
0116 static OWL_MUX(noc_clk_mux, "noc_clk_mux", noc_clk_mux_p, CMU_BUSCLK, 7, 1, CLK_SET_RATE_PARENT);
0117
0118 static struct clk_div_table nand_div_table[] = {
0119 { 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 6 },
0120 { 4, 8 }, { 5, 10 }, { 6, 12 }, { 7, 14 },
0121 { 8, 16 }, { 9, 18 }, { 10, 20 }, { 11, 22 },
0122 { 12, 24 }, { 13, 26 }, { 14, 28 }, { 15, 30 },
0123 { }
0124 };
0125
0126 static struct clk_div_table apb_div_table[] = {
0127 { 1, 2 }, { 2, 3 }, { 3, 4 },
0128 { }
0129 };
0130
0131 static struct clk_div_table eth_mac_div_table[] = {
0132 { 0, 2 }, { 1, 4 },
0133 { }
0134 };
0135
0136 static struct clk_div_table rmii_ref_div_table[] = {
0137 { 0, 4 }, { 1, 10 },
0138 { }
0139 };
0140
0141 static struct clk_div_table usb3_mac_div_table[] = {
0142 { 1, 2 }, { 2, 3 }, { 3, 4 },
0143 { }
0144 };
0145
0146 static struct clk_div_table i2s_div_table[] = {
0147 { 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 },
0148 { 4, 6 }, { 5, 8 }, { 6, 12 }, { 7, 16 },
0149 { 8, 24 },
0150 { }
0151 };
0152
0153 static struct clk_div_table hdmia_div_table[] = {
0154 { 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 },
0155 { 4, 6 }, { 5, 8 }, { 6, 12 }, { 7, 16 },
0156 { 8, 24 },
0157 { }
0158 };
0159
0160
0161 static OWL_DIVIDER(noc_clk_div, "noc_clk_div", "noc_clk", CMU_BUSCLK, 19, 1, NULL, 0, 0);
0162 static OWL_DIVIDER(ahb_clk, "ahb_clk", "noc_clk_div", CMU_BUSCLK, 4, 1, NULL, 0, 0);
0163 static OWL_DIVIDER(apb_clk, "apb_clk", "ahb_clk", CMU_BUSCLK, 8, 2, apb_div_table, 0, 0);
0164 static OWL_DIVIDER(usb3_mac_clk, "usb3_mac_clk", "assist_pll_clk", CMU_ASSISTPLL, 12, 2, usb3_mac_div_table, 0, 0);
0165 static OWL_DIVIDER(rmii_ref_clk, "rmii_ref_clk", "assist_pll_clk", CMU_ASSISTPLL, 8, 1, rmii_ref_div_table, 0, 0);
0166
0167 static struct clk_factor_table sd_factor_table[] = {
0168
0169 { 0, 1, 1 }, { 1, 1, 2 }, { 2, 1, 3 }, { 3, 1, 4 },
0170 { 4, 1, 5 }, { 5, 1, 6 }, { 6, 1, 7 }, { 7, 1, 8 },
0171 { 8, 1, 9 }, { 9, 1, 10 }, { 10, 1, 11 }, { 11, 1, 12 },
0172 { 12, 1, 13 }, { 13, 1, 14 }, { 14, 1, 15 }, { 15, 1, 16 },
0173 { 16, 1, 17 }, { 17, 1, 18 }, { 18, 1, 19 }, { 19, 1, 20 },
0174 { 20, 1, 21 }, { 21, 1, 22 }, { 22, 1, 23 }, { 23, 1, 24 },
0175 { 24, 1, 25 }, { 25, 1, 26 }, { 26, 1, 27 }, { 27, 1, 28 },
0176 { 28, 1, 29 }, { 29, 1, 30 }, { 30, 1, 31 }, { 31, 1, 32 },
0177
0178
0179 { 256, 1, 1 * 128 }, { 257, 1, 2 * 128 }, { 258, 1, 3 * 128 }, { 259, 1, 4 * 128 },
0180 { 260, 1, 5 * 128 }, { 261, 1, 6 * 128 }, { 262, 1, 7 * 128 }, { 263, 1, 8 * 128 },
0181 { 264, 1, 9 * 128 }, { 265, 1, 10 * 128 }, { 266, 1, 11 * 128 }, { 267, 1, 12 * 128 },
0182 { 268, 1, 13 * 128 }, { 269, 1, 14 * 128 }, { 270, 1, 15 * 128 }, { 271, 1, 16 * 128 },
0183 { 272, 1, 17 * 128 }, { 273, 1, 18 * 128 }, { 274, 1, 19 * 128 }, { 275, 1, 20 * 128 },
0184 { 276, 1, 21 * 128 }, { 277, 1, 22 * 128 }, { 278, 1, 23 * 128 }, { 279, 1, 24 * 128 },
0185 { 280, 1, 25 * 128 }, { 281, 1, 26 * 128 }, { 282, 1, 27 * 128 }, { 283, 1, 28 * 128 },
0186 { 284, 1, 29 * 128 }, { 285, 1, 30 * 128 }, { 286, 1, 31 * 128 }, { 287, 1, 32 * 128 },
0187
0188 { }
0189 };
0190
0191 static struct clk_factor_table dmm_factor_table[] = {
0192 { 0, 1, 1 }, { 1, 2, 3 }, { 2, 1, 2 }, { 3, 1, 3 },
0193 { 4, 1, 4 },
0194 { }
0195 };
0196
0197 static struct clk_factor_table noc_factor_table[] = {
0198 { 0, 1, 1 }, { 1, 2, 3 }, { 2, 1, 2 }, { 3, 1, 3 }, { 4, 1, 4 },
0199 { }
0200 };
0201
0202 static struct clk_factor_table bisp_factor_table[] = {
0203 { 0, 1, 1 }, { 1, 2, 3 }, { 2, 1, 2 }, { 3, 2, 5 },
0204 { 4, 1, 3 }, { 5, 1, 4 }, { 6, 1, 6 }, { 7, 1, 8 },
0205 { }
0206 };
0207
0208
0209 static OWL_FACTOR(noc_clk, "noc_clk", "noc_clk_mux", CMU_BUSCLK, 16, 3, noc_factor_table, 0, 0);
0210 static OWL_FACTOR(de_clk1, "de_clk1", "de_clk", CMU_DECLK, 0, 3, bisp_factor_table, 0, 0);
0211 static OWL_FACTOR(de_clk2, "de_clk2", "de_clk", CMU_DECLK, 4, 3, bisp_factor_table, 0, 0);
0212 static OWL_FACTOR(de_clk3, "de_clk3", "de_clk", CMU_DECLK, 8, 3, bisp_factor_table, 0, 0);
0213
0214
0215 static OWL_GATE(gpio_clk, "gpio_clk", "apb_clk", CMU_DEVCLKEN0, 18, 0, 0);
0216 static OWL_GATE_NO_PARENT(gpu_clk, "gpu_clk", CMU_DEVCLKEN0, 30, 0, 0);
0217 static OWL_GATE(dmac_clk, "dmac_clk", "noc_clk_div", CMU_DEVCLKEN0, 1, 0, 0);
0218 static OWL_GATE(timer_clk, "timer_clk", "hosc", CMU_DEVCLKEN1, 27, 0, 0);
0219 static OWL_GATE_NO_PARENT(dsi_clk, "dsi_clk", CMU_DEVCLKEN0, 12, 0, 0);
0220 static OWL_GATE(ddr0_clk, "ddr0_clk", "ddr_pll_clk", CMU_DEVCLKEN0, 31, 0, CLK_IGNORE_UNUSED);
0221 static OWL_GATE(ddr1_clk, "ddr1_clk", "ddr_pll_clk", CMU_DEVCLKEN0, 29, 0, CLK_IGNORE_UNUSED);
0222 static OWL_GATE_NO_PARENT(usb3_480mpll0_clk, "usb3_480mpll0_clk", CMU_USBPLL, 3, 0, 0);
0223 static OWL_GATE_NO_PARENT(usb3_480mphy0_clk, "usb3_480mphy0_clk", CMU_USBPLL, 2, 0, 0);
0224 static OWL_GATE_NO_PARENT(usb3_5gphy_clk, "usb3_5gphy_clk", CMU_USBPLL, 1, 0, 0);
0225 static OWL_GATE_NO_PARENT(usb3_cce_clk, "usb3_cce_clk", CMU_USBPLL, 0, 0, 0);
0226 static OWL_GATE(edp24M_clk, "edp24M_clk", "diff24M", CMU_EDPCLK, 8, 0, 0);
0227 static OWL_GATE(edp_link_clk, "edp_link_clk", "edp_pll_clk", CMU_DEVCLKEN0, 10, 0, 0);
0228 static OWL_GATE_NO_PARENT(usbh0_pllen_clk, "usbh0_pllen_clk", CMU_USBPLL, 12, 0, 0);
0229 static OWL_GATE_NO_PARENT(usbh0_phy_clk, "usbh0_phy_clk", CMU_USBPLL, 10, 0, 0);
0230 static OWL_GATE_NO_PARENT(usbh0_cce_clk, "usbh0_cce_clk", CMU_USBPLL, 8, 0, 0);
0231 static OWL_GATE_NO_PARENT(usbh1_pllen_clk, "usbh1_pllen_clk", CMU_USBPLL, 13, 0, 0);
0232 static OWL_GATE_NO_PARENT(usbh1_phy_clk, "usbh1_phy_clk", CMU_USBPLL, 11, 0, 0);
0233 static OWL_GATE_NO_PARENT(usbh1_cce_clk, "usbh1_cce_clk", CMU_USBPLL, 9, 0, 0);
0234 static OWL_GATE(spi0_clk, "spi0_clk", "ahb_clk", CMU_DEVCLKEN1, 10, 0, CLK_IGNORE_UNUSED);
0235 static OWL_GATE(spi1_clk, "spi1_clk", "ahb_clk", CMU_DEVCLKEN1, 11, 0, CLK_IGNORE_UNUSED);
0236 static OWL_GATE(spi2_clk, "spi2_clk", "ahb_clk", CMU_DEVCLKEN1, 12, 0, CLK_IGNORE_UNUSED);
0237 static OWL_GATE(spi3_clk, "spi3_clk", "ahb_clk", CMU_DEVCLKEN1, 13, 0, CLK_IGNORE_UNUSED);
0238
0239
0240 static OWL_COMP_FACTOR(bisp_clk, "bisp_clk", bisp_clk_mux_p,
0241 OWL_MUX_HW(CMU_BISPCLK, 4, 1),
0242 OWL_GATE_HW(CMU_DEVCLKEN0, 14, 0),
0243 OWL_FACTOR_HW(CMU_BISPCLK, 0, 3, 0, bisp_factor_table),
0244 0);
0245
0246 static OWL_COMP_DIV(csi0_clk, "csi0_clk", csi_clk_mux_p,
0247 OWL_MUX_HW(CMU_CSICLK, 4, 1),
0248 OWL_GATE_HW(CMU_DEVCLKEN0, 13, 0),
0249 OWL_DIVIDER_HW(CMU_CSICLK, 0, 4, 0, NULL),
0250 0);
0251
0252 static OWL_COMP_DIV(csi1_clk, "csi1_clk", csi_clk_mux_p,
0253 OWL_MUX_HW(CMU_CSICLK, 20, 1),
0254 OWL_GATE_HW(CMU_DEVCLKEN0, 15, 0),
0255 OWL_DIVIDER_HW(CMU_CSICLK, 16, 4, 0, NULL),
0256 0);
0257
0258 static OWL_COMP_PASS(de_clk, "de_clk", de_clk_mux_p,
0259 OWL_MUX_HW(CMU_DECLK, 12, 1),
0260 OWL_GATE_HW(CMU_DEVCLKEN0, 8, 0),
0261 0);
0262
0263 static OWL_COMP_FACTOR(dmm_clk, "dmm_clk", dmm_clk_mux_p,
0264 OWL_MUX_HW(CMU_BUSCLK, 10, 2),
0265 OWL_GATE_HW(CMU_DEVCLKEN0, 19, 0),
0266 OWL_FACTOR_HW(CMU_BUSCLK, 12, 3, 0, dmm_factor_table),
0267 CLK_IGNORE_UNUSED);
0268
0269 static OWL_COMP_FACTOR(edp_clk, "edp_clk", edp_clk_mux_p,
0270 OWL_MUX_HW(CMU_EDPCLK, 19, 1),
0271 OWL_GATE_HW(CMU_DEVCLKEN0, 10, 0),
0272 OWL_FACTOR_HW(CMU_EDPCLK, 16, 3, 0, bisp_factor_table),
0273 0);
0274
0275 static OWL_COMP_DIV_FIXED(eth_mac_clk, "eth_mac_clk", "assist_pll_clk",
0276 OWL_GATE_HW(CMU_DEVCLKEN1, 22, 0),
0277 OWL_DIVIDER_HW(CMU_ASSISTPLL, 10, 1, 0, eth_mac_div_table),
0278 0);
0279
0280 static OWL_COMP_FACTOR(gpu_core_clk, "gpu_core_clk", gpu_clk_mux_p,
0281 OWL_MUX_HW(CMU_GPU3DCLK, 4, 2),
0282 OWL_GATE_HW(CMU_GPU3DCLK, 15, 0),
0283 OWL_FACTOR_HW(CMU_GPU3DCLK, 0, 3, 0, bisp_factor_table),
0284 0);
0285
0286 static OWL_COMP_FACTOR(gpu_mem_clk, "gpu_mem_clk", gpu_clk_mux_p,
0287 OWL_MUX_HW(CMU_GPU3DCLK, 20, 2),
0288 OWL_GATE_HW(CMU_GPU3DCLK, 14, 0),
0289 OWL_FACTOR_HW(CMU_GPU3DCLK, 16, 3, 0, bisp_factor_table),
0290 0);
0291
0292 static OWL_COMP_FACTOR(gpu_sys_clk, "gpu_sys_clk", gpu_clk_mux_p,
0293 OWL_MUX_HW(CMU_GPU3DCLK, 28, 2),
0294 OWL_GATE_HW(CMU_GPU3DCLK, 13, 0),
0295 OWL_FACTOR_HW(CMU_GPU3DCLK, 24, 3, 0, bisp_factor_table),
0296 0);
0297
0298 static OWL_COMP_FACTOR(hde_clk, "hde_clk", hde_clk_mux_p,
0299 OWL_MUX_HW(CMU_HDECLK, 4, 2),
0300 OWL_GATE_HW(CMU_DEVCLKEN0, 27, 0),
0301 OWL_FACTOR_HW(CMU_HDECLK, 0, 3, 0, bisp_factor_table),
0302 0);
0303
0304 static OWL_COMP_DIV(hdmia_clk, "hdmia_clk", i2s_clk_mux_p,
0305 OWL_MUX_HW(CMU_AUDIOPLL, 24, 1),
0306 OWL_GATE_HW(CMU_DEVCLKEN0, 22, 0),
0307 OWL_DIVIDER_HW(CMU_AUDIOPLL, 24, 4, 0, hdmia_div_table),
0308 0);
0309
0310 static OWL_COMP_FIXED_FACTOR(i2c0_clk, "i2c0_clk", "assist_pll_clk",
0311 OWL_GATE_HW(CMU_DEVCLKEN1, 14, 0),
0312 1, 5, 0);
0313
0314 static OWL_COMP_FIXED_FACTOR(i2c1_clk, "i2c1_clk", "assist_pll_clk",
0315 OWL_GATE_HW(CMU_DEVCLKEN1, 15, 0),
0316 1, 5, 0);
0317
0318 static OWL_COMP_FIXED_FACTOR(i2c2_clk, "i2c2_clk", "assist_pll_clk",
0319 OWL_GATE_HW(CMU_DEVCLKEN1, 30, 0),
0320 1, 5, 0);
0321
0322 static OWL_COMP_FIXED_FACTOR(i2c3_clk, "i2c3_clk", "assist_pll_clk",
0323 OWL_GATE_HW(CMU_DEVCLKEN1, 31, 0),
0324 1, 5, 0);
0325
0326 static OWL_COMP_FIXED_FACTOR(i2c4_clk, "i2c4_clk", "assist_pll_clk",
0327 OWL_GATE_HW(CMU_DEVCLKEN0, 17, 0),
0328 1, 5, 0);
0329
0330 static OWL_COMP_FIXED_FACTOR(i2c5_clk, "i2c5_clk", "assist_pll_clk",
0331 OWL_GATE_HW(CMU_DEVCLKEN1, 1, 0),
0332 1, 5, 0);
0333
0334 static OWL_COMP_DIV(i2srx_clk, "i2srx_clk", i2s_clk_mux_p,
0335 OWL_MUX_HW(CMU_AUDIOPLL, 24, 1),
0336 OWL_GATE_HW(CMU_DEVCLKEN0, 21, 0),
0337 OWL_DIVIDER_HW(CMU_AUDIOPLL, 20, 4, 0, i2s_div_table),
0338 0);
0339
0340 static OWL_COMP_DIV(i2stx_clk, "i2stx_clk", i2s_clk_mux_p,
0341 OWL_MUX_HW(CMU_AUDIOPLL, 24, 1),
0342 OWL_GATE_HW(CMU_DEVCLKEN0, 20, 0),
0343 OWL_DIVIDER_HW(CMU_AUDIOPLL, 16, 4, 0, i2s_div_table),
0344 0);
0345
0346 static OWL_COMP_FACTOR(imx_clk, "imx_clk", imx_clk_mux_p,
0347 OWL_MUX_HW(CMU_IMXCLK, 4, 1),
0348 OWL_GATE_HW(CMU_DEVCLKEN1, 17, 0),
0349 OWL_FACTOR_HW(CMU_IMXCLK, 0, 3, 0, bisp_factor_table),
0350 0);
0351
0352 static OWL_COMP_DIV(lcd_clk, "lcd_clk", lcd_clk_mux_p,
0353 OWL_MUX_HW(CMU_LCDCLK, 12, 2),
0354 OWL_GATE_HW(CMU_DEVCLKEN0, 9, 0),
0355 OWL_DIVIDER_HW(CMU_LCDCLK, 0, 5, 0, NULL),
0356 0);
0357
0358 static OWL_COMP_DIV(nand0_clk, "nand0_clk", nand_clk_mux_p,
0359 OWL_MUX_HW(CMU_NANDCCLK, 8, 1),
0360 OWL_GATE_HW(CMU_DEVCLKEN0, 4, 0),
0361 OWL_DIVIDER_HW(CMU_NANDCCLK, 0, 4, 0, nand_div_table),
0362 CLK_SET_RATE_PARENT);
0363
0364 static OWL_COMP_DIV(nand1_clk, "nand1_clk", nand_clk_mux_p,
0365 OWL_MUX_HW(CMU_NANDCCLK, 24, 1),
0366 OWL_GATE_HW(CMU_DEVCLKEN0, 11, 0),
0367 OWL_DIVIDER_HW(CMU_NANDCCLK, 16, 4, 0, nand_div_table),
0368 CLK_SET_RATE_PARENT);
0369
0370 static OWL_COMP_DIV_FIXED(pwm0_clk, "pwm0_clk", "hosc",
0371 OWL_GATE_HW(CMU_DEVCLKEN1, 23, 0),
0372 OWL_DIVIDER_HW(CMU_PWM0CLK, 0, 6, 0, NULL),
0373 0);
0374
0375 static OWL_COMP_DIV_FIXED(pwm1_clk, "pwm1_clk", "hosc",
0376 OWL_GATE_HW(CMU_DEVCLKEN1, 24, 0),
0377 OWL_DIVIDER_HW(CMU_PWM1CLK, 0, 6, 0, NULL),
0378 0);
0379
0380
0381
0382
0383
0384
0385
0386 static OWL_COMP_DIV_FIXED(pwm2_clk, "pwm2_clk", "hosc",
0387 OWL_GATE_HW(CMU_DEVCLKEN1, 25, 0),
0388 OWL_DIVIDER_HW(CMU_PWM2CLK, 0, 6, 0, NULL),
0389 CLK_IGNORE_UNUSED);
0390
0391 static OWL_COMP_DIV_FIXED(pwm3_clk, "pwm3_clk", "hosc",
0392 OWL_GATE_HW(CMU_DEVCLKEN1, 26, 0),
0393 OWL_DIVIDER_HW(CMU_PWM3CLK, 0, 6, 0, NULL),
0394 0);
0395
0396 static OWL_COMP_DIV_FIXED(pwm4_clk, "pwm4_clk", "hosc",
0397 OWL_GATE_HW(CMU_DEVCLKEN1, 4, 0),
0398 OWL_DIVIDER_HW(CMU_PWM4CLK, 0, 6, 0, NULL),
0399 0);
0400
0401 static OWL_COMP_DIV_FIXED(pwm5_clk, "pwm5_clk", "hosc",
0402 OWL_GATE_HW(CMU_DEVCLKEN1, 5, 0),
0403 OWL_DIVIDER_HW(CMU_PWM5CLK, 0, 6, 0, NULL),
0404 0);
0405
0406 static OWL_COMP_FACTOR(sd0_clk, "sd0_clk", sd_clk_mux_p,
0407 OWL_MUX_HW(CMU_SD0CLK, 9, 1),
0408 OWL_GATE_HW(CMU_DEVCLKEN0, 5, 0),
0409 OWL_FACTOR_HW(CMU_SD0CLK, 0, 9, 0, sd_factor_table),
0410 0);
0411
0412 static OWL_COMP_FACTOR(sd1_clk, "sd1_clk", sd_clk_mux_p,
0413 OWL_MUX_HW(CMU_SD1CLK, 9, 1),
0414 OWL_GATE_HW(CMU_DEVCLKEN0, 6, 0),
0415 OWL_FACTOR_HW(CMU_SD1CLK, 0, 9, 0, sd_factor_table),
0416 0);
0417
0418 static OWL_COMP_FACTOR(sd2_clk, "sd2_clk", sd_clk_mux_p,
0419 OWL_MUX_HW(CMU_SD2CLK, 9, 1),
0420 OWL_GATE_HW(CMU_DEVCLKEN0, 7, 0),
0421 OWL_FACTOR_HW(CMU_SD2CLK, 0, 9, 0, sd_factor_table),
0422 0);
0423
0424 static OWL_COMP_FACTOR(sd3_clk, "sd3_clk", sd_clk_mux_p,
0425 OWL_MUX_HW(CMU_SD3CLK, 9, 1),
0426 OWL_GATE_HW(CMU_DEVCLKEN0, 16, 0),
0427 OWL_FACTOR_HW(CMU_SD3CLK, 0, 9, 0, sd_factor_table),
0428 0);
0429
0430 static OWL_COMP_DIV(sensor_clk, "sensor_clk", sensor_clk_mux_p,
0431 OWL_MUX_HW(CMU_SENSORCLK, 4, 1),
0432 OWL_GATE_HW(CMU_DEVCLKEN0, 14, 0),
0433 OWL_DIVIDER_HW(CMU_SENSORCLK, 0, 4, 0, NULL),
0434 0);
0435
0436 static OWL_COMP_DIV_FIXED(speed_sensor_clk, "speed_sensor_clk",
0437 "hosc",
0438 OWL_GATE_HW(CMU_DEVCLKEN1, 0, 0),
0439 OWL_DIVIDER_HW(CMU_TLSCLK, 0, 4, CLK_DIVIDER_POWER_OF_TWO, NULL),
0440 0);
0441
0442 static OWL_COMP_DIV_FIXED(thermal_sensor_clk, "thermal_sensor_clk",
0443 "hosc",
0444 OWL_GATE_HW(CMU_DEVCLKEN1, 2, 0),
0445 OWL_DIVIDER_HW(CMU_TLSCLK, 8, 4, CLK_DIVIDER_POWER_OF_TWO, NULL),
0446 0);
0447
0448 static OWL_COMP_DIV(uart0_clk, "uart0_clk", uart_clk_mux_p,
0449 OWL_MUX_HW(CMU_UART0CLK, 16, 1),
0450 OWL_GATE_HW(CMU_DEVCLKEN1, 6, 0),
0451 OWL_DIVIDER_HW(CMU_UART0CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
0452 CLK_IGNORE_UNUSED);
0453
0454 static OWL_COMP_DIV(uart1_clk, "uart1_clk", uart_clk_mux_p,
0455 OWL_MUX_HW(CMU_UART1CLK, 16, 1),
0456 OWL_GATE_HW(CMU_DEVCLKEN1, 7, 0),
0457 OWL_DIVIDER_HW(CMU_UART1CLK, 1, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
0458 CLK_IGNORE_UNUSED);
0459
0460 static OWL_COMP_DIV(uart2_clk, "uart2_clk", uart_clk_mux_p,
0461 OWL_MUX_HW(CMU_UART2CLK, 16, 1),
0462 OWL_GATE_HW(CMU_DEVCLKEN1, 8, 0),
0463 OWL_DIVIDER_HW(CMU_UART2CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
0464 CLK_IGNORE_UNUSED);
0465
0466 static OWL_COMP_DIV(uart3_clk, "uart3_clk", uart_clk_mux_p,
0467 OWL_MUX_HW(CMU_UART3CLK, 16, 1),
0468 OWL_GATE_HW(CMU_DEVCLKEN1, 19, 0),
0469 OWL_DIVIDER_HW(CMU_UART3CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
0470 CLK_IGNORE_UNUSED);
0471
0472 static OWL_COMP_DIV(uart4_clk, "uart4_clk", uart_clk_mux_p,
0473 OWL_MUX_HW(CMU_UART4CLK, 16, 1),
0474 OWL_GATE_HW(CMU_DEVCLKEN1, 20, 0),
0475 OWL_DIVIDER_HW(CMU_UART4CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
0476 CLK_IGNORE_UNUSED);
0477
0478 static OWL_COMP_DIV(uart5_clk, "uart5_clk", uart_clk_mux_p,
0479 OWL_MUX_HW(CMU_UART5CLK, 16, 1),
0480 OWL_GATE_HW(CMU_DEVCLKEN1, 21, 0),
0481 OWL_DIVIDER_HW(CMU_UART5CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
0482 CLK_IGNORE_UNUSED);
0483
0484 static OWL_COMP_DIV(uart6_clk, "uart6_clk", uart_clk_mux_p,
0485 OWL_MUX_HW(CMU_UART6CLK, 16, 1),
0486 OWL_GATE_HW(CMU_DEVCLKEN1, 18, 0),
0487 OWL_DIVIDER_HW(CMU_UART6CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
0488 CLK_IGNORE_UNUSED);
0489
0490 static OWL_COMP_FACTOR(vce_clk, "vce_clk", vce_clk_mux_p,
0491 OWL_MUX_HW(CMU_VCECLK, 4, 2),
0492 OWL_GATE_HW(CMU_DEVCLKEN0, 26, 0),
0493 OWL_FACTOR_HW(CMU_VCECLK, 0, 3, 0, bisp_factor_table),
0494 0);
0495
0496 static OWL_COMP_FACTOR(vde_clk, "vde_clk", hde_clk_mux_p,
0497 OWL_MUX_HW(CMU_VDECLK, 4, 2),
0498 OWL_GATE_HW(CMU_DEVCLKEN0, 25, 0),
0499 OWL_FACTOR_HW(CMU_VDECLK, 0, 3, 0, bisp_factor_table),
0500 0);
0501
0502 static struct owl_clk_common *s900_clks[] = {
0503 &core_pll_clk.common,
0504 &dev_pll_clk.common,
0505 &ddr_pll_clk.common,
0506 &nand_pll_clk.common,
0507 &display_pll_clk.common,
0508 &assist_pll_clk.common,
0509 &audio_pll_clk.common,
0510 &edp_pll_clk.common,
0511 &cpu_clk.common,
0512 &dev_clk.common,
0513 &noc_clk_mux.common,
0514 &noc_clk_div.common,
0515 &ahb_clk.common,
0516 &apb_clk.common,
0517 &usb3_mac_clk.common,
0518 &rmii_ref_clk.common,
0519 &noc_clk.common,
0520 &de_clk1.common,
0521 &de_clk2.common,
0522 &de_clk3.common,
0523 &gpio_clk.common,
0524 &gpu_clk.common,
0525 &dmac_clk.common,
0526 &timer_clk.common,
0527 &dsi_clk.common,
0528 &ddr0_clk.common,
0529 &ddr1_clk.common,
0530 &usb3_480mpll0_clk.common,
0531 &usb3_480mphy0_clk.common,
0532 &usb3_5gphy_clk.common,
0533 &usb3_cce_clk.common,
0534 &edp24M_clk.common,
0535 &edp_link_clk.common,
0536 &usbh0_pllen_clk.common,
0537 &usbh0_phy_clk.common,
0538 &usbh0_cce_clk.common,
0539 &usbh1_pllen_clk.common,
0540 &usbh1_phy_clk.common,
0541 &usbh1_cce_clk.common,
0542 &i2c0_clk.common,
0543 &i2c1_clk.common,
0544 &i2c2_clk.common,
0545 &i2c3_clk.common,
0546 &i2c4_clk.common,
0547 &i2c5_clk.common,
0548 &spi0_clk.common,
0549 &spi1_clk.common,
0550 &spi2_clk.common,
0551 &spi3_clk.common,
0552 &bisp_clk.common,
0553 &csi0_clk.common,
0554 &csi1_clk.common,
0555 &de_clk.common,
0556 &dmm_clk.common,
0557 &edp_clk.common,
0558 ð_mac_clk.common,
0559 &gpu_core_clk.common,
0560 &gpu_mem_clk.common,
0561 &gpu_sys_clk.common,
0562 &hde_clk.common,
0563 &hdmia_clk.common,
0564 &i2srx_clk.common,
0565 &i2stx_clk.common,
0566 &imx_clk.common,
0567 &lcd_clk.common,
0568 &nand0_clk.common,
0569 &nand1_clk.common,
0570 &pwm0_clk.common,
0571 &pwm1_clk.common,
0572 &pwm2_clk.common,
0573 &pwm3_clk.common,
0574 &pwm4_clk.common,
0575 &pwm5_clk.common,
0576 &sd0_clk.common,
0577 &sd1_clk.common,
0578 &sd2_clk.common,
0579 &sd3_clk.common,
0580 &sensor_clk.common,
0581 &speed_sensor_clk.common,
0582 &thermal_sensor_clk.common,
0583 &uart0_clk.common,
0584 &uart1_clk.common,
0585 &uart2_clk.common,
0586 &uart3_clk.common,
0587 &uart4_clk.common,
0588 &uart5_clk.common,
0589 &uart6_clk.common,
0590 &vce_clk.common,
0591 &vde_clk.common,
0592 };
0593
0594 static struct clk_hw_onecell_data s900_hw_clks = {
0595 .hws = {
0596 [CLK_CORE_PLL] = &core_pll_clk.common.hw,
0597 [CLK_DEV_PLL] = &dev_pll_clk.common.hw,
0598 [CLK_DDR_PLL] = &ddr_pll_clk.common.hw,
0599 [CLK_NAND_PLL] = &nand_pll_clk.common.hw,
0600 [CLK_DISPLAY_PLL] = &display_pll_clk.common.hw,
0601 [CLK_ASSIST_PLL] = &assist_pll_clk.common.hw,
0602 [CLK_AUDIO_PLL] = &audio_pll_clk.common.hw,
0603 [CLK_EDP_PLL] = &edp_pll_clk.common.hw,
0604 [CLK_CPU] = &cpu_clk.common.hw,
0605 [CLK_DEV] = &dev_clk.common.hw,
0606 [CLK_NOC_MUX] = &noc_clk_mux.common.hw,
0607 [CLK_NOC_DIV] = &noc_clk_div.common.hw,
0608 [CLK_AHB] = &ahb_clk.common.hw,
0609 [CLK_APB] = &apb_clk.common.hw,
0610 [CLK_USB3_MAC] = &usb3_mac_clk.common.hw,
0611 [CLK_RMII_REF] = &rmii_ref_clk.common.hw,
0612 [CLK_NOC] = &noc_clk.common.hw,
0613 [CLK_DE1] = &de_clk1.common.hw,
0614 [CLK_DE2] = &de_clk2.common.hw,
0615 [CLK_DE3] = &de_clk3.common.hw,
0616 [CLK_GPIO] = &gpio_clk.common.hw,
0617 [CLK_GPU] = &gpu_clk.common.hw,
0618 [CLK_DMAC] = &dmac_clk.common.hw,
0619 [CLK_TIMER] = &timer_clk.common.hw,
0620 [CLK_DSI] = &dsi_clk.common.hw,
0621 [CLK_DDR0] = &ddr0_clk.common.hw,
0622 [CLK_DDR1] = &ddr1_clk.common.hw,
0623 [CLK_USB3_480MPLL0] = &usb3_480mpll0_clk.common.hw,
0624 [CLK_USB3_480MPHY0] = &usb3_480mphy0_clk.common.hw,
0625 [CLK_USB3_5GPHY] = &usb3_5gphy_clk.common.hw,
0626 [CLK_USB3_CCE] = &usb3_cce_clk.common.hw,
0627 [CLK_24M_EDP] = &edp24M_clk.common.hw,
0628 [CLK_EDP_LINK] = &edp_link_clk.common.hw,
0629 [CLK_USB2H0_PLLEN] = &usbh0_pllen_clk.common.hw,
0630 [CLK_USB2H0_PHY] = &usbh0_phy_clk.common.hw,
0631 [CLK_USB2H0_CCE] = &usbh0_cce_clk.common.hw,
0632 [CLK_USB2H1_PLLEN] = &usbh1_pllen_clk.common.hw,
0633 [CLK_USB2H1_PHY] = &usbh1_phy_clk.common.hw,
0634 [CLK_USB2H1_CCE] = &usbh1_cce_clk.common.hw,
0635 [CLK_I2C0] = &i2c0_clk.common.hw,
0636 [CLK_I2C1] = &i2c1_clk.common.hw,
0637 [CLK_I2C2] = &i2c2_clk.common.hw,
0638 [CLK_I2C3] = &i2c3_clk.common.hw,
0639 [CLK_I2C4] = &i2c4_clk.common.hw,
0640 [CLK_I2C5] = &i2c5_clk.common.hw,
0641 [CLK_SPI0] = &spi0_clk.common.hw,
0642 [CLK_SPI1] = &spi1_clk.common.hw,
0643 [CLK_SPI2] = &spi2_clk.common.hw,
0644 [CLK_SPI3] = &spi3_clk.common.hw,
0645 [CLK_BISP] = &bisp_clk.common.hw,
0646 [CLK_CSI0] = &csi0_clk.common.hw,
0647 [CLK_CSI1] = &csi1_clk.common.hw,
0648 [CLK_DE0] = &de_clk.common.hw,
0649 [CLK_DMM] = &dmm_clk.common.hw,
0650 [CLK_EDP] = &edp_clk.common.hw,
0651 [CLK_ETH_MAC] = ð_mac_clk.common.hw,
0652 [CLK_GPU_CORE] = &gpu_core_clk.common.hw,
0653 [CLK_GPU_MEM] = &gpu_mem_clk.common.hw,
0654 [CLK_GPU_SYS] = &gpu_sys_clk.common.hw,
0655 [CLK_HDE] = &hde_clk.common.hw,
0656 [CLK_HDMI_AUDIO] = &hdmia_clk.common.hw,
0657 [CLK_I2SRX] = &i2srx_clk.common.hw,
0658 [CLK_I2STX] = &i2stx_clk.common.hw,
0659 [CLK_IMX] = &imx_clk.common.hw,
0660 [CLK_LCD] = &lcd_clk.common.hw,
0661 [CLK_NAND0] = &nand0_clk.common.hw,
0662 [CLK_NAND1] = &nand1_clk.common.hw,
0663 [CLK_PWM0] = &pwm0_clk.common.hw,
0664 [CLK_PWM1] = &pwm1_clk.common.hw,
0665 [CLK_PWM2] = &pwm2_clk.common.hw,
0666 [CLK_PWM3] = &pwm3_clk.common.hw,
0667 [CLK_PWM4] = &pwm4_clk.common.hw,
0668 [CLK_PWM5] = &pwm5_clk.common.hw,
0669 [CLK_SD0] = &sd0_clk.common.hw,
0670 [CLK_SD1] = &sd1_clk.common.hw,
0671 [CLK_SD2] = &sd2_clk.common.hw,
0672 [CLK_SD3] = &sd3_clk.common.hw,
0673 [CLK_SENSOR] = &sensor_clk.common.hw,
0674 [CLK_SPEED_SENSOR] = &speed_sensor_clk.common.hw,
0675 [CLK_THERMAL_SENSOR] = &thermal_sensor_clk.common.hw,
0676 [CLK_UART0] = &uart0_clk.common.hw,
0677 [CLK_UART1] = &uart1_clk.common.hw,
0678 [CLK_UART2] = &uart2_clk.common.hw,
0679 [CLK_UART3] = &uart3_clk.common.hw,
0680 [CLK_UART4] = &uart4_clk.common.hw,
0681 [CLK_UART5] = &uart5_clk.common.hw,
0682 [CLK_UART6] = &uart6_clk.common.hw,
0683 [CLK_VCE] = &vce_clk.common.hw,
0684 [CLK_VDE] = &vde_clk.common.hw,
0685 },
0686 .num = CLK_NR_CLKS,
0687 };
0688
0689 static const struct owl_reset_map s900_resets[] = {
0690 [RESET_DMAC] = { CMU_DEVRST0, BIT(0) },
0691 [RESET_SRAMI] = { CMU_DEVRST0, BIT(1) },
0692 [RESET_DDR_CTL_PHY] = { CMU_DEVRST0, BIT(2) },
0693 [RESET_NANDC0] = { CMU_DEVRST0, BIT(3) },
0694 [RESET_SD0] = { CMU_DEVRST0, BIT(4) },
0695 [RESET_SD1] = { CMU_DEVRST0, BIT(5) },
0696 [RESET_PCM1] = { CMU_DEVRST0, BIT(6) },
0697 [RESET_DE] = { CMU_DEVRST0, BIT(7) },
0698 [RESET_LVDS] = { CMU_DEVRST0, BIT(8) },
0699 [RESET_SD2] = { CMU_DEVRST0, BIT(9) },
0700 [RESET_DSI] = { CMU_DEVRST0, BIT(10) },
0701 [RESET_CSI0] = { CMU_DEVRST0, BIT(11) },
0702 [RESET_BISP_AXI] = { CMU_DEVRST0, BIT(12) },
0703 [RESET_CSI1] = { CMU_DEVRST0, BIT(13) },
0704 [RESET_GPIO] = { CMU_DEVRST0, BIT(15) },
0705 [RESET_EDP] = { CMU_DEVRST0, BIT(16) },
0706 [RESET_AUDIO] = { CMU_DEVRST0, BIT(17) },
0707 [RESET_PCM0] = { CMU_DEVRST0, BIT(18) },
0708 [RESET_HDE] = { CMU_DEVRST0, BIT(21) },
0709 [RESET_GPU3D_PA] = { CMU_DEVRST0, BIT(22) },
0710 [RESET_IMX] = { CMU_DEVRST0, BIT(23) },
0711 [RESET_SE] = { CMU_DEVRST0, BIT(24) },
0712 [RESET_NANDC1] = { CMU_DEVRST0, BIT(25) },
0713 [RESET_SD3] = { CMU_DEVRST0, BIT(26) },
0714 [RESET_GIC] = { CMU_DEVRST0, BIT(27) },
0715 [RESET_GPU3D_PB] = { CMU_DEVRST0, BIT(28) },
0716 [RESET_DDR_CTL_PHY_AXI] = { CMU_DEVRST0, BIT(29) },
0717 [RESET_CMU_DDR] = { CMU_DEVRST0, BIT(30) },
0718 [RESET_DMM] = { CMU_DEVRST0, BIT(31) },
0719 [RESET_USB2HUB] = { CMU_DEVRST1, BIT(0) },
0720 [RESET_USB2HSIC] = { CMU_DEVRST1, BIT(1) },
0721 [RESET_HDMI] = { CMU_DEVRST1, BIT(2) },
0722 [RESET_HDCP2TX] = { CMU_DEVRST1, BIT(3) },
0723 [RESET_UART6] = { CMU_DEVRST1, BIT(4) },
0724 [RESET_UART0] = { CMU_DEVRST1, BIT(5) },
0725 [RESET_UART1] = { CMU_DEVRST1, BIT(6) },
0726 [RESET_UART2] = { CMU_DEVRST1, BIT(7) },
0727 [RESET_SPI0] = { CMU_DEVRST1, BIT(8) },
0728 [RESET_SPI1] = { CMU_DEVRST1, BIT(9) },
0729 [RESET_SPI2] = { CMU_DEVRST1, BIT(10) },
0730 [RESET_SPI3] = { CMU_DEVRST1, BIT(11) },
0731 [RESET_I2C0] = { CMU_DEVRST1, BIT(12) },
0732 [RESET_I2C1] = { CMU_DEVRST1, BIT(13) },
0733 [RESET_USB3] = { CMU_DEVRST1, BIT(14) },
0734 [RESET_UART3] = { CMU_DEVRST1, BIT(15) },
0735 [RESET_UART4] = { CMU_DEVRST1, BIT(16) },
0736 [RESET_UART5] = { CMU_DEVRST1, BIT(17) },
0737 [RESET_I2C2] = { CMU_DEVRST1, BIT(18) },
0738 [RESET_I2C3] = { CMU_DEVRST1, BIT(19) },
0739 [RESET_ETHERNET] = { CMU_DEVRST1, BIT(20) },
0740 [RESET_CHIPID] = { CMU_DEVRST1, BIT(21) },
0741 [RESET_I2C4] = { CMU_DEVRST1, BIT(22) },
0742 [RESET_I2C5] = { CMU_DEVRST1, BIT(23) },
0743 [RESET_CPU_SCNT] = { CMU_DEVRST1, BIT(30) }
0744 };
0745
0746 static struct owl_clk_desc s900_clk_desc = {
0747 .clks = s900_clks,
0748 .num_clks = ARRAY_SIZE(s900_clks),
0749
0750 .hw_clks = &s900_hw_clks,
0751
0752 .resets = s900_resets,
0753 .num_resets = ARRAY_SIZE(s900_resets),
0754 };
0755
0756 static int s900_clk_probe(struct platform_device *pdev)
0757 {
0758 struct owl_clk_desc *desc;
0759 struct owl_reset *reset;
0760 int ret;
0761
0762 desc = &s900_clk_desc;
0763 owl_clk_regmap_init(pdev, desc);
0764
0765
0766
0767
0768
0769 reset = devm_kzalloc(&pdev->dev, sizeof(*reset), GFP_KERNEL);
0770 if (!reset)
0771 return -ENOMEM;
0772
0773 reset->rcdev.of_node = pdev->dev.of_node;
0774 reset->rcdev.ops = &owl_reset_ops;
0775 reset->rcdev.nr_resets = desc->num_resets;
0776 reset->reset_map = desc->resets;
0777 reset->regmap = desc->regmap;
0778
0779 ret = devm_reset_controller_register(&pdev->dev, &reset->rcdev);
0780 if (ret)
0781 dev_err(&pdev->dev, "Failed to register reset controller\n");
0782
0783 return owl_clk_probe(&pdev->dev, desc->hw_clks);
0784 }
0785
0786 static const struct of_device_id s900_clk_of_match[] = {
0787 { .compatible = "actions,s900-cmu", },
0788 { }
0789 };
0790
0791 static struct platform_driver s900_clk_driver = {
0792 .probe = s900_clk_probe,
0793 .driver = {
0794 .name = "s900-cmu",
0795 .of_match_table = s900_clk_of_match,
0796 },
0797 };
0798
0799 static int __init s900_clk_init(void)
0800 {
0801 return platform_driver_register(&s900_clk_driver);
0802 }
0803 core_initcall(s900_clk_init);
