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0012 #include <linux/clk-provider.h>
0013 #include <linux/platform_device.h>
0014
0015 #include "owl-common.h"
0016 #include "owl-composite.h"
0017 #include "owl-divider.h"
0018 #include "owl-factor.h"
0019 #include "owl-fixed-factor.h"
0020 #include "owl-gate.h"
0021 #include "owl-mux.h"
0022 #include "owl-pll.h"
0023 #include "owl-reset.h"
0024
0025 #include <dt-bindings/clock/actions,s700-cmu.h>
0026 #include <dt-bindings/reset/actions,s700-reset.h>
0027
0028 #define CMU_COREPLL (0x0000)
0029 #define CMU_DEVPLL (0x0004)
0030 #define CMU_DDRPLL (0x0008)
0031 #define CMU_NANDPLL (0x000C)
0032 #define CMU_DISPLAYPLL (0x0010)
0033 #define CMU_AUDIOPLL (0x0014)
0034 #define CMU_TVOUTPLL (0x0018)
0035 #define CMU_BUSCLK (0x001C)
0036 #define CMU_SENSORCLK (0x0020)
0037 #define CMU_LCDCLK (0x0024)
0038 #define CMU_DSIPLLCLK (0x0028)
0039 #define CMU_CSICLK (0x002C)
0040 #define CMU_DECLK (0x0030)
0041 #define CMU_SICLK (0x0034)
0042 #define CMU_BUSCLK1 (0x0038)
0043 #define CMU_HDECLK (0x003C)
0044 #define CMU_VDECLK (0x0040)
0045 #define CMU_VCECLK (0x0044)
0046 #define CMU_NANDCCLK (0x004C)
0047 #define CMU_SD0CLK (0x0050)
0048 #define CMU_SD1CLK (0x0054)
0049 #define CMU_SD2CLK (0x0058)
0050 #define CMU_UART0CLK (0x005C)
0051 #define CMU_UART1CLK (0x0060)
0052 #define CMU_UART2CLK (0x0064)
0053 #define CMU_UART3CLK (0x0068)
0054 #define CMU_UART4CLK (0x006C)
0055 #define CMU_UART5CLK (0x0070)
0056 #define CMU_UART6CLK (0x0074)
0057 #define CMU_PWM0CLK (0x0078)
0058 #define CMU_PWM1CLK (0x007C)
0059 #define CMU_PWM2CLK (0x0080)
0060 #define CMU_PWM3CLK (0x0084)
0061 #define CMU_PWM4CLK (0x0088)
0062 #define CMU_PWM5CLK (0x008C)
0063 #define CMU_GPU3DCLK (0x0090)
0064 #define CMU_CORECTL (0x009C)
0065 #define CMU_DEVCLKEN0 (0x00A0)
0066 #define CMU_DEVCLKEN1 (0x00A4)
0067 #define CMU_DEVRST0 (0x00A8)
0068 #define CMU_DEVRST1 (0x00AC)
0069 #define CMU_USBPLL (0x00B0)
0070 #define CMU_ETHERNETPLL (0x00B4)
0071 #define CMU_CVBSPLL (0x00B8)
0072 #define CMU_SSTSCLK (0x00C0)
0073
0074 static struct clk_pll_table clk_audio_pll_table[] = {
0075 {0, 45158400}, {1, 49152000},
0076 { }
0077 };
0078
0079 static struct clk_pll_table clk_cvbs_pll_table[] = {
0080 {27, 29 * 12000000}, {28, 30 * 12000000}, {29, 31 * 12000000},
0081 {30, 32 * 12000000}, {31, 33 * 12000000}, {32, 34 * 12000000},
0082 {33, 35 * 12000000}, {34, 36 * 12000000}, {35, 37 * 12000000},
0083 {36, 38 * 12000000}, {37, 39 * 12000000}, {38, 40 * 12000000},
0084 {39, 41 * 12000000}, {40, 42 * 12000000}, {41, 43 * 12000000},
0085 {42, 44 * 12000000}, {43, 45 * 12000000},
0086 { }
0087 };
0088
0089
0090 static OWL_PLL_NO_PARENT(clk_core_pll, "core_pll", CMU_COREPLL, 12000000, 9, 0, 8, 4, 174, NULL, CLK_IGNORE_UNUSED);
0091 static OWL_PLL_NO_PARENT(clk_dev_pll, "dev_pll", CMU_DEVPLL, 6000000, 8, 0, 8, 8, 126, NULL, CLK_IGNORE_UNUSED);
0092 static OWL_PLL_NO_PARENT(clk_ddr_pll, "ddr_pll", CMU_DDRPLL, 6000000, 8, 0, 8, 2, 180, NULL, CLK_IGNORE_UNUSED);
0093 static OWL_PLL_NO_PARENT(clk_nand_pll, "nand_pll", CMU_NANDPLL, 6000000, 8, 0, 8, 2, 86, NULL, CLK_IGNORE_UNUSED);
0094 static OWL_PLL_NO_PARENT(clk_display_pll, "display_pll", CMU_DISPLAYPLL, 6000000, 8, 0, 8, 2, 140, NULL, CLK_IGNORE_UNUSED);
0095 static OWL_PLL_NO_PARENT(clk_cvbs_pll, "cvbs_pll", CMU_CVBSPLL, 0, 8, 0, 8, 27, 43, clk_cvbs_pll_table, CLK_IGNORE_UNUSED);
0096 static OWL_PLL_NO_PARENT(clk_audio_pll, "audio_pll", CMU_AUDIOPLL, 0, 4, 0, 1, 0, 0, clk_audio_pll_table, CLK_IGNORE_UNUSED);
0097 static OWL_PLL_NO_PARENT(clk_ethernet_pll, "ethernet_pll", CMU_ETHERNETPLL, 500000000, 0, 0, 0, 0, 0, NULL, CLK_IGNORE_UNUSED);
0098
0099 static const char *cpu_clk_mux_p[] = {"losc", "hosc", "core_pll", "noc1_clk_div"};
0100 static const char *dev_clk_p[] = { "hosc", "dev_pll"};
0101 static const char *noc_clk_mux_p[] = { "dev_clk", "display_pll", "nand_pll", "ddr_pll", "cvbs_pll"};
0102
0103 static const char *csi_clk_mux_p[] = { "display_pll", "dev_clk"};
0104 static const char *de_clk_mux_p[] = { "display_pll", "dev_clk"};
0105 static const char *hde_clk_mux_p[] = { "dev_clk", "display_pll", "nand_pll", "ddr_pll"};
0106 static const char *nand_clk_mux_p[] = { "nand_pll", "display_pll", "dev_clk", "ddr_pll"};
0107 static const char *sd_clk_mux_p[] = { "dev_clk", "nand_pll", };
0108 static const char *uart_clk_mux_p[] = { "hosc", "dev_pll"};
0109 static const char *pwm_clk_mux_p[] = { "losc", "hosc"};
0110 static const char *gpu_clk_mux_p[] = { "dev_clk", "display_pll", "nand_pll", "ddr_clk", "cvbs_pll"};
0111 static const char *lcd_clk_mux_p[] = { "display_pll", "dev_clk" };
0112 static const char *i2s_clk_mux_p[] = { "audio_pll" };
0113 static const char *sensor_clk_mux_p[] = { "hosc", "si"};
0114
0115
0116 static OWL_MUX(clk_cpu, "cpu_clk", cpu_clk_mux_p, CMU_BUSCLK, 0, 2, CLK_SET_RATE_PARENT);
0117 static OWL_MUX(clk_dev, "dev_clk", dev_clk_p, CMU_DEVPLL, 12, 1, CLK_SET_RATE_PARENT);
0118 static OWL_MUX(clk_noc0_clk_mux, "noc0_clk_mux", noc_clk_mux_p, CMU_BUSCLK, 4, 3, CLK_SET_RATE_PARENT);
0119 static OWL_MUX(clk_noc1_clk_mux, "noc1_clk_mux", noc_clk_mux_p, CMU_BUSCLK1, 4, 3, CLK_SET_RATE_PARENT);
0120 static OWL_MUX(clk_hp_clk_mux, "hp_clk_mux", noc_clk_mux_p, CMU_BUSCLK1, 8, 3, CLK_SET_RATE_PARENT);
0121
0122 static struct clk_factor_table sd_factor_table[] = {
0123
0124 {0, 1, 1}, {1, 1, 2}, {2, 1, 3}, {3, 1, 4},
0125 {4, 1, 5}, {5, 1, 6}, {6, 1, 7}, {7, 1, 8},
0126 {8, 1, 9}, {9, 1, 10}, {10, 1, 11}, {11, 1, 12},
0127 {12, 1, 13}, {13, 1, 14}, {14, 1, 15}, {15, 1, 16},
0128 {16, 1, 17}, {17, 1, 18}, {18, 1, 19}, {19, 1, 20},
0129 {20, 1, 21}, {21, 1, 22}, {22, 1, 23}, {23, 1, 24},
0130 {24, 1, 25}, {25, 1, 26},
0131
0132
0133 {256, 1, 1 * 128}, {257, 1, 2 * 128}, {258, 1, 3 * 128}, {259, 1, 4 * 128},
0134 {260, 1, 5 * 128}, {261, 1, 6 * 128}, {262, 1, 7 * 128}, {263, 1, 8 * 128},
0135 {264, 1, 9 * 128}, {265, 1, 10 * 128}, {266, 1, 11 * 128}, {267, 1, 12 * 128},
0136 {268, 1, 13 * 128}, {269, 1, 14 * 128}, {270, 1, 15 * 128}, {271, 1, 16 * 128},
0137 {272, 1, 17 * 128}, {273, 1, 18 * 128}, {274, 1, 19 * 128}, {275, 1, 20 * 128},
0138 {276, 1, 21 * 128}, {277, 1, 22 * 128}, {278, 1, 23 * 128}, {279, 1, 24 * 128},
0139 {280, 1, 25 * 128}, {281, 1, 26 * 128},
0140
0141 { }
0142 };
0143
0144 static struct clk_factor_table lcd_factor_table[] = {
0145
0146 {0, 1, 1}, {1, 1, 2}, {2, 1, 3}, {3, 1, 4},
0147 {4, 1, 5}, {5, 1, 6}, {6, 1, 7}, {7, 1, 8},
0148 {8, 1, 9}, {9, 1, 10}, {10, 1, 11}, {11, 1, 12},
0149
0150
0151 {256, 1, 1 * 7}, {257, 1, 2 * 7}, {258, 1, 3 * 7}, {259, 1, 4 * 7},
0152 {260, 1, 5 * 7}, {261, 1, 6 * 7}, {262, 1, 7 * 7}, {263, 1, 8 * 7},
0153 {264, 1, 9 * 7}, {265, 1, 10 * 7}, {266, 1, 11 * 7}, {267, 1, 12 * 7},
0154 { }
0155 };
0156
0157 static struct clk_div_table hdmia_div_table[] = {
0158 {0, 1}, {1, 2}, {2, 3}, {3, 4},
0159 {4, 6}, {5, 8}, {6, 12}, {7, 16},
0160 {8, 24},
0161 { }
0162 };
0163
0164 static struct clk_div_table rmii_div_table[] = {
0165 {0, 4}, {1, 10},
0166 { }
0167 };
0168
0169
0170 static OWL_DIVIDER(clk_noc0, "noc0_clk", "noc0_clk_mux", CMU_BUSCLK, 16, 2, NULL, 0, 0);
0171 static OWL_DIVIDER(clk_noc1, "noc1_clk", "noc1_clk_mux", CMU_BUSCLK1, 16, 2, NULL, 0, 0);
0172 static OWL_DIVIDER(clk_noc1_clk_div, "noc1_clk_div", "noc1_clk", CMU_BUSCLK1, 20, 1, NULL, 0, 0);
0173 static OWL_DIVIDER(clk_hp_clk_div, "hp_clk_div", "hp_clk_mux", CMU_BUSCLK1, 12, 2, NULL, 0, 0);
0174 static OWL_DIVIDER(clk_ahb, "ahb_clk", "hp_clk_div", CMU_BUSCLK1, 2, 2, NULL, 0, 0);
0175 static OWL_DIVIDER(clk_apb, "apb_clk", "ahb_clk", CMU_BUSCLK1, 14, 2, NULL, 0, 0);
0176 static OWL_DIVIDER(clk_sensor0, "sensor0", "sensor_src", CMU_SENSORCLK, 0, 4, NULL, 0, 0);
0177 static OWL_DIVIDER(clk_sensor1, "sensor1", "sensor_src", CMU_SENSORCLK, 8, 4, NULL, 0, 0);
0178 static OWL_DIVIDER(clk_rmii_ref, "rmii_ref", "ethernet_pll", CMU_ETHERNETPLL, 2, 1, rmii_div_table, 0, 0);
0179
0180 static struct clk_factor_table de_factor_table[] = {
0181 {0, 1, 1}, {1, 2, 3}, {2, 1, 2}, {3, 2, 5},
0182 {4, 1, 3}, {5, 1, 4}, {6, 1, 6}, {7, 1, 8},
0183 {8, 1, 12},
0184 { }
0185 };
0186
0187 static struct clk_factor_table hde_factor_table[] = {
0188 {0, 1, 1}, {1, 2, 3}, {2, 1, 2}, {3, 2, 5},
0189 {4, 1, 3}, {5, 1, 4}, {6, 1, 6}, {7, 1, 8},
0190 { }
0191 };
0192
0193
0194 static OWL_GATE(clk_gpio, "gpio", "apb_clk", CMU_DEVCLKEN1, 25, 0, 0);
0195 static OWL_GATE(clk_dmac, "dmac", "hp_clk_div", CMU_DEVCLKEN0, 17, 0, 0);
0196 static OWL_GATE(clk_timer, "timer", "hosc", CMU_DEVCLKEN1, 22, 0, 0);
0197 static OWL_GATE_NO_PARENT(clk_dsi, "dsi_clk", CMU_DEVCLKEN0, 2, 0, 0);
0198 static OWL_GATE_NO_PARENT(clk_tvout, "tvout_clk", CMU_DEVCLKEN0, 3, 0, 0);
0199 static OWL_GATE_NO_PARENT(clk_hdmi_dev, "hdmi_dev", CMU_DEVCLKEN0, 5, 0, 0);
0200 static OWL_GATE_NO_PARENT(clk_usb3_480mpll0, "usb3_480mpll0", CMU_USBPLL, 3, 0, 0);
0201 static OWL_GATE_NO_PARENT(clk_usb3_480mphy0, "usb3_480mphy0", CMU_USBPLL, 2, 0, 0);
0202 static OWL_GATE_NO_PARENT(clk_usb3_5gphy, "usb3_5gphy", CMU_USBPLL, 1, 0, 0);
0203 static OWL_GATE_NO_PARENT(clk_usb3_cce, "usb3_cce", CMU_DEVCLKEN0, 25, 0, 0);
0204 static OWL_GATE(clk_i2c0, "i2c0", "hosc", CMU_DEVCLKEN1, 0, 0, 0);
0205 static OWL_GATE(clk_i2c1, "i2c1", "hosc", CMU_DEVCLKEN1, 1, 0, 0);
0206 static OWL_GATE(clk_i2c2, "i2c2", "hosc", CMU_DEVCLKEN1, 2, 0, 0);
0207 static OWL_GATE(clk_i2c3, "i2c3", "hosc", CMU_DEVCLKEN1, 3, 0, 0);
0208 static OWL_GATE(clk_spi0, "spi0", "ahb_clk", CMU_DEVCLKEN1, 4, 0, 0);
0209 static OWL_GATE(clk_spi1, "spi1", "ahb_clk", CMU_DEVCLKEN1, 5, 0, 0);
0210 static OWL_GATE(clk_spi2, "spi2", "ahb_clk", CMU_DEVCLKEN1, 6, 0, 0);
0211 static OWL_GATE(clk_spi3, "spi3", "ahb_clk", CMU_DEVCLKEN1, 7, 0, 0);
0212 static OWL_GATE_NO_PARENT(clk_usb2h0_pllen, "usbh0_pllen", CMU_USBPLL, 12, 0, 0);
0213 static OWL_GATE_NO_PARENT(clk_usb2h0_phy, "usbh0_phy", CMU_USBPLL, 10, 0, 0);
0214 static OWL_GATE_NO_PARENT(clk_usb2h0_cce, "usbh0_cce", CMU_DEVCLKEN0, 26, 0, 0);
0215 static OWL_GATE_NO_PARENT(clk_usb2h1_pllen, "usbh1_pllen", CMU_USBPLL, 13, 0, 0);
0216 static OWL_GATE_NO_PARENT(clk_usb2h1_phy, "usbh1_phy", CMU_USBPLL, 11, 0, 0);
0217 static OWL_GATE_NO_PARENT(clk_usb2h1_cce, "usbh1_cce", CMU_DEVCLKEN0, 27, 0, 0);
0218 static OWL_GATE_NO_PARENT(clk_irc_switch, "irc_switch", CMU_DEVCLKEN1, 15, 0, 0);
0219
0220
0221
0222 static OWL_COMP_DIV(clk_csi, "csi", csi_clk_mux_p,
0223 OWL_MUX_HW(CMU_CSICLK, 4, 1),
0224 OWL_GATE_HW(CMU_DEVCLKEN0, 13, 0),
0225 OWL_DIVIDER_HW(CMU_CSICLK, 0, 4, 0, NULL),
0226 0);
0227
0228 static OWL_COMP_DIV(clk_si, "si", csi_clk_mux_p,
0229 OWL_MUX_HW(CMU_SICLK, 4, 1),
0230 OWL_GATE_HW(CMU_DEVCLKEN0, 14, 0),
0231 OWL_DIVIDER_HW(CMU_SICLK, 0, 4, 0, NULL),
0232 0);
0233
0234 static OWL_COMP_FACTOR(clk_de, "de", de_clk_mux_p,
0235 OWL_MUX_HW(CMU_DECLK, 12, 1),
0236 OWL_GATE_HW(CMU_DEVCLKEN0, 0, 0),
0237 OWL_FACTOR_HW(CMU_DECLK, 0, 3, 0, de_factor_table),
0238 0);
0239
0240 static OWL_COMP_FACTOR(clk_hde, "hde", hde_clk_mux_p,
0241 OWL_MUX_HW(CMU_HDECLK, 4, 2),
0242 OWL_GATE_HW(CMU_DEVCLKEN0, 9, 0),
0243 OWL_FACTOR_HW(CMU_HDECLK, 0, 3, 0, hde_factor_table),
0244 0);
0245
0246 static OWL_COMP_FACTOR(clk_vde, "vde", hde_clk_mux_p,
0247 OWL_MUX_HW(CMU_VDECLK, 4, 2),
0248 OWL_GATE_HW(CMU_DEVCLKEN0, 10, 0),
0249 OWL_FACTOR_HW(CMU_VDECLK, 0, 3, 0, hde_factor_table),
0250 0);
0251
0252 static OWL_COMP_FACTOR(clk_vce, "vce", hde_clk_mux_p,
0253 OWL_MUX_HW(CMU_VCECLK, 4, 2),
0254 OWL_GATE_HW(CMU_DEVCLKEN0, 11, 0),
0255 OWL_FACTOR_HW(CMU_VCECLK, 0, 3, 0, hde_factor_table),
0256 0);
0257
0258 static OWL_COMP_DIV(clk_nand, "nand", nand_clk_mux_p,
0259 OWL_MUX_HW(CMU_NANDCCLK, 8, 2),
0260 OWL_GATE_HW(CMU_DEVCLKEN0, 21, 0),
0261 OWL_DIVIDER_HW(CMU_NANDCCLK, 0, 3, 0, NULL),
0262 CLK_SET_RATE_PARENT);
0263
0264 static OWL_COMP_FACTOR(clk_sd0, "sd0", sd_clk_mux_p,
0265 OWL_MUX_HW(CMU_SD0CLK, 9, 1),
0266 OWL_GATE_HW(CMU_DEVCLKEN0, 22, 0),
0267 OWL_FACTOR_HW(CMU_SD0CLK, 0, 9, 0, sd_factor_table),
0268 0);
0269
0270 static OWL_COMP_FACTOR(clk_sd1, "sd1", sd_clk_mux_p,
0271 OWL_MUX_HW(CMU_SD1CLK, 9, 1),
0272 OWL_GATE_HW(CMU_DEVCLKEN0, 23, 0),
0273 OWL_FACTOR_HW(CMU_SD1CLK, 0, 9, 0, sd_factor_table),
0274 0);
0275
0276 static OWL_COMP_FACTOR(clk_sd2, "sd2", sd_clk_mux_p,
0277 OWL_MUX_HW(CMU_SD2CLK, 9, 1),
0278 OWL_GATE_HW(CMU_DEVCLKEN0, 24, 0),
0279 OWL_FACTOR_HW(CMU_SD2CLK, 0, 9, 0, sd_factor_table),
0280 0);
0281
0282 static OWL_COMP_DIV(clk_uart0, "uart0", uart_clk_mux_p,
0283 OWL_MUX_HW(CMU_UART0CLK, 16, 1),
0284 OWL_GATE_HW(CMU_DEVCLKEN1, 8, 0),
0285 OWL_DIVIDER_HW(CMU_UART0CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
0286 0);
0287
0288 static OWL_COMP_DIV(clk_uart1, "uart1", uart_clk_mux_p,
0289 OWL_MUX_HW(CMU_UART1CLK, 16, 1),
0290 OWL_GATE_HW(CMU_DEVCLKEN1, 9, 0),
0291 OWL_DIVIDER_HW(CMU_UART1CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
0292 0);
0293
0294 static OWL_COMP_DIV(clk_uart2, "uart2", uart_clk_mux_p,
0295 OWL_MUX_HW(CMU_UART2CLK, 16, 1),
0296 OWL_GATE_HW(CMU_DEVCLKEN1, 10, 0),
0297 OWL_DIVIDER_HW(CMU_UART2CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
0298 0);
0299
0300 static OWL_COMP_DIV(clk_uart3, "uart3", uart_clk_mux_p,
0301 OWL_MUX_HW(CMU_UART3CLK, 16, 1),
0302 OWL_GATE_HW(CMU_DEVCLKEN1, 11, 0),
0303 OWL_DIVIDER_HW(CMU_UART3CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
0304 0);
0305
0306 static OWL_COMP_DIV(clk_uart4, "uart4", uart_clk_mux_p,
0307 OWL_MUX_HW(CMU_UART4CLK, 16, 1),
0308 OWL_GATE_HW(CMU_DEVCLKEN1, 12, 0),
0309 OWL_DIVIDER_HW(CMU_UART4CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
0310 0);
0311
0312 static OWL_COMP_DIV(clk_uart5, "uart5", uart_clk_mux_p,
0313 OWL_MUX_HW(CMU_UART5CLK, 16, 1),
0314 OWL_GATE_HW(CMU_DEVCLKEN1, 13, 0),
0315 OWL_DIVIDER_HW(CMU_UART5CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
0316 0);
0317
0318 static OWL_COMP_DIV(clk_uart6, "uart6", uart_clk_mux_p,
0319 OWL_MUX_HW(CMU_UART6CLK, 16, 1),
0320 OWL_GATE_HW(CMU_DEVCLKEN1, 14, 0),
0321 OWL_DIVIDER_HW(CMU_UART6CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL),
0322 0);
0323
0324 static OWL_COMP_DIV(clk_pwm0, "pwm0", pwm_clk_mux_p,
0325 OWL_MUX_HW(CMU_PWM0CLK, 12, 1),
0326 OWL_GATE_HW(CMU_DEVCLKEN1, 16, 0),
0327 OWL_DIVIDER_HW(CMU_PWM0CLK, 0, 10, 0, NULL),
0328 CLK_IGNORE_UNUSED);
0329
0330 static OWL_COMP_DIV(clk_pwm1, "pwm1", pwm_clk_mux_p,
0331 OWL_MUX_HW(CMU_PWM1CLK, 12, 1),
0332 OWL_GATE_HW(CMU_DEVCLKEN1, 17, 0),
0333 OWL_DIVIDER_HW(CMU_PWM1CLK, 0, 10, 0, NULL),
0334 0);
0335
0336 static OWL_COMP_DIV(clk_pwm2, "pwm2", pwm_clk_mux_p,
0337 OWL_MUX_HW(CMU_PWM2CLK, 12, 1),
0338 OWL_GATE_HW(CMU_DEVCLKEN1, 18, 0),
0339 OWL_DIVIDER_HW(CMU_PWM2CLK, 0, 10, 0, NULL),
0340 0);
0341
0342 static OWL_COMP_DIV(clk_pwm3, "pwm3", pwm_clk_mux_p,
0343 OWL_MUX_HW(CMU_PWM3CLK, 12, 1),
0344 OWL_GATE_HW(CMU_DEVCLKEN1, 19, 0),
0345 OWL_DIVIDER_HW(CMU_PWM3CLK, 0, 10, 0, NULL),
0346 0);
0347
0348 static OWL_COMP_DIV(clk_pwm4, "pwm4", pwm_clk_mux_p,
0349 OWL_MUX_HW(CMU_PWM4CLK, 12, 1),
0350 OWL_GATE_HW(CMU_DEVCLKEN1, 20, 0),
0351 OWL_DIVIDER_HW(CMU_PWM4CLK, 0, 10, 0, NULL),
0352 0);
0353
0354 static OWL_COMP_DIV(clk_pwm5, "pwm5", pwm_clk_mux_p,
0355 OWL_MUX_HW(CMU_PWM5CLK, 12, 1),
0356 OWL_GATE_HW(CMU_DEVCLKEN1, 21, 0),
0357 OWL_DIVIDER_HW(CMU_PWM5CLK, 0, 10, 0, NULL),
0358 0);
0359
0360 static OWL_COMP_FACTOR(clk_gpu3d, "gpu3d", gpu_clk_mux_p,
0361 OWL_MUX_HW(CMU_GPU3DCLK, 4, 3),
0362 OWL_GATE_HW(CMU_DEVCLKEN0, 8, 0),
0363 OWL_FACTOR_HW(CMU_GPU3DCLK, 0, 3, 0, hde_factor_table),
0364 0);
0365
0366 static OWL_COMP_FACTOR(clk_lcd, "lcd", lcd_clk_mux_p,
0367 OWL_MUX_HW(CMU_LCDCLK, 12, 2),
0368 OWL_GATE_HW(CMU_DEVCLKEN0, 1, 0),
0369 OWL_FACTOR_HW(CMU_LCDCLK, 0, 9, 0, lcd_factor_table),
0370 0);
0371
0372 static OWL_COMP_DIV(clk_hdmi_audio, "hdmia", i2s_clk_mux_p,
0373 OWL_MUX_HW(CMU_AUDIOPLL, 24, 1),
0374 OWL_GATE_HW(CMU_DEVCLKEN1, 28, 0),
0375 OWL_DIVIDER_HW(CMU_AUDIOPLL, 24, 4, 0, hdmia_div_table),
0376 0);
0377
0378 static OWL_COMP_DIV(clk_i2srx, "i2srx", i2s_clk_mux_p,
0379 OWL_MUX_HW(CMU_AUDIOPLL, 24, 1),
0380 OWL_GATE_HW(CMU_DEVCLKEN1, 27, 0),
0381 OWL_DIVIDER_HW(CMU_AUDIOPLL, 20, 4, 0, hdmia_div_table),
0382 0);
0383
0384 static OWL_COMP_DIV(clk_i2stx, "i2stx", i2s_clk_mux_p,
0385 OWL_MUX_HW(CMU_AUDIOPLL, 24, 1),
0386 OWL_GATE_HW(CMU_DEVCLKEN1, 26, 0),
0387 OWL_DIVIDER_HW(CMU_AUDIOPLL, 16, 4, 0, hdmia_div_table),
0388 0);
0389
0390
0391 static OWL_COMP_FIXED_FACTOR(clk_pcm1, "pcm1", "audio_pll",
0392 OWL_GATE_HW(CMU_DEVCLKEN1, 31, 0),
0393 1, 2, 0);
0394
0395 static OWL_COMP_DIV(clk_sensor_src, "sensor_src", sensor_clk_mux_p,
0396 OWL_MUX_HW(CMU_SENSORCLK, 4, 1),
0397 {0},
0398 OWL_DIVIDER_HW(CMU_SENSORCLK, 5, 2, 0, NULL),
0399 0);
0400
0401 static OWL_COMP_FIXED_FACTOR(clk_ethernet, "ethernet", "ethernet_pll",
0402 OWL_GATE_HW(CMU_DEVCLKEN1, 23, 0),
0403 1, 20, 0);
0404
0405 static OWL_COMP_DIV_FIXED(clk_thermal_sensor, "thermal_sensor", "hosc",
0406 OWL_GATE_HW(CMU_DEVCLKEN0, 31, 0),
0407 OWL_DIVIDER_HW(CMU_SSTSCLK, 20, 10, 0, NULL),
0408 0);
0409
0410 static struct owl_clk_common *s700_clks[] = {
0411 &clk_core_pll.common,
0412 &clk_dev_pll.common,
0413 &clk_ddr_pll.common,
0414 &clk_nand_pll.common,
0415 &clk_display_pll.common,
0416 &clk_cvbs_pll .common,
0417 &clk_audio_pll.common,
0418 &clk_ethernet_pll.common,
0419 &clk_cpu.common,
0420 &clk_dev.common,
0421 &clk_ahb.common,
0422 &clk_apb.common,
0423 &clk_dmac.common,
0424 &clk_noc0_clk_mux.common,
0425 &clk_noc1_clk_mux.common,
0426 &clk_hp_clk_mux.common,
0427 &clk_hp_clk_div.common,
0428 &clk_noc1_clk_div.common,
0429 &clk_noc0.common,
0430 &clk_noc1.common,
0431 &clk_sensor_src.common,
0432 &clk_gpio.common,
0433 &clk_timer.common,
0434 &clk_dsi.common,
0435 &clk_csi.common,
0436 &clk_si.common,
0437 &clk_de.common,
0438 &clk_hde.common,
0439 &clk_vde.common,
0440 &clk_vce.common,
0441 &clk_nand.common,
0442 &clk_sd0.common,
0443 &clk_sd1.common,
0444 &clk_sd2.common,
0445 &clk_uart0.common,
0446 &clk_uart1.common,
0447 &clk_uart2.common,
0448 &clk_uart3.common,
0449 &clk_uart4.common,
0450 &clk_uart5.common,
0451 &clk_uart6.common,
0452 &clk_pwm0.common,
0453 &clk_pwm1.common,
0454 &clk_pwm2.common,
0455 &clk_pwm3.common,
0456 &clk_pwm4.common,
0457 &clk_pwm5.common,
0458 &clk_gpu3d.common,
0459 &clk_i2c0.common,
0460 &clk_i2c1.common,
0461 &clk_i2c2.common,
0462 &clk_i2c3.common,
0463 &clk_spi0.common,
0464 &clk_spi1.common,
0465 &clk_spi2.common,
0466 &clk_spi3.common,
0467 &clk_usb3_480mpll0.common,
0468 &clk_usb3_480mphy0.common,
0469 &clk_usb3_5gphy.common,
0470 &clk_usb3_cce.common,
0471 &clk_lcd.common,
0472 &clk_hdmi_audio.common,
0473 &clk_i2srx.common,
0474 &clk_i2stx.common,
0475 &clk_sensor0.common,
0476 &clk_sensor1.common,
0477 &clk_hdmi_dev.common,
0478 &clk_ethernet.common,
0479 &clk_rmii_ref.common,
0480 &clk_usb2h0_pllen.common,
0481 &clk_usb2h0_phy.common,
0482 &clk_usb2h0_cce.common,
0483 &clk_usb2h1_pllen.common,
0484 &clk_usb2h1_phy.common,
0485 &clk_usb2h1_cce.common,
0486 &clk_tvout.common,
0487 &clk_thermal_sensor.common,
0488 &clk_irc_switch.common,
0489 &clk_pcm1.common,
0490 };
0491
0492 static struct clk_hw_onecell_data s700_hw_clks = {
0493 .hws = {
0494 [CLK_CORE_PLL] = &clk_core_pll.common.hw,
0495 [CLK_DEV_PLL] = &clk_dev_pll.common.hw,
0496 [CLK_DDR_PLL] = &clk_ddr_pll.common.hw,
0497 [CLK_NAND_PLL] = &clk_nand_pll.common.hw,
0498 [CLK_DISPLAY_PLL] = &clk_display_pll.common.hw,
0499 [CLK_CVBS_PLL] = &clk_cvbs_pll .common.hw,
0500 [CLK_AUDIO_PLL] = &clk_audio_pll.common.hw,
0501 [CLK_ETHERNET_PLL] = &clk_ethernet_pll.common.hw,
0502 [CLK_CPU] = &clk_cpu.common.hw,
0503 [CLK_DEV] = &clk_dev.common.hw,
0504 [CLK_AHB] = &clk_ahb.common.hw,
0505 [CLK_APB] = &clk_apb.common.hw,
0506 [CLK_DMAC] = &clk_dmac.common.hw,
0507 [CLK_NOC0_CLK_MUX] = &clk_noc0_clk_mux.common.hw,
0508 [CLK_NOC1_CLK_MUX] = &clk_noc1_clk_mux.common.hw,
0509 [CLK_HP_CLK_MUX] = &clk_hp_clk_mux.common.hw,
0510 [CLK_HP_CLK_DIV] = &clk_hp_clk_div.common.hw,
0511 [CLK_NOC1_CLK_DIV] = &clk_noc1_clk_div.common.hw,
0512 [CLK_NOC0] = &clk_noc0.common.hw,
0513 [CLK_NOC1] = &clk_noc1.common.hw,
0514 [CLK_SENOR_SRC] = &clk_sensor_src.common.hw,
0515 [CLK_GPIO] = &clk_gpio.common.hw,
0516 [CLK_TIMER] = &clk_timer.common.hw,
0517 [CLK_DSI] = &clk_dsi.common.hw,
0518 [CLK_CSI] = &clk_csi.common.hw,
0519 [CLK_SI] = &clk_si.common.hw,
0520 [CLK_DE] = &clk_de.common.hw,
0521 [CLK_HDE] = &clk_hde.common.hw,
0522 [CLK_VDE] = &clk_vde.common.hw,
0523 [CLK_VCE] = &clk_vce.common.hw,
0524 [CLK_NAND] = &clk_nand.common.hw,
0525 [CLK_SD0] = &clk_sd0.common.hw,
0526 [CLK_SD1] = &clk_sd1.common.hw,
0527 [CLK_SD2] = &clk_sd2.common.hw,
0528 [CLK_UART0] = &clk_uart0.common.hw,
0529 [CLK_UART1] = &clk_uart1.common.hw,
0530 [CLK_UART2] = &clk_uart2.common.hw,
0531 [CLK_UART3] = &clk_uart3.common.hw,
0532 [CLK_UART4] = &clk_uart4.common.hw,
0533 [CLK_UART5] = &clk_uart5.common.hw,
0534 [CLK_UART6] = &clk_uart6.common.hw,
0535 [CLK_PWM0] = &clk_pwm0.common.hw,
0536 [CLK_PWM1] = &clk_pwm1.common.hw,
0537 [CLK_PWM2] = &clk_pwm2.common.hw,
0538 [CLK_PWM3] = &clk_pwm3.common.hw,
0539 [CLK_PWM4] = &clk_pwm4.common.hw,
0540 [CLK_PWM5] = &clk_pwm5.common.hw,
0541 [CLK_GPU3D] = &clk_gpu3d.common.hw,
0542 [CLK_I2C0] = &clk_i2c0.common.hw,
0543 [CLK_I2C1] = &clk_i2c1.common.hw,
0544 [CLK_I2C2] = &clk_i2c2.common.hw,
0545 [CLK_I2C3] = &clk_i2c3.common.hw,
0546 [CLK_SPI0] = &clk_spi0.common.hw,
0547 [CLK_SPI1] = &clk_spi1.common.hw,
0548 [CLK_SPI2] = &clk_spi2.common.hw,
0549 [CLK_SPI3] = &clk_spi3.common.hw,
0550 [CLK_USB3_480MPLL0] = &clk_usb3_480mpll0.common.hw,
0551 [CLK_USB3_480MPHY0] = &clk_usb3_480mphy0.common.hw,
0552 [CLK_USB3_5GPHY] = &clk_usb3_5gphy.common.hw,
0553 [CLK_USB3_CCE] = &clk_usb3_cce.common.hw,
0554 [CLK_LCD] = &clk_lcd.common.hw,
0555 [CLK_HDMI_AUDIO] = &clk_hdmi_audio.common.hw,
0556 [CLK_I2SRX] = &clk_i2srx.common.hw,
0557 [CLK_I2STX] = &clk_i2stx.common.hw,
0558 [CLK_SENSOR0] = &clk_sensor0.common.hw,
0559 [CLK_SENSOR1] = &clk_sensor1.common.hw,
0560 [CLK_HDMI_DEV] = &clk_hdmi_dev.common.hw,
0561 [CLK_ETHERNET] = &clk_ethernet.common.hw,
0562 [CLK_RMII_REF] = &clk_rmii_ref.common.hw,
0563 [CLK_USB2H0_PLLEN] = &clk_usb2h0_pllen.common.hw,
0564 [CLK_USB2H0_PHY] = &clk_usb2h0_phy.common.hw,
0565 [CLK_USB2H0_CCE] = &clk_usb2h0_cce.common.hw,
0566 [CLK_USB2H1_PLLEN] = &clk_usb2h1_pllen.common.hw,
0567 [CLK_USB2H1_PHY] = &clk_usb2h1_phy.common.hw,
0568 [CLK_USB2H1_CCE] = &clk_usb2h1_cce.common.hw,
0569 [CLK_TVOUT] = &clk_tvout.common.hw,
0570 [CLK_THERMAL_SENSOR] = &clk_thermal_sensor.common.hw,
0571 [CLK_IRC_SWITCH] = &clk_irc_switch.common.hw,
0572 [CLK_PCM1] = &clk_pcm1.common.hw,
0573 },
0574 .num = CLK_NR_CLKS,
0575 };
0576
0577 static const struct owl_reset_map s700_resets[] = {
0578 [RESET_DE] = { CMU_DEVRST0, BIT(0) },
0579 [RESET_LCD0] = { CMU_DEVRST0, BIT(1) },
0580 [RESET_DSI] = { CMU_DEVRST0, BIT(2) },
0581 [RESET_CSI] = { CMU_DEVRST0, BIT(13) },
0582 [RESET_SI] = { CMU_DEVRST0, BIT(14) },
0583 [RESET_I2C0] = { CMU_DEVRST1, BIT(0) },
0584 [RESET_I2C1] = { CMU_DEVRST1, BIT(1) },
0585 [RESET_I2C2] = { CMU_DEVRST1, BIT(2) },
0586 [RESET_I2C3] = { CMU_DEVRST1, BIT(3) },
0587 [RESET_SPI0] = { CMU_DEVRST1, BIT(4) },
0588 [RESET_SPI1] = { CMU_DEVRST1, BIT(5) },
0589 [RESET_SPI2] = { CMU_DEVRST1, BIT(6) },
0590 [RESET_SPI3] = { CMU_DEVRST1, BIT(7) },
0591 [RESET_UART0] = { CMU_DEVRST1, BIT(8) },
0592 [RESET_UART1] = { CMU_DEVRST1, BIT(9) },
0593 [RESET_UART2] = { CMU_DEVRST1, BIT(10) },
0594 [RESET_UART3] = { CMU_DEVRST1, BIT(11) },
0595 [RESET_UART4] = { CMU_DEVRST1, BIT(12) },
0596 [RESET_UART5] = { CMU_DEVRST1, BIT(13) },
0597 [RESET_UART6] = { CMU_DEVRST1, BIT(14) },
0598 [RESET_KEY] = { CMU_DEVRST1, BIT(24) },
0599 [RESET_GPIO] = { CMU_DEVRST1, BIT(25) },
0600 [RESET_AUDIO] = { CMU_DEVRST1, BIT(29) },
0601 };
0602
0603 static struct owl_clk_desc s700_clk_desc = {
0604 .clks = s700_clks,
0605 .num_clks = ARRAY_SIZE(s700_clks),
0606
0607 .hw_clks = &s700_hw_clks,
0608
0609 .resets = s700_resets,
0610 .num_resets = ARRAY_SIZE(s700_resets),
0611 };
0612
0613 static int s700_clk_probe(struct platform_device *pdev)
0614 {
0615 struct owl_clk_desc *desc;
0616 struct owl_reset *reset;
0617 int ret;
0618
0619 desc = &s700_clk_desc;
0620 owl_clk_regmap_init(pdev, desc);
0621
0622
0623
0624
0625
0626 reset = devm_kzalloc(&pdev->dev, sizeof(*reset), GFP_KERNEL);
0627 if (!reset)
0628 return -ENOMEM;
0629
0630 reset->rcdev.of_node = pdev->dev.of_node;
0631 reset->rcdev.ops = &owl_reset_ops;
0632 reset->rcdev.nr_resets = desc->num_resets;
0633 reset->reset_map = desc->resets;
0634 reset->regmap = desc->regmap;
0635
0636 ret = devm_reset_controller_register(&pdev->dev, &reset->rcdev);
0637 if (ret)
0638 dev_err(&pdev->dev, "Failed to register reset controller\n");
0639
0640 return owl_clk_probe(&pdev->dev, desc->hw_clks);
0641 }
0642
0643 static const struct of_device_id s700_clk_of_match[] = {
0644 { .compatible = "actions,s700-cmu", },
0645 { }
0646 };
0647
0648 static struct platform_driver s700_clk_driver = {
0649 .probe = s700_clk_probe,
0650 .driver = {
0651 .name = "s700-cmu",
0652 .of_match_table = s700_clk_of_match
0653 },
0654 };
0655
0656 static int __init s700_clk_init(void)
0657 {
0658 return platform_driver_register(&s700_clk_driver);
0659 }
0660 core_initcall(s700_clk_init);
