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0015 #include <linux/clk-provider.h>
0016 #include <linux/platform_device.h>
0017
0018 #include "owl-common.h"
0019 #include "owl-composite.h"
0020 #include "owl-divider.h"
0021 #include "owl-factor.h"
0022 #include "owl-fixed-factor.h"
0023 #include "owl-gate.h"
0024 #include "owl-mux.h"
0025 #include "owl-pll.h"
0026 #include "owl-reset.h"
0027
0028 #include <dt-bindings/clock/actions,s500-cmu.h>
0029 #include <dt-bindings/reset/actions,s500-reset.h>
0030
0031 #define CMU_COREPLL (0x0000)
0032 #define CMU_DEVPLL (0x0004)
0033 #define CMU_DDRPLL (0x0008)
0034 #define CMU_NANDPLL (0x000C)
0035 #define CMU_DISPLAYPLL (0x0010)
0036 #define CMU_AUDIOPLL (0x0014)
0037 #define CMU_TVOUTPLL (0x0018)
0038 #define CMU_BUSCLK (0x001C)
0039 #define CMU_SENSORCLK (0x0020)
0040 #define CMU_LCDCLK (0x0024)
0041 #define CMU_DSICLK (0x0028)
0042 #define CMU_CSICLK (0x002C)
0043 #define CMU_DECLK (0x0030)
0044 #define CMU_BISPCLK (0x0034)
0045 #define CMU_BUSCLK1 (0x0038)
0046 #define CMU_VDECLK (0x0040)
0047 #define CMU_VCECLK (0x0044)
0048 #define CMU_NANDCCLK (0x004C)
0049 #define CMU_SD0CLK (0x0050)
0050 #define CMU_SD1CLK (0x0054)
0051 #define CMU_SD2CLK (0x0058)
0052 #define CMU_UART0CLK (0x005C)
0053 #define CMU_UART1CLK (0x0060)
0054 #define CMU_UART2CLK (0x0064)
0055 #define CMU_PWM4CLK (0x0068)
0056 #define CMU_PWM5CLK (0x006C)
0057 #define CMU_PWM0CLK (0x0070)
0058 #define CMU_PWM1CLK (0x0074)
0059 #define CMU_PWM2CLK (0x0078)
0060 #define CMU_PWM3CLK (0x007C)
0061 #define CMU_USBPLL (0x0080)
0062 #define CMU_ETHERNETPLL (0x0084)
0063 #define CMU_CVBSPLL (0x0088)
0064 #define CMU_LENSCLK (0x008C)
0065 #define CMU_GPU3DCLK (0x0090)
0066 #define CMU_CORECTL (0x009C)
0067 #define CMU_DEVCLKEN0 (0x00A0)
0068 #define CMU_DEVCLKEN1 (0x00A4)
0069 #define CMU_DEVRST0 (0x00A8)
0070 #define CMU_DEVRST1 (0x00AC)
0071 #define CMU_UART3CLK (0x00B0)
0072 #define CMU_UART4CLK (0x00B4)
0073 #define CMU_UART5CLK (0x00B8)
0074 #define CMU_UART6CLK (0x00BC)
0075 #define CMU_SSCLK (0x00C0)
0076 #define CMU_DIGITALDEBUG (0x00D0)
0077 #define CMU_ANALOGDEBUG (0x00D4)
0078 #define CMU_COREPLLDEBUG (0x00D8)
0079 #define CMU_DEVPLLDEBUG (0x00DC)
0080 #define CMU_DDRPLLDEBUG (0x00E0)
0081 #define CMU_NANDPLLDEBUG (0x00E4)
0082 #define CMU_DISPLAYPLLDEBUG (0x00E8)
0083 #define CMU_TVOUTPLLDEBUG (0x00EC)
0084 #define CMU_DEEPCOLORPLLDEBUG (0x00F4)
0085 #define CMU_AUDIOPLL_ETHPLLDEBUG (0x00F8)
0086 #define CMU_CVBSPLLDEBUG (0x00FC)
0087
0088 #define OWL_S500_COREPLL_DELAY (150)
0089 #define OWL_S500_DDRPLL_DELAY (63)
0090 #define OWL_S500_DEVPLL_DELAY (28)
0091 #define OWL_S500_NANDPLL_DELAY (44)
0092 #define OWL_S500_DISPLAYPLL_DELAY (57)
0093 #define OWL_S500_ETHERNETPLL_DELAY (25)
0094 #define OWL_S500_AUDIOPLL_DELAY (100)
0095
0096 static const struct clk_pll_table clk_audio_pll_table[] = {
0097 { 0, 45158400 }, { 1, 49152000 },
0098 { }
0099 };
0100
0101
0102 static OWL_PLL_NO_PARENT_DELAY(ethernet_pll_clk, "ethernet_pll_clk", CMU_ETHERNETPLL, 500000000, 0, 0, 0, 0, 0, OWL_S500_ETHERNETPLL_DELAY, NULL, CLK_IGNORE_UNUSED);
0103 static OWL_PLL_NO_PARENT_DELAY(core_pll_clk, "core_pll_clk", CMU_COREPLL, 12000000, 9, 0, 8, 4, 134, OWL_S500_COREPLL_DELAY, NULL, CLK_IGNORE_UNUSED);
0104 static OWL_PLL_NO_PARENT_DELAY(ddr_pll_clk, "ddr_pll_clk", CMU_DDRPLL, 12000000, 8, 0, 8, 1, 67, OWL_S500_DDRPLL_DELAY, NULL, CLK_IGNORE_UNUSED);
0105 static OWL_PLL_NO_PARENT_DELAY(nand_pll_clk, "nand_pll_clk", CMU_NANDPLL, 6000000, 8, 0, 7, 2, 86, OWL_S500_NANDPLL_DELAY, NULL, CLK_IGNORE_UNUSED);
0106 static OWL_PLL_NO_PARENT_DELAY(display_pll_clk, "display_pll_clk", CMU_DISPLAYPLL, 6000000, 8, 0, 8, 2, 126, OWL_S500_DISPLAYPLL_DELAY, NULL, CLK_IGNORE_UNUSED);
0107 static OWL_PLL_NO_PARENT_DELAY(dev_pll_clk, "dev_pll_clk", CMU_DEVPLL, 6000000, 8, 0, 7, 8, 126, OWL_S500_DEVPLL_DELAY, NULL, CLK_IGNORE_UNUSED);
0108 static OWL_PLL_NO_PARENT_DELAY(audio_pll_clk, "audio_pll_clk", CMU_AUDIOPLL, 0, 4, 0, 1, 0, 0, OWL_S500_AUDIOPLL_DELAY, clk_audio_pll_table, CLK_IGNORE_UNUSED);
0109
0110 static const char * const dev_clk_mux_p[] = { "hosc", "dev_pll_clk" };
0111 static const char * const bisp_clk_mux_p[] = { "display_pll_clk", "dev_clk" };
0112 static const char * const sensor_clk_mux_p[] = { "hosc", "bisp_clk" };
0113 static const char * const sd_clk_mux_p[] = { "dev_clk", "nand_pll_clk" };
0114 static const char * const pwm_clk_mux_p[] = { "losc", "hosc" };
0115 static const char * const ahbprediv_clk_mux_p[] = { "dev_clk", "display_pll_clk", "nand_pll_clk", "ddr_pll_clk" };
0116 static const char * const nic_clk_mux_p[] = { "dev_clk", "display_pll_clk", "nand_pll_clk", "ddr_pll_clk" };
0117 static const char * const uart_clk_mux_p[] = { "hosc", "dev_pll_clk" };
0118 static const char * const de_clk_mux_p[] = { "display_pll_clk", "dev_clk" };
0119 static const char * const i2s_clk_mux_p[] = { "audio_pll_clk" };
0120 static const char * const hde_clk_mux_p[] = { "dev_clk", "display_pll_clk", "nand_pll_clk", "ddr_pll_clk" };
0121 static const char * const nand_clk_mux_p[] = { "nand_pll_clk", "display_pll_clk", "dev_clk", "ddr_pll_clk" };
0122
0123 static struct clk_factor_table sd_factor_table[] = {
0124
0125 { 0, 1, 1 }, { 1, 1, 2 }, { 2, 1, 3 }, { 3, 1, 4 },
0126 { 4, 1, 5 }, { 5, 1, 6 }, { 6, 1, 7 }, { 7, 1, 8 },
0127 { 8, 1, 9 }, { 9, 1, 10 }, { 10, 1, 11 }, { 11, 1, 12 },
0128 { 12, 1, 13 }, { 13, 1, 14 }, { 14, 1, 15 }, { 15, 1, 16 },
0129 { 16, 1, 17 }, { 17, 1, 18 }, { 18, 1, 19 }, { 19, 1, 20 },
0130 { 20, 1, 21 }, { 21, 1, 22 }, { 22, 1, 23 }, { 23, 1, 24 },
0131 { 24, 1, 25 },
0132
0133
0134 { 256, 1, 1 * 128 }, { 257, 1, 2 * 128 }, { 258, 1, 3 * 128 }, { 259, 1, 4 * 128 },
0135 { 260, 1, 5 * 128 }, { 261, 1, 6 * 128 }, { 262, 1, 7 * 128 }, { 263, 1, 8 * 128 },
0136 { 264, 1, 9 * 128 }, { 265, 1, 10 * 128 }, { 266, 1, 11 * 128 }, { 267, 1, 12 * 128 },
0137 { 268, 1, 13 * 128 }, { 269, 1, 14 * 128 }, { 270, 1, 15 * 128 }, { 271, 1, 16 * 128 },
0138 { 272, 1, 17 * 128 }, { 273, 1, 18 * 128 }, { 274, 1, 19 * 128 }, { 275, 1, 20 * 128 },
0139 { 276, 1, 21 * 128 }, { 277, 1, 22 * 128 }, { 278, 1, 23 * 128 }, { 279, 1, 24 * 128 },
0140 { 280, 1, 25 * 128 },
0141 { }
0142 };
0143
0144 static struct clk_factor_table de_factor_table[] = {
0145 { 0, 1, 1 }, { 1, 2, 3 }, { 2, 1, 2 }, { 3, 2, 5 },
0146 { 4, 1, 3 }, { 5, 1, 4 }, { 6, 1, 6 }, { 7, 1, 8 },
0147 { 8, 1, 12 },
0148 { }
0149 };
0150
0151 static struct clk_factor_table hde_factor_table[] = {
0152 { 0, 1, 1 }, { 1, 2, 3 }, { 2, 1, 2 }, { 3, 2, 5 },
0153 { 4, 1, 3 }, { 5, 1, 4 }, { 6, 1, 6 }, { 7, 1, 8 },
0154 { }
0155 };
0156
0157 static struct clk_div_table rmii_ref_div_table[] = {
0158 { 0, 4 }, { 1, 10 },
0159 { }
0160 };
0161
0162 static struct clk_div_table std12rate_div_table[] = {
0163 { 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 },
0164 { 4, 5 }, { 5, 6 }, { 6, 7 }, { 7, 8 },
0165 { 8, 9 }, { 9, 10 }, { 10, 11 }, { 11, 12 },
0166 { }
0167 };
0168
0169 static struct clk_div_table i2s_div_table[] = {
0170 { 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 },
0171 { 4, 6 }, { 5, 8 }, { 6, 12 }, { 7, 16 },
0172 { 8, 24 },
0173 { }
0174 };
0175
0176 static struct clk_div_table nand_div_table[] = {
0177 { 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 6 },
0178 { 4, 8 }, { 5, 10 }, { 6, 12 }, { 7, 14 },
0179 { 8, 16 }, { 9, 18 }, { 10, 20 }, { 11, 22 },
0180 { }
0181 };
0182
0183
0184 static OWL_MUX(dev_clk, "dev_clk", dev_clk_mux_p, CMU_DEVPLL, 12, 1, CLK_SET_RATE_PARENT);
0185
0186
0187 static OWL_GATE(gpio_clk, "gpio_clk", "apb_clk", CMU_DEVCLKEN0, 18, 0, 0);
0188 static OWL_GATE(dmac_clk, "dmac_clk", "h_clk", CMU_DEVCLKEN0, 1, 0, 0);
0189 static OWL_GATE(spi0_clk, "spi0_clk", "ahb_clk", CMU_DEVCLKEN1, 10, 0, CLK_IGNORE_UNUSED);
0190 static OWL_GATE(spi1_clk, "spi1_clk", "ahb_clk", CMU_DEVCLKEN1, 11, 0, CLK_IGNORE_UNUSED);
0191 static OWL_GATE(spi2_clk, "spi2_clk", "ahb_clk", CMU_DEVCLKEN1, 12, 0, CLK_IGNORE_UNUSED);
0192 static OWL_GATE(spi3_clk, "spi3_clk", "ahb_clk", CMU_DEVCLKEN1, 13, 0, CLK_IGNORE_UNUSED);
0193 static OWL_GATE(timer_clk, "timer_clk", "hosc", CMU_DEVCLKEN1, 27, 0, 0);
0194 static OWL_GATE(hdmi_clk, "hdmi_clk", "hosc", CMU_DEVCLKEN1, 3, 0, 0);
0195
0196
0197 static OWL_DIVIDER(h_clk, "h_clk", "ahbprediv_clk", CMU_BUSCLK1, 2, 2, NULL, 0, 0);
0198 static OWL_DIVIDER(apb_clk, "apb_clk", "nic_clk", CMU_BUSCLK1, 14, 2, NULL, 0, 0);
0199 static OWL_DIVIDER(rmii_ref_clk, "rmii_ref_clk", "ethernet_pll_clk", CMU_ETHERNETPLL, 1, 1, rmii_ref_div_table, 0, 0);
0200
0201
0202 static OWL_FACTOR(de1_clk, "de_clk1", "de_clk", CMU_DECLK, 0, 4, de_factor_table, 0, 0);
0203 static OWL_FACTOR(de2_clk, "de_clk2", "de_clk", CMU_DECLK, 4, 4, de_factor_table, 0, 0);
0204
0205
0206 static OWL_COMP_DIV(nic_clk, "nic_clk", nic_clk_mux_p,
0207 OWL_MUX_HW(CMU_BUSCLK1, 4, 3),
0208 { 0 },
0209 OWL_DIVIDER_HW(CMU_BUSCLK1, 16, 2, 0, NULL),
0210 0);
0211
0212 static OWL_COMP_DIV(ahbprediv_clk, "ahbprediv_clk", ahbprediv_clk_mux_p,
0213 OWL_MUX_HW(CMU_BUSCLK1, 8, 3),
0214 { 0 },
0215 OWL_DIVIDER_HW(CMU_BUSCLK1, 12, 2, 0, NULL),
0216 CLK_SET_RATE_PARENT);
0217
0218 static OWL_COMP_FIXED_FACTOR(ahb_clk, "ahb_clk", "h_clk",
0219 { 0 },
0220 1, 1, 0);
0221
0222 static OWL_COMP_FACTOR(vce_clk, "vce_clk", hde_clk_mux_p,
0223 OWL_MUX_HW(CMU_VCECLK, 4, 2),
0224 OWL_GATE_HW(CMU_DEVCLKEN0, 26, 0),
0225 OWL_FACTOR_HW(CMU_VCECLK, 0, 3, 0, hde_factor_table),
0226 0);
0227
0228 static OWL_COMP_FACTOR(vde_clk, "vde_clk", hde_clk_mux_p,
0229 OWL_MUX_HW(CMU_VDECLK, 4, 2),
0230 OWL_GATE_HW(CMU_DEVCLKEN0, 25, 0),
0231 OWL_FACTOR_HW(CMU_VDECLK, 0, 3, 0, hde_factor_table),
0232 0);
0233
0234 static OWL_COMP_DIV(bisp_clk, "bisp_clk", bisp_clk_mux_p,
0235 OWL_MUX_HW(CMU_BISPCLK, 4, 1),
0236 OWL_GATE_HW(CMU_DEVCLKEN0, 14, 0),
0237 OWL_DIVIDER_HW(CMU_BISPCLK, 0, 4, 0, std12rate_div_table),
0238 0);
0239
0240 static OWL_COMP_DIV(sensor0_clk, "sensor0_clk", sensor_clk_mux_p,
0241 OWL_MUX_HW(CMU_SENSORCLK, 4, 1),
0242 OWL_GATE_HW(CMU_DEVCLKEN0, 14, 0),
0243 OWL_DIVIDER_HW(CMU_SENSORCLK, 0, 4, 0, std12rate_div_table),
0244 0);
0245
0246 static OWL_COMP_DIV(sensor1_clk, "sensor1_clk", sensor_clk_mux_p,
0247 OWL_MUX_HW(CMU_SENSORCLK, 4, 1),
0248 OWL_GATE_HW(CMU_DEVCLKEN0, 14, 0),
0249 OWL_DIVIDER_HW(CMU_SENSORCLK, 8, 4, 0, std12rate_div_table),
0250 0);
0251
0252 static OWL_COMP_FACTOR(sd0_clk, "sd0_clk", sd_clk_mux_p,
0253 OWL_MUX_HW(CMU_SD0CLK, 9, 1),
0254 OWL_GATE_HW(CMU_DEVCLKEN0, 5, 0),
0255 OWL_FACTOR_HW(CMU_SD0CLK, 0, 9, 0, sd_factor_table),
0256 0);
0257
0258 static OWL_COMP_FACTOR(sd1_clk, "sd1_clk", sd_clk_mux_p,
0259 OWL_MUX_HW(CMU_SD1CLK, 9, 1),
0260 OWL_GATE_HW(CMU_DEVCLKEN0, 6, 0),
0261 OWL_FACTOR_HW(CMU_SD1CLK, 0, 9, 0, sd_factor_table),
0262 0);
0263
0264 static OWL_COMP_FACTOR(sd2_clk, "sd2_clk", sd_clk_mux_p,
0265 OWL_MUX_HW(CMU_SD2CLK, 9, 1),
0266 OWL_GATE_HW(CMU_DEVCLKEN0, 7, 0),
0267 OWL_FACTOR_HW(CMU_SD2CLK, 0, 9, 0, sd_factor_table),
0268 0);
0269
0270 static OWL_COMP_DIV(pwm0_clk, "pwm0_clk", pwm_clk_mux_p,
0271 OWL_MUX_HW(CMU_PWM0CLK, 12, 1),
0272 OWL_GATE_HW(CMU_DEVCLKEN1, 23, 0),
0273 OWL_DIVIDER_HW(CMU_PWM0CLK, 0, 10, 0, NULL),
0274 0);
0275
0276 static OWL_COMP_DIV(pwm1_clk, "pwm1_clk", pwm_clk_mux_p,
0277 OWL_MUX_HW(CMU_PWM1CLK, 12, 1),
0278 OWL_GATE_HW(CMU_DEVCLKEN1, 24, 0),
0279 OWL_DIVIDER_HW(CMU_PWM1CLK, 0, 10, 0, NULL),
0280 0);
0281
0282 static OWL_COMP_DIV(pwm2_clk, "pwm2_clk", pwm_clk_mux_p,
0283 OWL_MUX_HW(CMU_PWM2CLK, 12, 1),
0284 OWL_GATE_HW(CMU_DEVCLKEN1, 25, 0),
0285 OWL_DIVIDER_HW(CMU_PWM2CLK, 0, 10, 0, NULL),
0286 0);
0287
0288 static OWL_COMP_DIV(pwm3_clk, "pwm3_clk", pwm_clk_mux_p,
0289 OWL_MUX_HW(CMU_PWM3CLK, 12, 1),
0290 OWL_GATE_HW(CMU_DEVCLKEN1, 26, 0),
0291 OWL_DIVIDER_HW(CMU_PWM3CLK, 0, 10, 0, NULL),
0292 0);
0293
0294 static OWL_COMP_DIV(pwm4_clk, "pwm4_clk", pwm_clk_mux_p,
0295 OWL_MUX_HW(CMU_PWM4CLK, 12, 1),
0296 OWL_GATE_HW(CMU_DEVCLKEN0, 11, 0),
0297 OWL_DIVIDER_HW(CMU_PWM4CLK, 0, 10, 0, NULL),
0298 0);
0299
0300 static OWL_COMP_DIV(pwm5_clk, "pwm5_clk", pwm_clk_mux_p,
0301 OWL_MUX_HW(CMU_PWM5CLK, 12, 1),
0302 OWL_GATE_HW(CMU_DEVCLKEN0, 0, 0),
0303 OWL_DIVIDER_HW(CMU_PWM5CLK, 0, 10, 0, NULL),
0304 0);
0305
0306 static OWL_COMP_PASS(de_clk, "de_clk", de_clk_mux_p,
0307 OWL_MUX_HW(CMU_DECLK, 12, 1),
0308 OWL_GATE_HW(CMU_DEVCLKEN0, 8, 0),
0309 0);
0310
0311 static OWL_COMP_FIXED_FACTOR(i2c0_clk, "i2c0_clk", "ethernet_pll_clk",
0312 OWL_GATE_HW(CMU_DEVCLKEN1, 14, 0),
0313 1, 5, 0);
0314
0315 static OWL_COMP_FIXED_FACTOR(i2c1_clk, "i2c1_clk", "ethernet_pll_clk",
0316 OWL_GATE_HW(CMU_DEVCLKEN1, 15, 0),
0317 1, 5, 0);
0318
0319 static OWL_COMP_FIXED_FACTOR(i2c2_clk, "i2c2_clk", "ethernet_pll_clk",
0320 OWL_GATE_HW(CMU_DEVCLKEN1, 30, 0),
0321 1, 5, 0);
0322
0323 static OWL_COMP_FIXED_FACTOR(i2c3_clk, "i2c3_clk", "ethernet_pll_clk",
0324 OWL_GATE_HW(CMU_DEVCLKEN1, 31, 0),
0325 1, 5, 0);
0326
0327 static OWL_COMP_FIXED_FACTOR(ethernet_clk, "ethernet_clk", "ethernet_pll_clk",
0328 OWL_GATE_HW(CMU_DEVCLKEN1, 22, 0),
0329 1, 20, 0);
0330
0331 static OWL_COMP_DIV(uart0_clk, "uart0_clk", uart_clk_mux_p,
0332 OWL_MUX_HW(CMU_UART0CLK, 16, 1),
0333 OWL_GATE_HW(CMU_DEVCLKEN1, 6, 0),
0334 OWL_DIVIDER_HW(CMU_UART0CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
0335 CLK_IGNORE_UNUSED);
0336
0337 static OWL_COMP_DIV(uart1_clk, "uart1_clk", uart_clk_mux_p,
0338 OWL_MUX_HW(CMU_UART1CLK, 16, 1),
0339 OWL_GATE_HW(CMU_DEVCLKEN1, 7, 0),
0340 OWL_DIVIDER_HW(CMU_UART1CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
0341 CLK_IGNORE_UNUSED);
0342
0343 static OWL_COMP_DIV(uart2_clk, "uart2_clk", uart_clk_mux_p,
0344 OWL_MUX_HW(CMU_UART2CLK, 16, 1),
0345 OWL_GATE_HW(CMU_DEVCLKEN1, 8, 0),
0346 OWL_DIVIDER_HW(CMU_UART2CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
0347 CLK_IGNORE_UNUSED);
0348
0349 static OWL_COMP_DIV(uart3_clk, "uart3_clk", uart_clk_mux_p,
0350 OWL_MUX_HW(CMU_UART3CLK, 16, 1),
0351 OWL_GATE_HW(CMU_DEVCLKEN1, 19, 0),
0352 OWL_DIVIDER_HW(CMU_UART3CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
0353 CLK_IGNORE_UNUSED);
0354
0355 static OWL_COMP_DIV(uart4_clk, "uart4_clk", uart_clk_mux_p,
0356 OWL_MUX_HW(CMU_UART4CLK, 16, 1),
0357 OWL_GATE_HW(CMU_DEVCLKEN1, 20, 0),
0358 OWL_DIVIDER_HW(CMU_UART4CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
0359 CLK_IGNORE_UNUSED);
0360
0361 static OWL_COMP_DIV(uart5_clk, "uart5_clk", uart_clk_mux_p,
0362 OWL_MUX_HW(CMU_UART5CLK, 16, 1),
0363 OWL_GATE_HW(CMU_DEVCLKEN1, 21, 0),
0364 OWL_DIVIDER_HW(CMU_UART5CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
0365 CLK_IGNORE_UNUSED);
0366
0367 static OWL_COMP_DIV(uart6_clk, "uart6_clk", uart_clk_mux_p,
0368 OWL_MUX_HW(CMU_UART6CLK, 16, 1),
0369 OWL_GATE_HW(CMU_DEVCLKEN1, 18, 0),
0370 OWL_DIVIDER_HW(CMU_UART6CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
0371 CLK_IGNORE_UNUSED);
0372
0373 static OWL_COMP_DIV(i2srx_clk, "i2srx_clk", i2s_clk_mux_p,
0374 OWL_MUX_HW(CMU_AUDIOPLL, 24, 1),
0375 OWL_GATE_HW(CMU_DEVCLKEN0, 21, 0),
0376 OWL_DIVIDER_HW(CMU_AUDIOPLL, 20, 4, 0, i2s_div_table),
0377 0);
0378
0379 static OWL_COMP_DIV(i2stx_clk, "i2stx_clk", i2s_clk_mux_p,
0380 OWL_MUX_HW(CMU_AUDIOPLL, 24, 1),
0381 OWL_GATE_HW(CMU_DEVCLKEN0, 20, 0),
0382 OWL_DIVIDER_HW(CMU_AUDIOPLL, 16, 4, 0, i2s_div_table),
0383 0);
0384
0385 static OWL_COMP_DIV(hdmia_clk, "hdmia_clk", i2s_clk_mux_p,
0386 OWL_MUX_HW(CMU_AUDIOPLL, 24, 1),
0387 OWL_GATE_HW(CMU_DEVCLKEN0, 22, 0),
0388 OWL_DIVIDER_HW(CMU_AUDIOPLL, 24, 4, 0, i2s_div_table),
0389 0);
0390
0391 static OWL_COMP_DIV(spdif_clk, "spdif_clk", i2s_clk_mux_p,
0392 OWL_MUX_HW(CMU_AUDIOPLL, 24, 1),
0393 OWL_GATE_HW(CMU_DEVCLKEN0, 23, 0),
0394 OWL_DIVIDER_HW(CMU_AUDIOPLL, 28, 4, 0, i2s_div_table),
0395 0);
0396
0397 static OWL_COMP_DIV(nand_clk, "nand_clk", nand_clk_mux_p,
0398 OWL_MUX_HW(CMU_NANDCCLK, 8, 2),
0399 OWL_GATE_HW(CMU_DEVCLKEN0, 4, 0),
0400 OWL_DIVIDER_HW(CMU_NANDCCLK, 0, 3, 0, nand_div_table),
0401 CLK_SET_RATE_PARENT);
0402
0403 static OWL_COMP_DIV(ecc_clk, "ecc_clk", nand_clk_mux_p,
0404 OWL_MUX_HW(CMU_NANDCCLK, 8, 2),
0405 OWL_GATE_HW(CMU_DEVCLKEN0, 4, 0),
0406 OWL_DIVIDER_HW(CMU_NANDCCLK, 4, 3, 0, nand_div_table),
0407 CLK_SET_RATE_PARENT);
0408
0409 static struct owl_clk_common *s500_clks[] = {
0410 ðernet_pll_clk.common,
0411 &core_pll_clk.common,
0412 &ddr_pll_clk.common,
0413 &dev_pll_clk.common,
0414 &nand_pll_clk.common,
0415 &audio_pll_clk.common,
0416 &display_pll_clk.common,
0417 &dev_clk.common,
0418 &timer_clk.common,
0419 &i2c0_clk.common,
0420 &i2c1_clk.common,
0421 &i2c2_clk.common,
0422 &i2c3_clk.common,
0423 &uart0_clk.common,
0424 &uart1_clk.common,
0425 &uart2_clk.common,
0426 &uart3_clk.common,
0427 &uart4_clk.common,
0428 &uart5_clk.common,
0429 &uart6_clk.common,
0430 &pwm0_clk.common,
0431 &pwm1_clk.common,
0432 &pwm2_clk.common,
0433 &pwm3_clk.common,
0434 &pwm4_clk.common,
0435 &pwm5_clk.common,
0436 &sensor0_clk.common,
0437 &sensor1_clk.common,
0438 &sd0_clk.common,
0439 &sd1_clk.common,
0440 &sd2_clk.common,
0441 &bisp_clk.common,
0442 &ahb_clk.common,
0443 &ahbprediv_clk.common,
0444 &h_clk.common,
0445 &spi0_clk.common,
0446 &spi1_clk.common,
0447 &spi2_clk.common,
0448 &spi3_clk.common,
0449 &rmii_ref_clk.common,
0450 &de_clk.common,
0451 &de1_clk.common,
0452 &de2_clk.common,
0453 &i2srx_clk.common,
0454 &i2stx_clk.common,
0455 &hdmia_clk.common,
0456 &hdmi_clk.common,
0457 &vce_clk.common,
0458 &vde_clk.common,
0459 &spdif_clk.common,
0460 &nand_clk.common,
0461 &ecc_clk.common,
0462 &apb_clk.common,
0463 &dmac_clk.common,
0464 &gpio_clk.common,
0465 &nic_clk.common,
0466 ðernet_clk.common,
0467 };
0468
0469 static struct clk_hw_onecell_data s500_hw_clks = {
0470 .hws = {
0471 [CLK_ETHERNET_PLL] = ðernet_pll_clk.common.hw,
0472 [CLK_CORE_PLL] = &core_pll_clk.common.hw,
0473 [CLK_DDR_PLL] = &ddr_pll_clk.common.hw,
0474 [CLK_NAND_PLL] = &nand_pll_clk.common.hw,
0475 [CLK_DISPLAY_PLL] = &display_pll_clk.common.hw,
0476 [CLK_DEV_PLL] = &dev_pll_clk.common.hw,
0477 [CLK_AUDIO_PLL] = &audio_pll_clk.common.hw,
0478 [CLK_TIMER] = &timer_clk.common.hw,
0479 [CLK_DEV] = &dev_clk.common.hw,
0480 [CLK_DE] = &de_clk.common.hw,
0481 [CLK_DE1] = &de1_clk.common.hw,
0482 [CLK_DE2] = &de2_clk.common.hw,
0483 [CLK_I2C0] = &i2c0_clk.common.hw,
0484 [CLK_I2C1] = &i2c1_clk.common.hw,
0485 [CLK_I2C2] = &i2c2_clk.common.hw,
0486 [CLK_I2C3] = &i2c3_clk.common.hw,
0487 [CLK_I2SRX] = &i2srx_clk.common.hw,
0488 [CLK_I2STX] = &i2stx_clk.common.hw,
0489 [CLK_UART0] = &uart0_clk.common.hw,
0490 [CLK_UART1] = &uart1_clk.common.hw,
0491 [CLK_UART2] = &uart2_clk.common.hw,
0492 [CLK_UART3] = &uart3_clk.common.hw,
0493 [CLK_UART4] = &uart4_clk.common.hw,
0494 [CLK_UART5] = &uart5_clk.common.hw,
0495 [CLK_UART6] = &uart6_clk.common.hw,
0496 [CLK_PWM0] = &pwm0_clk.common.hw,
0497 [CLK_PWM1] = &pwm1_clk.common.hw,
0498 [CLK_PWM2] = &pwm2_clk.common.hw,
0499 [CLK_PWM3] = &pwm3_clk.common.hw,
0500 [CLK_PWM4] = &pwm4_clk.common.hw,
0501 [CLK_PWM5] = &pwm5_clk.common.hw,
0502 [CLK_SENSOR0] = &sensor0_clk.common.hw,
0503 [CLK_SENSOR1] = &sensor1_clk.common.hw,
0504 [CLK_SD0] = &sd0_clk.common.hw,
0505 [CLK_SD1] = &sd1_clk.common.hw,
0506 [CLK_SD2] = &sd2_clk.common.hw,
0507 [CLK_BISP] = &bisp_clk.common.hw,
0508 [CLK_SPI0] = &spi0_clk.common.hw,
0509 [CLK_SPI1] = &spi1_clk.common.hw,
0510 [CLK_SPI2] = &spi2_clk.common.hw,
0511 [CLK_SPI3] = &spi3_clk.common.hw,
0512 [CLK_AHB] = &ahb_clk.common.hw,
0513 [CLK_H] = &h_clk.common.hw,
0514 [CLK_AHBPREDIV] = &ahbprediv_clk.common.hw,
0515 [CLK_RMII_REF] = &rmii_ref_clk.common.hw,
0516 [CLK_HDMI_AUDIO] = &hdmia_clk.common.hw,
0517 [CLK_HDMI] = &hdmi_clk.common.hw,
0518 [CLK_VDE] = &vde_clk.common.hw,
0519 [CLK_VCE] = &vce_clk.common.hw,
0520 [CLK_SPDIF] = &spdif_clk.common.hw,
0521 [CLK_NAND] = &nand_clk.common.hw,
0522 [CLK_ECC] = &ecc_clk.common.hw,
0523 [CLK_APB] = &apb_clk.common.hw,
0524 [CLK_DMAC] = &dmac_clk.common.hw,
0525 [CLK_GPIO] = &gpio_clk.common.hw,
0526 [CLK_NIC] = &nic_clk.common.hw,
0527 [CLK_ETHERNET] = ðernet_clk.common.hw,
0528 },
0529 .num = CLK_NR_CLKS,
0530 };
0531
0532 static const struct owl_reset_map s500_resets[] = {
0533 [RESET_DMAC] = { CMU_DEVRST0, BIT(0) },
0534 [RESET_NORIF] = { CMU_DEVRST0, BIT(1) },
0535 [RESET_DDR] = { CMU_DEVRST0, BIT(2) },
0536 [RESET_NANDC] = { CMU_DEVRST0, BIT(3) },
0537 [RESET_SD0] = { CMU_DEVRST0, BIT(4) },
0538 [RESET_SD1] = { CMU_DEVRST0, BIT(5) },
0539 [RESET_PCM1] = { CMU_DEVRST0, BIT(6) },
0540 [RESET_DE] = { CMU_DEVRST0, BIT(7) },
0541 [RESET_LCD] = { CMU_DEVRST0, BIT(8) },
0542 [RESET_SD2] = { CMU_DEVRST0, BIT(9) },
0543 [RESET_DSI] = { CMU_DEVRST0, BIT(10) },
0544 [RESET_CSI] = { CMU_DEVRST0, BIT(11) },
0545 [RESET_BISP] = { CMU_DEVRST0, BIT(12) },
0546 [RESET_KEY] = { CMU_DEVRST0, BIT(14) },
0547 [RESET_GPIO] = { CMU_DEVRST0, BIT(15) },
0548 [RESET_AUDIO] = { CMU_DEVRST0, BIT(17) },
0549 [RESET_PCM0] = { CMU_DEVRST0, BIT(18) },
0550 [RESET_VDE] = { CMU_DEVRST0, BIT(19) },
0551 [RESET_VCE] = { CMU_DEVRST0, BIT(20) },
0552 [RESET_GPU3D] = { CMU_DEVRST0, BIT(22) },
0553 [RESET_NIC301] = { CMU_DEVRST0, BIT(23) },
0554 [RESET_LENS] = { CMU_DEVRST0, BIT(26) },
0555 [RESET_PERIPHRESET] = { CMU_DEVRST0, BIT(27) },
0556 [RESET_USB2_0] = { CMU_DEVRST1, BIT(0) },
0557 [RESET_TVOUT] = { CMU_DEVRST1, BIT(1) },
0558 [RESET_HDMI] = { CMU_DEVRST1, BIT(2) },
0559 [RESET_HDCP2TX] = { CMU_DEVRST1, BIT(3) },
0560 [RESET_UART6] = { CMU_DEVRST1, BIT(4) },
0561 [RESET_UART0] = { CMU_DEVRST1, BIT(5) },
0562 [RESET_UART1] = { CMU_DEVRST1, BIT(6) },
0563 [RESET_UART2] = { CMU_DEVRST1, BIT(7) },
0564 [RESET_SPI0] = { CMU_DEVRST1, BIT(8) },
0565 [RESET_SPI1] = { CMU_DEVRST1, BIT(9) },
0566 [RESET_SPI2] = { CMU_DEVRST1, BIT(10) },
0567 [RESET_SPI3] = { CMU_DEVRST1, BIT(11) },
0568 [RESET_I2C0] = { CMU_DEVRST1, BIT(12) },
0569 [RESET_I2C1] = { CMU_DEVRST1, BIT(13) },
0570 [RESET_USB3] = { CMU_DEVRST1, BIT(14) },
0571 [RESET_UART3] = { CMU_DEVRST1, BIT(15) },
0572 [RESET_UART4] = { CMU_DEVRST1, BIT(16) },
0573 [RESET_UART5] = { CMU_DEVRST1, BIT(17) },
0574 [RESET_I2C2] = { CMU_DEVRST1, BIT(18) },
0575 [RESET_I2C3] = { CMU_DEVRST1, BIT(19) },
0576 [RESET_ETHERNET] = { CMU_DEVRST1, BIT(20) },
0577 [RESET_CHIPID] = { CMU_DEVRST1, BIT(21) },
0578 [RESET_USB2_1] = { CMU_DEVRST1, BIT(22) },
0579 [RESET_WD0RESET] = { CMU_DEVRST1, BIT(24) },
0580 [RESET_WD1RESET] = { CMU_DEVRST1, BIT(25) },
0581 [RESET_WD2RESET] = { CMU_DEVRST1, BIT(26) },
0582 [RESET_WD3RESET] = { CMU_DEVRST1, BIT(27) },
0583 [RESET_DBG0RESET] = { CMU_DEVRST1, BIT(28) },
0584 [RESET_DBG1RESET] = { CMU_DEVRST1, BIT(29) },
0585 [RESET_DBG2RESET] = { CMU_DEVRST1, BIT(30) },
0586 [RESET_DBG3RESET] = { CMU_DEVRST1, BIT(31) },
0587 };
0588
0589 static struct owl_clk_desc s500_clk_desc = {
0590 .clks = s500_clks,
0591 .num_clks = ARRAY_SIZE(s500_clks),
0592
0593 .hw_clks = &s500_hw_clks,
0594
0595 .resets = s500_resets,
0596 .num_resets = ARRAY_SIZE(s500_resets),
0597 };
0598
0599 static int s500_clk_probe(struct platform_device *pdev)
0600 {
0601 struct owl_clk_desc *desc;
0602 struct owl_reset *reset;
0603 int ret;
0604
0605 desc = &s500_clk_desc;
0606 owl_clk_regmap_init(pdev, desc);
0607
0608 reset = devm_kzalloc(&pdev->dev, sizeof(*reset), GFP_KERNEL);
0609 if (!reset)
0610 return -ENOMEM;
0611
0612 reset->rcdev.of_node = pdev->dev.of_node;
0613 reset->rcdev.ops = &owl_reset_ops;
0614 reset->rcdev.nr_resets = desc->num_resets;
0615 reset->reset_map = desc->resets;
0616 reset->regmap = desc->regmap;
0617
0618 ret = devm_reset_controller_register(&pdev->dev, &reset->rcdev);
0619 if (ret)
0620 dev_err(&pdev->dev, "Failed to register reset controller\n");
0621
0622 return owl_clk_probe(&pdev->dev, desc->hw_clks);
0623 }
0624
0625 static const struct of_device_id s500_clk_of_match[] = {
0626 { .compatible = "actions,s500-cmu", },
0627 { }
0628 };
0629
0630 static struct platform_driver s500_clk_driver = {
0631 .probe = s500_clk_probe,
0632 .driver = {
0633 .name = "s500-cmu",
0634 .of_match_table = s500_clk_of_match,
0635 },
0636 };
0637
0638 static int __init s500_clk_init(void)
0639 {
0640 return platform_driver_register(&s500_clk_driver);
0641 }
0642 core_initcall(s500_clk_init);
