clk/actions/owl-pll.h

0001 /* SPDX-License-Identifier: GPL-2.0+ */
0002 //
0003 // OWL pll clock driver
0004 //
0005 // Copyright (c) 2014 Actions Semi Inc.
0006 // Author: David Liu <liuwei@actions-semi.com>
0007 //
0008 // Copyright (c) 2018 Linaro Ltd.
0009 // Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
0010
0011 #ifndef _OWL_PLL_H_
0012 #define _OWL_PLL_H_
0013
0014 #include "owl-common.h"
0015
0016 #define OWL_PLL_DEF_DELAY   50
0017
0018 /* last entry should have rate = 0 */
0019 struct clk_pll_table {
0020     unsigned int        val;
0021     unsigned long       rate;
0022 };
0023
0024 struct owl_pll_hw {
0025     u32         reg;
0026     u32         bfreq;
0027     u8          bit_idx;
0028     u8          shift;
0029     u8          width;
0030     u8          min_mul;
0031     u8          max_mul;
0032     u8          delay;
0033     const struct clk_pll_table *table;
0034 };
0035
0036 struct owl_pll {
0037     struct owl_pll_hw   pll_hw;
0038     struct owl_clk_common   common;
0039 };
0040
0041 #define OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift,          \
0042            _width, _min_mul, _max_mul, _delay, _table)      \
0043     {                               \
0044         .reg        = _reg,                 \
0045         .bfreq      = _bfreq,               \
0046         .bit_idx    = _bit_idx,             \
0047         .shift      = _shift,               \
0048         .width      = _width,               \
0049         .min_mul    = _min_mul,             \
0050         .max_mul    = _max_mul,             \
0051         .delay      = _delay,               \
0052         .table      = _table,               \
0053     }
0054
0055 #define OWL_PLL(_struct, _name, _parent, _reg, _bfreq, _bit_idx,    \
0056         _shift, _width, _min_mul, _max_mul, _table, _flags) \
0057     struct owl_pll _struct = {                  \
0058         .pll_hw = OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift,    \
0059                      _width, _min_mul, _max_mul,    \
0060                      OWL_PLL_DEF_DELAY, _table),    \
0061         .common = {                     \
0062             .regmap = NULL,                 \
0063             .hw.init = CLK_HW_INIT(_name,           \
0064                            _parent,         \
0065                            &owl_pll_ops,        \
0066                            _flags),         \
0067         },                          \
0068     }
0069
0070 #define OWL_PLL_NO_PARENT(_struct, _name, _reg, _bfreq, _bit_idx,   \
0071         _shift, _width, _min_mul, _max_mul, _table, _flags) \
0072     struct owl_pll _struct = {                  \
0073         .pll_hw = OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift,    \
0074                      _width, _min_mul, _max_mul,    \
0075                      OWL_PLL_DEF_DELAY, _table),    \
0076         .common = {                     \
0077             .regmap = NULL,                 \
0078             .hw.init = CLK_HW_INIT_NO_PARENT(_name,     \
0079                            &owl_pll_ops,        \
0080                            _flags),         \
0081         },                          \
0082     }
0083
0084 #define OWL_PLL_NO_PARENT_DELAY(_struct, _name, _reg, _bfreq, _bit_idx, \
0085         _shift, _width, _min_mul, _max_mul, _delay, _table, \
0086         _flags)                         \
0087     struct owl_pll _struct = {                  \
0088         .pll_hw = OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift,    \
0089                      _width, _min_mul,  _max_mul,   \
0090                      _delay, _table),           \
0091         .common = {                     \
0092             .regmap = NULL,                 \
0093             .hw.init = CLK_HW_INIT_NO_PARENT(_name,     \
0094                            &owl_pll_ops,        \
0095                            _flags),         \
0096         },                          \
0097     }
0098
0099 #define mul_mask(m)     ((1 << ((m)->width)) - 1)
0100
0101 static inline struct owl_pll *hw_to_owl_pll(const struct clk_hw *hw)
0102 {
0103     struct owl_clk_common *common = hw_to_owl_clk_common(hw);
0104
0105     return container_of(common, struct owl_pll, common);
0106 }
0107
0108 extern const struct clk_ops owl_pll_ops;
0109
0110 #endif /* _OWL_PLL_H_ */