clk/actions/owl-mux.c

0001 // SPDX-License-Identifier: GPL-2.0+
0002 //
0003 // OWL mux clock driver
0004 //
0005 // Copyright (c) 2014 Actions Semi Inc.
0006 // Author: David Liu <liuwei@actions-semi.com>
0007 //
0008 // Copyright (c) 2018 Linaro Ltd.
0009 // Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
0010
0011 #include <linux/clk-provider.h>
0012 #include <linux/regmap.h>
0013
0014 #include "owl-mux.h"
0015
0016 u8 owl_mux_helper_get_parent(const struct owl_clk_common *common,
0017                  const struct owl_mux_hw *mux_hw)
0018 {
0019     u32 reg;
0020     u8 parent;
0021
0022     regmap_read(common->regmap, mux_hw->reg, &reg);
0023     parent = reg >> mux_hw->shift;
0024     parent &= BIT(mux_hw->width) - 1;
0025
0026     return parent;
0027 }
0028
0029 static u8 owl_mux_get_parent(struct clk_hw *hw)
0030 {
0031     struct owl_mux *mux = hw_to_owl_mux(hw);
0032
0033     return owl_mux_helper_get_parent(&mux->common, &mux->mux_hw);
0034 }
0035
0036 int owl_mux_helper_set_parent(const struct owl_clk_common *common,
0037                   struct owl_mux_hw *mux_hw, u8 index)
0038 {
0039     u32 reg;
0040
0041     regmap_read(common->regmap, mux_hw->reg, &reg);
0042     reg &= ~GENMASK(mux_hw->width + mux_hw->shift - 1, mux_hw->shift);
0043     regmap_write(common->regmap, mux_hw->reg,
0044             reg | (index << mux_hw->shift));
0045
0046     return 0;
0047 }
0048
0049 static int owl_mux_set_parent(struct clk_hw *hw, u8 index)
0050 {
0051     struct owl_mux *mux = hw_to_owl_mux(hw);
0052
0053     return owl_mux_helper_set_parent(&mux->common, &mux->mux_hw, index);
0054 }
0055
0056 const struct clk_ops owl_mux_ops = {
0057     .get_parent = owl_mux_get_parent,
0058     .set_parent = owl_mux_set_parent,
0059     .determine_rate = __clk_mux_determine_rate,
0060 };